CN115279686A - 防止微型装置侧壁上的电极中断 - Google Patents

防止微型装置侧壁上的电极中断 Download PDF

Info

Publication number
CN115279686A
CN115279686A CN202180018187.6A CN202180018187A CN115279686A CN 115279686 A CN115279686 A CN 115279686A CN 202180018187 A CN202180018187 A CN 202180018187A CN 115279686 A CN115279686 A CN 115279686A
Authority
CN
China
Prior art keywords
polymer
sidewall
conductive layer
film
sidewalls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180018187.6A
Other languages
English (en)
Inventor
格拉姆雷扎·查济
埃桑诺拉·法蒂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vuereal Inc
Original Assignee
Vuereal Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vuereal Inc filed Critical Vuereal Inc
Publication of CN115279686A publication Critical patent/CN115279686A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00611—Processes for the planarisation of structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/04—Electrodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0118—Processes for the planarization of structures
    • B81C2201/0119—Processes for the planarization of structures involving only addition of materials, i.e. additive planarization
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0118—Processes for the planarization of structures
    • B81C2201/0122—Selective addition
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0176—Chemical vapour Deposition
    • B81C2201/0178—Oxidation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0176—Chemical vapour Deposition
    • B81C2201/018—Plasma polymerization, i.e. monomer or polymer deposition
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0183—Selective deposition
    • B81C2201/0188—Selective deposition techniques not provided for in B81C2201/0184 - B81C2201/0187

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开涉及在处理微型装置时蚀刻和处理侧壁的过程。一个方面是用聚合物填充装置壁凹部。本公开涉及一种方法和装置，其结构用于蚀刻和处理侧壁的该过程。使用蚀刻、涂覆和固化的该方法。

Description

防止微型装置侧壁上的电极中断
技术领域
本发明涉及在处理微型装置时蚀刻和处理侧壁的过程。
发明内容
本发明涉及一种使微型装置的侧壁平坦化的方法，该方法包括：用聚合物涂覆微型装置；以及通过干蚀刻工艺去除聚合物并将聚合物留在侧壁凹部中，以使侧壁平坦化。
附图说明
通过阅读以下详细描述并参考附图，本公开的前述和其它优点将变得显而易见。
图1示出了装置100的示例，其中壁具有凹部。
图2A示出了涂覆装置的壁的聚合物。
图2B示出了通过干蚀刻回蚀的聚合物。
图2C示出了在干蚀刻之后壁上的导电层。
图3A示出了涂覆以覆盖装置的壁的聚合物材料，其中在聚合物的至少一部分与壁之间存在(多个)膜。
图3B示出了蚀刻工艺之后的聚合物。
图3C示出了在蚀刻之后在壁上形成导电层。
图4示出了壁在装置层中形成VIA的位置。
虽然本公开易于进行各种修改和替代形式，但具体实施例或实施方式已经通过举例的方式在附图中示出并且将在本文中详细描述。然而，应该理解，本公开不旨在限于所公开的特定形式。相反，本公开内容将涵盖落入由所附权利要求限定的本发明的精神和范围内的所有修改、等同形式和替代形式。
具体实施方式
在本说明书中，术语“装置”和“微型装置”可互换使用。然而，本领域技术人员清楚，这里描述的实施方案与装置尺寸无关。
在处理微型装置期间，侧壁(或VIA的内壁)可以具有一些凹部。这可作为蚀刻或处理侧壁的一部分发生。
如果导电层需要静置(覆盖)于壁上，则凹部可能引起中断，且因此导电层可能断开。
图1示出了装置100的示例，其中壁具有凹部102。导电层104和106由于此凹部102而断开。
取决于凹部的深度，可能难以用薄膜沉积工艺填充该凹部。
本发明将用聚合物填充装置壁凹部。聚合物层覆盖壁。聚合物层也可以被旋涂或印刷(或其它方法)。
在聚合物覆盖壁之后，壁上存在过量的材料。通过干蚀刻的过程去除此过量的材料，以将聚合物留在凹部中。在干蚀刻之后，聚合物薄层可能仍留在壁上。此薄层降低了凹部边缘的锐度，且因此使得对将沉积(或形成)于壁上的后续膜的更好覆盖。膜可以是导电的、电介质的或其组合。
在另一种情况下，诸如电介质、导电材料等其它材料可用于填充凹部。
图2(包括图2A、2B及2C)突出显示填充凹部的方法。在图2A中，聚合物材料208经涂覆(或由其它方式形成)以覆盖装置200的壁。聚合物可在涂覆之后固化。固化(基于热或基于光)可以具有回流周期，其中聚合物可以在硬固化之前填充空间。回流周期是在光温下固化的一种形式，其中材料足够软以使得其可以移动到小空间。通过干蚀刻工艺回蚀聚合物(图2B)。干蚀刻工艺可以是反应离子蚀刻(RIE)、离子铣削或电感耦合等离子体(ICP)RIE。此过程是相当定向的，且因此，材料将保持在凹部区域202内部。在蚀刻工艺之后，导电层204可形成在壁上，如图2C所示。
图3(包括图3A、3B及3C)突出显示在凹部平坦化之前另一膜310(或膜的组合)形成在壁上的情况。
在图3A中，聚合物材料308经涂覆(或由其它方式形成)以覆盖装置300的壁，其中在聚合物308的至少一部分与壁之间存在膜310(或组合膜)。聚合物(或其它材料)可在涂覆之后固化。固化可以具有回流周期，其中聚合物可以在硬固化之前填充空间。
在图3B中，通过干蚀刻工艺对覆盖其中存在膜310的装置300的壁的聚合物进行回蚀。干蚀刻工艺可以是RIE、离子铣削或ICP。此过程是相当定向的，且因此，材料将保持在凹部区域302内部。
在蚀刻工艺之后，导电层304可形成在壁上，如图3C所示。膜310可以是电介质的或导电的或其组合。在一种情况下，膜310中的至少一个膜可以是蚀刻聚合物的掩模。此层将在聚合物308的回蚀期间保护装置300。膜310可以覆盖装置的壁或表面。也可以去除膜310。
图4示出了壁在装置400层中形成VIA的示例。在此，根据上文所描述的方法用聚合物(或其它膜)填充凹部402。在填充凹部402之前，可以存在膜410(或膜的组合)。在填充凹部402之后，沉积另一膜404。在此，膜404可以是导电的，以将信号从通孔的顶部带到底部。VIA可以位于底部并且耦合到另一膜。
方法方面
本发明公开了一种使微型装置的侧壁平坦化的方法。该方法包括：用聚合物涂覆微型装置；以及通过干蚀刻工艺去除聚合物，从而使聚合物留在侧壁凹部中以使侧壁平坦化。在此，聚合物被固化。而且，导电层可以覆盖平坦化的侧壁的一部分，并且导电层与平坦化的侧壁之间可以存在另一电介质，其中该电介质在平坦化之前或之后放置。此外，固化可以是基于热或基于光的，并且固化可以具有回流周期。在一种情况下，干蚀刻工艺可以是RIE、离子铣削或ICP。另外，可以在聚合物的一部分与侧壁之间存在膜。在一个实例中，组合膜可以存在于聚合物的一部分与侧壁之间，其中附加膜充当干蚀刻工艺的掩模。在此，组合膜可以充当干蚀刻工艺的掩模，并且膜包括电介质和导电层。此外，附加膜可以是导电层或电介质。在另一方面，侧壁是VIA的壁，其中导电层将信号从VIA的顶部带到底部。
本发明的一个或多个实施方式的前述描述是出于说明和描述的目的而呈现的。并不意在穷举或将本发明限制为所公开的精确形式。根据上述教示，许多修改和变化是可能的。本发明的范围旨在不受此详细描述的限制，而是由所附的权利要求限制。

Claims (16)

1.一种使微型装置的侧壁平坦化的方法，所述方法包括：
用聚合物涂覆微型装置；以及
通过干蚀刻工艺去除所述聚合物并将所述聚合物留在侧壁凹部中，以使所述侧壁平坦化。
2.根据权利要求1所述的方法，其中所述聚合物被固化。
3.根据权利要求1所述的方法，其中导电层覆盖平坦化的侧壁的一部分。
4.根据权利要求1所述的方法，其中所述导电层与所述平坦化的侧壁之间存在另一电介质。
5.根据权利要求4所述的方法，其中所述电介质在所述平坦化之前或之后放置。
6.根据权利要求2所述的方法，其中所述固化是基于热或基于光的。
7.根据权利要求2所述的方法，其中所述固化具有回流周期。
8.根据权利要求1所述的方法，其中所述干蚀刻工艺可以是RIE、离子铣削或ICP。
9.根据权利要求1所述的方法，其中在所述聚合物的一部分与所述侧壁之间存在附加膜。
10.根据权利要求1所述的方法，其中在所述聚合物的所述部分与所述侧壁之间存在组合膜。
11.根据权利要求9所述的方法，其中所述附加膜充当所述干蚀刻工艺的掩模。
12.根据权利要求10所述的方法，其中组合膜充当所述干蚀刻工艺的掩模。
13.根据权利要求9所述的方法，其中所述附加膜是导电层或电介质。
14.根据权利要求10所述的方法，其中所述组合膜包括电介质和导电层。
15.根据权利要求1所述的方法，其中所述侧壁是VIA的壁。
16.根据权利要求15所述的方法，其中所述导电层将信号从所述VIA的顶部带到底部。
CN202180018187.6A 2020-03-23 2021-03-23 防止微型装置侧壁上的电极中断 Pending CN115279686A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202062993477P 2020-03-23 2020-03-23
US62/993,477 2020-03-23
PCT/CA2021/050380 WO2021189136A1 (en) 2020-03-23 2021-03-23 Preventing electrode discontinuation on microdevice sidewall

Publications (1)

Publication Number Publication Date
CN115279686A true CN115279686A (zh) 2022-11-01

Family

ID=77890103

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180018187.6A Pending CN115279686A (zh) 2020-03-23 2021-03-23 防止微型装置侧壁上的电极中断

Country Status (3)

Country Link
US (1) US20230154790A1 (zh)
CN (1) CN115279686A (zh)
WO (1) WO2021189136A1 (zh)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849558B2 (en) * 2002-05-22 2005-02-01 The Board Of Trustees Of The Leland Stanford Junior University Replication and transfer of microstructures and nanostructures
CN102386089B (zh) * 2010-09-03 2013-06-12 中芯国际集成电路制造(上海)有限公司 制备半导体器件结构的方法
US9035279B2 (en) * 2013-07-08 2015-05-19 LuxVue Technology Corporation Micro device with stabilization post
WO2018096455A1 (en) * 2016-11-25 2018-05-31 Vuereal Inc. Integration of micro-devices into system substrate

Also Published As

Publication number Publication date
WO2021189136A1 (en) 2021-09-30
US20230154790A1 (en) 2023-05-18

Similar Documents

Publication Publication Date Title
KR100621255B1 (ko) 얕은트랜치분리를위한갭충전및평탄화방법
US6734084B1 (en) Method of manufacturing a semiconductor device with recesses using anodic oxide
US6828646B2 (en) Isolating trench and manufacturing process
US9029212B2 (en) MEMS pressure sensors and fabrication method thereof
US9875965B2 (en) Semiconductor device
JPH11162987A (ja) 非コンフォーマルな膜の平坦化法
EP3279932B1 (en) A semiconductor device and manufacture thereof
US10712660B2 (en) Template for imprint lithography including a recession and an apparatus and method of using the template
US5773361A (en) Process of making a microcavity structure and applications thereof
CN115279686A (zh) 防止微型装置侧壁上的电极中断
US11018218B2 (en) Narrow gap device with parallel releasing structure
US7541255B2 (en) Method for manufacturing semiconductor device
US20060270185A1 (en) Method of forming isolation film of semiconductor device
US6503848B1 (en) Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography window
US10049926B2 (en) Metal lines having etch-bias independent height
JP2004077432A (ja) 可動部を有する半導体センサ
KR100443322B1 (ko) 반도체 장치의 제조 방법
CN111295742B (zh) 用于减少浅沟槽隔离中的锥体形成的选择性蚀刻
US6719918B2 (en) Method of reducing notching during reactive ion etching
CN108257910A (zh) 浅沟槽隔离沟槽的制作方法
TWI262558B (en) Planarization method of spin-on material layer and manufacturing method of photoresist layer
KR102265096B1 (ko) 함몰부를 포함하는 임프린트 리소그래피용 템플레이트, 템플레이트를 이용하는 장치, 및 물품 제조 방법
US20070054471A1 (en) Alignment mark and method of forming the same
CN113830726A (zh) 一种半导体器件的制造方法和半导体器件
US6613648B1 (en) Shallow trench isolation using TEOS cap and polysilicon pullback

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination