CN115274647A - 用于管芯平铺应用的小芯片优先架构 - Google Patents
用于管芯平铺应用的小芯片优先架构 Download PDFInfo
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- CN115274647A CN115274647A CN202210661435.5A CN202210661435A CN115274647A CN 115274647 A CN115274647 A CN 115274647A CN 202210661435 A CN202210661435 A CN 202210661435A CN 115274647 A CN115274647 A CN 115274647A
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Abstract
本文公开的实施例包括电子封装和形成这样的电子封装的方法。在实施例中,电子封装包括:模制层,该模制层具有第一表面和与该第一表面相对的第二表面;和嵌入模制层中的多个第一管芯。在实施例中,多个第一管芯中的每个具有与模制层的第一表面大致共面的表面。在实施例中,电子封装进一步包括嵌入模制层中的第二管芯。在实施例中,第二管芯被安置在多个第一管芯与模制层的第二表面之间。
Description
技术领域
本公开的实施例涉及电子封装,并且更特定地,涉及具有第一管芯和第一管芯上方的第二管芯的多管芯电子封装以及形成这样的电子封装的方法。
背景技术
针对规格(form factor)小型化的需求和针对高性能的增加的集成度正在推动半导体行业中的精密封装方法。嵌入式多管芯互连桥(EMIB)架构所实现的管芯分区虑及了小规格的小型化和高性能而没有用其他方法看到的成品率问题。然而,这样的封装架构需要精细的管芯到管芯互连,其由于差的凸点(bump)厚度变化(BTV)(例如,由于翘曲(warpage)、对组装工具的限制等)而易受到成品率问题影响。
还已经提出了在细管芯与传统的有机衬底之间使用包含粗节点管芯的补片(patch)的备选方法。这样的架构虑及在不同过程节点(process node)处形成的管芯集成。该架构也有若干限制。特别地,高级节点管芯在封装形成的后期阶段使用热压接合(TCB)附接到较低级节点管芯。因此,管芯放置精度受到TCB工具集(toolset)和翘曲的限制。后期阶段中的TCB附接对补片施加严格的翘曲限制并且推动明显降低的TCB窗口。此外,提出的架构还依赖于附接了高级节点管芯之后的第二载体附接以便实现中级互连(MLI)和封装侧凸点(PSB)。这导致额外的成品率损失。
附图说明
图1A是根据实施例的多管芯封装的横截面图示,该多管芯封装包括采用面对面配置耦合到第二管芯的多个第一管芯。
图1B是根据实施例的多管芯封装的横截面图示,该多管芯封装包括采用面对面配置耦合到多个第二管芯的多个第一管芯,其中这些第二管芯通过嵌入式桥而耦合在一起。
图2A是根据实施例的多管芯封装的横截面图示,该多管芯封装包括耦合到第二管芯的多个第一管芯,其中在第一管芯与第二管芯之间具有阻焊层(solder resist layer)。
图2B是根据实施例的多管芯封装的横截面图示,该多管芯封装包括耦合到多个第二管芯的多个第一管芯,其中在第一管芯与第二管芯之间具有阻焊层,其中第二管芯通过嵌入式桥而耦合在一起。
图3A是根据实施例安装到载体衬底的多个第一管芯的横截面图示。
图3B是根据实施例在多个第一管芯上方设置模制层之后的横截面图示。
图3C是根据实施例在模制层上方形成柱之后的横截面图示。
图3D是根据实施例在第二管芯附接到第一管芯之后的横截面图示。
图3E是根据实施例在第二管芯上方设置模制层之后的横截面图示。
图3F是根据实施例在模制层上方形成柱之后的横截面图示。
图3G是根据实施例在模制层上方形成重分布层(RDL)之后的横截面图示。
图3H是根据实施例在RDL上方设置阻焊层并且使该阻焊层图案化之后的横截面图示。
图3I是根据实施例在通过阻焊层设置中级互连(MLI)之后的横截面图示。
图3J是根据实施例在移除载体之后的横截面图示。
图4A是根据实施例在多个第二管芯附接到多个第一管芯之后的电子封装的横截面图示。
图4B是根据实施例在第二管芯上方设置模制层之后的横截面图示。
图4C是根据实施例在跨第二管芯附接桥之后的横截面图示。
图4D是根据实施例在第二管芯上方形成模制层和RDL之后的横截面图示。
图4E是根据实施例在移除载体之后的横截面图示。
图5A是根据实施例具有种子(seed)层的第一载体的横截面图示。
图5B是根据实施例在种子层上方设置阻焊层并且使该阻焊层图案化之后的横截面图示。
图5C是根据实施例在将互连设置到阻焊开口中之后的横截面图示。
图5D是根据实施例在第一管芯附接到互连之后的横截面图示。
图5E是根据实施例在移除第一载体并且将第二载体附接到封装之后的横截面图示。
图5F是根据实施例在第二管芯附接到第一管芯之后的横截面图示。
图5G是根据实施例在第二管芯上方形成RDL并且移除第二载体之后的横截面图示。
图6A是根据实施例具有附接到第一管芯的多个第二管芯的封装的横截面图示。
图6B是根据实施例在跨第二管芯附接桥之后的横截面图示。
图6C是根据实施例在第二管芯上形成RDL并且移除第二载体之后的横截面图示。
图7是根据实施例包括多芯片封装的电子系统的横截面图示。
图8是根据实施例构建的计算设备的示意图。
具体实施方式
本文描述了根据各种实施例具有第一管芯和第一管芯上方的第二管芯的多管芯电子封装以及形成这样的电子封装的方法。在下面的描述中,将使用本领域内技术人员通常采用的术语来描述说明性实现的各个方面以向本领域其他技术人员传达它们的工作实质。然而,本领域技术人员将明白,本发明可以仅用所描述的方面中的一些来实践。为了说明的目的,阐述特定数字、材料和配置以便提供对说明性实施例的透彻理解。然而,本领域技术人员将明白,本发明可以在没有特定细节的情况下实践。在其他实例中,省略或简化众所周知的特征以免混淆说明性实现。
各种操作将进而采用对于理解本发明最有帮助的方式描述为多个分立操作,然而,描述的顺序不应该解释为意指这些操作必定依赖于顺序。特别地,这些操作不需要按呈现的顺序执行。
如上文指出的,多管芯封装提供了持续缩放到较小规格同时还获得高级性能的能力。然而,当前的架构受到组装问题的困扰,这些组装问题对成品率产生负面影响。因此,本文公开的实施例包括下述多管芯封装:其利用使翘曲和对准问题最小化的工艺流程来组装。
特别地,本文公开的实施例包括高级过程节点处的多个第一管芯和低级过程节点处的一个或多个第二管芯。在实施例中,第一节点在封装组装的初始阶段被放置到封装中。提早放置第一管芯具有若干优势。一方面,放置过程可以用管芯安装器(mounter)代替热压接合(TCB)工具来实现。管芯安装器具有一定的放置精度,其比TCB工具精确一个数量级。另外,在第一管芯的早期放置期间翘曲更少。
在实施例中,将低级节点第二管芯附接到第一管芯也具有较大的TCB窗口。因为封装仍附接到在原处(in place)的尺寸稳定的(例如,玻璃)载体上的第一管芯,这导致低翘曲,所以TCB窗口被改进。另外,实施例虑及移除载体之前的中级互连(MLI)和PSB形成。因此,避免形成这样的特征另外所需要的额外载体。
现在参考图1A,示出根据实施例的多管芯电子封装100的横截面图示。在实施例中,电子封装100可以包括模制层120,在该模制层中嵌入多个管芯。例如,多个第一管芯107以及第二管芯110可以嵌入模制层120中。虽然模制层120被示为包括分立层,但要意识到在模制层120的不同部分之间可能没有可辨别边界存在。在实施例中,模制层120可以包括第一表面109和与该第一表面109相对的第二表面127。模制层120可以包括用于电子封装的任何适合的材料,诸如环氧树脂或类似物。
在实施例中,多个第一管芯107可以嵌入模制层120中使得第一管芯107的表面108与模制层120的第一表面109大致共面。在实施例中,表面108可以称为第一管芯107的背面。因为使背面108暴露,所以改进了电子封装100的热管理。在一些实施例中,散热器或其他散热方案(thermal solution)可以附接到第一管芯107的背面108。
在实施例中,多个高速输入/输出HSIO管芯112也可以嵌入模制层120中。HSIO管芯112可以与第一管芯107大致共面。也就是说,HSIO管芯112的背面113可以与模制层120的第一表面109以及第一管芯107的背面108大致共面。
在实施例中,多个第一管芯107可以电耦合到嵌入模制层120中的第二管芯110。在实施例中,第二管芯110被安置在第一管芯107的有源表面106与模制层120的第二表面127之间。第二管芯110可以具有有源表面114和背面115。在实施例中,第二管芯110和第一管芯107采用面对面配置来布置。也就是说,第二管芯110的有源表面114面对第一管芯107的有源表面106。在实施例中,第一管芯107可以在第一过程节点处制造并且第二管芯110可以在第二过程节点处制造,该第二过程节点不如第一过程节点高级。
在实施例中,第一管芯107可以利用第一级互连(FLI)118电耦合到第二管芯110。例如,第一管芯107的衬垫117可以通过FLI 118而电耦合到第二管芯110的衬垫119,该FLI118诸如可控塌陷芯片连接(controlled collapse chip connection,C4)凸点或类似物。在实施例中,第二管芯110的衬垫119和FLI 118可以被底部填充(underfill)材料111环绕,并且第一管芯107的衬垫117可以被模制层120环绕。
在特定实施例中,第一管芯107可以通过第二管芯110彼此互连。也就是说,第二管芯110可以充当补片以在第一管芯107中的每个之间提供互连。在一些实施例中,第一管芯107全部可以彼此大致相似。在其他实施例中,第一管芯107可以包括不同功能性。在图示的实施例中,示出四个第一管芯107。然而,要意识到在电子封装100中可以使用任何数量的第一管芯107(例如,两个或更多)的阵列。
在实施例中,HSIO管芯112还可以电耦合到第二管芯110。例如,HSIO管芯112可以采用与第一管芯107连接到第二管芯110大致相同的方式通过FLI 118电耦合到第二管芯110上的衬垫119。在实施例中,第二管芯110可以在第一管芯107与HSIO管芯112之间提供互连。
在实施例中,包括导电迹线、衬垫125和通孔124的多个重分布层(RDL)可以嵌入模制层120中。RDL可以在模制层120的第二表面127上方将第一管芯107、第二管芯110和HSIO管芯112的表面电耦合到中级互连(MLI)128。在实施例中, MLI 128可以通过阻焊剂122被安置在开口中,如本领域中已知的那样。
现在参考图1B,示出根据额外实施例的电子封装101的横截面图示。在实施例中,除了包括多个第二管芯110之外,电子封装101可以与在上文针对图1A描述的电子封装100大致相似。在图示的实施例中,示出两个第二管芯110A和110B。然而,要意识到在电子封装101中可以包括任何数量的第二管芯110(例如,两个或更多)的阵列。
在实施例中,第二管芯110可以与一个或多个桥130电耦合在一起。桥130可以是嵌入式多管芯互连桥(EMIB)或类似物。例如,桥130可以包括衬垫131,其具有适合于连接到第二管芯110的背面115上的衬垫119的细间距。例如,FLI 118可以将衬垫131电耦合到衬垫119。在实施例中,衬垫131和FLI 118可以被底部填充材料111环绕,并且第二管芯110的背面115上的衬垫119可以被模制层120环绕。
第二管芯110的阵列与一个或多个桥130的互连提供管芯平铺(tiling)架构。也就是说,多个第二管芯110可以充当单个管芯。这在第二管芯的组合区超出用于制造第二管芯110的过程节点的标线(reticle)限制时可以是特别有益的。
现在参考图2A,示出根据实施例的电子封装200的横截面图示。在实施例中,电子封装200可以包括模制层220,其中在该模制层中嵌入多个管芯。例如,多个第一管芯207以及第二管芯210可以嵌入模制层220中。虽然模制层220被示为包括分立层,但要意识到在模制层220的不同部分之间可能没有可辨别边界存在。在实施例中,模制层220可以包括第一表面209和与该第一表面209相对的第二表面227。模制层220可以包括用于电子封装的任何适合的材料,诸如环氧树脂或类似物。
在实施例中,多个第一管芯207可以嵌入模制层220中。与上文描述的电子封装100形成对比,第一管芯207的表面208可以被模制层220覆盖。在实施例中,表面208可以称为第一管芯207的背面。
在实施例中,多个HSIO管芯212也可以嵌入模制层220中。HSIO管芯212可以与模制层220的第一表面209大致共面。也就是说,HSIO管芯212的背面213可以与模制层220的第一表面209大致共面。在实施例中,第一管芯207的厚度T1可以与HSIO管芯212的厚度T2不同。例如,第一管芯207的厚度T1可以小于HSIO管芯212的厚度T2。如在图2A中示出的,HSIO管芯212的背面213与模制层220的表面209大致共面。然而,要意识到模制层220还可以完全内嵌HSIO管芯212使得背面213被模制层220覆盖。
在实施例中,多个第一管芯207可以电耦合到嵌入模制层220中的第二管芯210。在实施例中,第二管芯210被安置在第一管芯207的有源表面206与模制层220的第二表面227之间。第二管芯210可以具有有源表面214和背面215。在实施例中,第二管芯210和第一管芯207采用面对面配置来布置。也就是说,第二管芯210的有源表面214面对第一管芯207的有源表面206。在实施例中,第一管芯207可以在第一过程节点处制造并且第二管芯210可以在第二过程节点处制造,该第二过程节点不如第一过程节点高级。在实施例中,阻焊层242可以位于第一管芯207与第二管芯210之间。
在实施例中,第一管芯207可以利用第一级互连(FLI)218和通过阻焊层242的通孔246而电耦合到第二管芯210。例如,第一管芯207的衬垫217可以通过FLI 218而电耦合到通孔246。通孔246的相对面也可以通过FLI 218而电耦合到第二管芯210的衬垫219。在实施例中,通孔246与第二管芯210之间的FLI 218以及第二管芯210的衬垫219可以被底部填充材料211环绕。在实施例中,第一管芯207的衬垫217以及第一管芯207之间的FLI 218可以被不同的底部填充材料211环绕。
在特定实施例中,第一管芯207可以通过第二管芯210而彼此互连。也就是说,第二管芯210可以充当补片以在第一管芯207中的每个之间提供互连。在一些实施例中,第一管芯207全部可以彼此大致相似。在其他实施例中,第一管芯207可以包括不同的功能性。在图示的实施例中,示出四个第一管芯207。然而,要意识到在电子封装200中可以使用任何数量的第一管芯207(例如,两个或更多)的阵列。
在实施例中,HSIO管芯212还可以电耦合到第二管芯210。例如,HSIO管芯212可以采用与第一管芯207连接到第二管芯210大致相同的方式通过FLI 218以及通过阻焊层242的通孔246而电耦合到第二管芯210上的衬垫219。在实施例中,第二管芯210可以在第一管芯207与HSIO管芯212之间提供互连。
在实施例中,包括导电迹线、衬垫225和通孔224的多个重分布层(RDL)可以嵌入模制层220中。RDL可以在模制层220的第二表面227上方将第一管芯207、第二管芯210和HSIO管芯212的表面电耦合到中级互连(MLI)228。在实施例中, MLI 228可以被安置在通过阻焊剂222的开口中,如本领域中已知的那样。
现在参考图2B,示出根据额外实施例的电子封装201的横截面图示。在实施例中,除了包括多个第二管芯210之外,电子封装201可以与在上文针对图2A描述的电子封装200大致相似。在图示的实施例中,示出两个第二管芯210A和210B。然而,要意识到在电子封装201中可以包括任何数量的第二管芯210(例如,两个或更多)的阵列。
在实施例中,第二管芯210可以与一个或多个桥230电耦合在一起。桥230可以是EMIB或类似物。例如,桥230可以包括衬垫231,其具有适合于连接到第二管芯210的背面215上的衬垫219的细间距。例如,FLI 218可以将衬垫231电耦合到衬垫219。在实施例中,衬垫231和FLI 218可以被底部填充材料211环绕,并且第二管芯210的背面215上的衬垫219可以被模制层220环绕。
第二管芯210的阵列与一个或多个桥230的互连提供管芯平铺架构。也就是说,多个第二管芯210可以充当单个管芯。这在第二管芯的组合区超出用于制造第二管芯210的过程节点的标线限制时可以是特别有益的。
现在参考图3A-3J,示出根据实施例的描绘用于制造与图1A中描述的电子封装100相似的电子封装300的过程的一系列横截面图示。如将显而易见的是,过程包括在组装过程提早安装第一管芯307以便提供改进的对准,其不易受到翘曲引起的变化的影响。
现在参考图3A,示出根据实施例在放置第一管芯307之后的电子封装300的横截面图示。在实施例中,第一管芯307可以附接到载体370上方的释放层371。载体370可以是尺寸稳定的材料,其不易受到明显翘曲的影响。例如,载体370可以是玻璃载体。
在实施例中,第一管芯307可以利用管芯安装器工具安装到释放层。与TCB工具相比,放置第一管芯307的管芯安装器工具的使用提供了改进的放置精度。管芯安装器工具通常具有一定放置精度,其胜过TCB工具一个数量级。例如,TCB工具通常具有±15μm的精度,而管芯安装器工具具有±5μm的精度。
在实施例中,第一管芯307安装到释放层371,其中背面308与释放层371对接。因此,有源表面306以及第一管芯307的有源表面306上的衬垫317背对载体370。在实施例中,多个HSIO管芯312也可以安装到释放层371。HSIO管芯312的背面313可以与释放层371对接,其中衬垫317背对载体370。因此,第一管芯307的背面308可以与HSIO管芯312的背面313大致共面。
现在参考图3B,示出根据实施例在第一管芯307、HSIO管芯312和载体370上方设置模制层320之后的电子封装300的横截面图示。在实施例中,可以设置模制层320并且使其图案化以便使第一管芯307和HSIO管芯312的衬垫317的表面暴露。模制层320可以利用研磨或抛光工艺来平面化,如本领域中已知的。
现在参考图3C,示出根据实施例在选择的衬垫317上制造通孔324之后的电子封装300的横截面图示。在实施例中,通孔324可以是导电柱或者用于在电子封装中形成通孔的任何其他适合的导电特征。在实施例中,通孔324可以在HSIO管芯312上的衬垫317上方制造。
现在参考图3D,示出根据实施例在第二管芯310附接到第一管芯307和HSIO管芯312之后的电子封装的横截面图示。在实施例中,第二管芯310可以利用TCB工具附接。因为TCB附接在封装组装早期发生(并且尺寸稳定的载体370仍在原处),翘曲的影响最小。因此,成品率损失最小或没有。
在实施例中,第二管芯310可以利用FLI 318而耦合到第一管芯307和HSIO管芯312。例如,C4凸点可以将第一管芯307和HSIO管芯312的衬垫317电耦合到第二管芯310的衬垫319。在实施例中,底部填充材料311可以环绕FLI 318以及第二管芯310的衬垫319。
在实施例中,第二管芯310可以采用面对面配置安装到第一管芯307。也就是说,第二管芯310的有源表面314可以面对第一管芯307的有源表面306(即,衬垫317下面的表面)。在实施例中,衬垫319还可以在第二管芯310的背面315上方形成。背面315上方的衬垫319可以是针对贯穿衬底通孔(TSV)(未示出)的衬垫,这些TSV虑及从有源表面314经过第二管芯310到达背面315的电连接。在实施例中,第一管芯307可以在第一过程节点处制造并且第二管芯310可以在第二过程节点处制造,该第二过程节点不如第一过程节点高级。
现在参考图3E,示出根据实施例在第二管芯310和通孔324上方以及周围设置模制层320之后的电子封装300的横截面图示。在实施例中,模制层320可以被平面化(例如,利用抛光或研磨)以使通孔324和衬垫319的表面暴露。
现在参考图3F,示出根据实施例在形成衬垫325和通孔324之后的电子封装300的横截面图示。在实施例中,衬垫325和通孔324可以是针对在第二管芯310之上形成的重分布层(RDL)。
现在参考图3G,示出根据实施例在形成额外的RDL之后的电子封装300的横截面图示。在实施例中,RDL可以包括嵌入模制层320中的衬垫325和通孔324。在实施例中,RDL用光刻通孔工艺(例如,衬垫/通孔形成、模制(molding)、模制研磨/抛光(以使通孔暴露)等等)来制造。在其他实施例中,RDL可以利用适合的半加成工艺(SAP)使用传统的高密度互连(HDI)有机堆积介电层、电镀等等来制造。如在图3G中示出的,模制层320包括多个可区分层320。然而,要意识到在一些实施例中在模制层320的层之间可以没有可辨别边界。
现在参考图3H,示出根据实施例在模制层320的表面327上方设置阻焊层322并且使该阻焊层图案化之后的电子封装300的横截面图示。在实施例中,阻焊层被图案化以形成多个开口323,其使模制层320上方的衬垫325暴露。
现在参考图3I,示出根据实施例在开口323中设置MLI 328之后的电子封装300的横截面图示。在实施例中,MLI 328可以包括焊料或类似物。此外,要意识到实现MIL形成而同时尺寸稳定的载体仍附接到电子封装300。因此,如之前所公开的方法的情况那样,不需要附接额外的载体。
现在参考图3J,示出根据实施例在移除载体370和释放层371之后的电子封装300的横截面图示。在实施例中,可以用典型的湿式或干式清洗法来移除任何释放层残余物,如本领域中已知的那样。在清洗之后,封装300可以被切割以具有期望的尺寸。
如在图3J中示出的,使第一管芯307的背面308暴露。因此,改进了电子封装300的热管理。在一些实施例中,散热方案(例如,散热器、均热器(heat spreader)等)可以耦合到第一管芯307的背面308。在实施例中,第一管芯307的背面308可以与HSIO管芯312的背面313以及模制层320的表面309大致共面。
现在参考图4A-4D,示出根据实施例描绘了形成电子封装401的工艺的一系列横截面图示,电子封装401与针对图1B描述的电子封装101相似。
现在参考图4A,示出根据实施例在多个第二管芯410附接到第一管芯之后的电子封装401的横截面图示。在实施例中,引入的电子封装401可以利用针对图3A-3C描述的大致相似的处理操作来制造。例如,第一管芯407的背面408和HSIO管芯412的背面413可以安装到尺寸稳定的载体470上方的释放层471,并且通孔424可以在HSIO管芯412上方形成。
在实施例中,第二管芯410A和410B可以利用TCB工具附接到第一管芯407。因为TCB附接在封装组装早期发生(并且其中尺寸稳定的载体470仍在原处),翘曲的影响最小。因此,成品率损失最小或没有。
在实施例中,第二管芯410A和410B可以利用FLI 418耦合到第一管芯407和HSIO管芯412。例如,C4凸点可以将第一管芯407和HSIO管芯412的衬垫417电耦合到第二管芯410的衬垫419。在实施例中,底部填充材料411可以环绕FLI 418以及第二管芯410的衬垫419。
在实施例中,第二管芯410可以采用面对面配置安装到第一管芯407。也就是说,第二管芯410的有源表面414可以面对第一管芯407的有源表面406。在实施例中,衬垫419也可以在第二管芯410的背面415上方形成。背面415上方的衬垫419可以是针对贯穿衬底通孔(TSV)(未示出)的衬垫,这些TSV虑及从有源表面414经过第二管芯410到达背面415的电连接。在实施例中,第一管芯407可以在第一过程节点处制造并且第二管芯410可以在第二过程节点处制造,该第二过程节点不如第一过程节点高级。
现在参考图4B,示出根据实施例在第二管芯410和通孔424上方以及周围设置模制层420之后的电子封装401的横截面图示。在实施例中,模制层420可以被平面化(例如,利用抛光或研磨)以使通孔424和衬垫419的表面暴露。
现在参考图4C,示出根据实施例在桥430跨第二管芯410A和410B附接之后的电子封装401的横截面图示。在实施例中,桥430可以是EMIB或类似物,其在第二管芯410A与410B之间提供电耦合。第二管芯410的阵列与一个或多个桥430的互连提供管芯平铺架构。也就是说,多个第二管芯410可以充当单个管芯。这在第二管芯410的组合区超出用于制造第二管芯410的过程节点的标线限制时可以是特别有益的。
在实施例中,桥430可以包括衬垫431,其电耦合到第二管芯410的背面415上的衬垫419。在实施例中,衬垫419可以利用FLI 418而电耦合到衬垫431。衬垫431和FLI 418可以被底部填充材料411环绕。虽然在图4C中示出单个桥430,但要意识到电子封装401可以包括多个桥430以在任何数量的第二管芯410之间提供连接。
现在参考图4D,示出根据实施例在第二管芯410上方制造包括衬垫425、通孔424和模制层420的RDL之后的电子封装的横截面图示。在实施例中,RDL可以用光刻通孔工艺或用标准SAP工艺制造。在实施例中,阻焊剂422可以在模制层420的表面427上方形成。MLI 428可以经过阻焊剂422以提供与衬垫425的连接。此外,要意识到实现MIL形成而同时尺寸稳定的载体仍附接到电子封装401。因此,如之前所公开的方法的情况那样,不需要附接额外的载体。
现在参考图4E,示出根据实施例在移除载体470和释放层471之后的电子封装401的横截面图示。在实施例中,可以利用典型的湿式或干式清洗法来移除任何释放层残余物,如本领域中已知的那样。在清洗之后,封装401可以被切割以具有期望的尺寸。
如在图4E中示出的,使第一管芯407的背面408暴露。因此,改进了电子封装401的热管理。在一些实施例中,散热方案(例如,散热器、均热器等)可以耦合到第一管芯407的背面408。在实施例中,第一管芯407的背面408可以与HSIO管芯412的背面413以及模制层420的表面409大致共面。
现在参考图5A-5G,示出根据实施例描绘了形成电子封装500的工艺的一系列横截面图示,电子封装500与图2A中示出的电子封装200相似。
现在参考图5A,示出根据实施例的具有种子层573的第一载体570的横截面图示。在实施例中,第一载体570可以是任何尺寸稳定的载体,例如玻璃。
现在参考图5B,示出根据实施例在种子层573上方设置具有图案化开口543的阻焊层542之后的电子封装500的横截面图示。阻焊层542可以用层压工艺等等设置。
现在参考图5C,示出根据实施例在开口543中设置通孔546和FLI 518之后的电子封装500的横截面图示。在实施例中,通孔546可以是铜或类似物,并且FLI 518可以是焊料凸点或类似物。
现在参考图5D,示出根据实施例在安装第一管芯507和HSIO管芯512之后的电子封装500的横截面图示。在实施例中,第一管芯507和HSIO管芯512可以利用TCB工具安装到FLI518。因此,衬垫517可以附接到FLI 518。衬垫517和FLI 518可以被底部填充材料511环绕。如示出的,第一管芯507可以利用面朝下配置来附接。也就是说,第一管芯507的有源表面506可以面朝第一载体570并且第一管芯507的背面508可以背对第一载体570。
在实施例中,面朝下配置提供的优势在于,第一管芯507和HSIO管芯512的厚度不需要相同。例如,第一管芯507可以具有第一厚度T1并且HSIO管芯512可以具有第二厚度T2,其与第一厚度T1不同(例如,大于第一厚度T1)。在实施例中,在第一管芯507和HSIO管芯512已经安装到第一载体570之后,可以在它们上方以及周围设置模制层520。在一些实施例中,模塑层520可以利用研磨或抛光工艺而凹陷以使HSIO管芯背面暴露。
现在参考图5E,示出在移除第一载体570并且第二载体580附接到电子封装500的相对面之后的电子封装500的横截面图示。如示出的,第二载体580可以与模制层520对接并且阻焊剂542现在面朝上背对第二载体580。在实施例中,种子层573可以被图案化以在通孔546上方形成衬垫574。
现在参考图5F,示出根据实施例在制造通孔524并且第二管芯510附接到第一管芯507和HSIO管芯512之后的电子封装500的横截面图示。在实施例中,第二管芯510可以利用TCB工具附接。因为TCB附接在封装组装早期发生(并且其中尺寸稳定的第二载体580仍在原处),翘曲的影响最小。因此,成品率损失最小或没有。
在实施例中,第二管芯510可以利用FLI 518耦合到第一管芯507和HSIO管芯512。例如,FLI 518可以通过阻焊剂542将第二管芯510的衬垫519耦合到通孔546。在实施例中,底部填充材料511可以环绕FLI 518以及第二管芯510的衬垫519。
在实施例中,第二管芯510可以采用面对面配置安装到第一管芯507。也就是说,第二管芯510的有源表面514可以面对第一管芯507的有源表面506。在实施例中,衬垫519也可以在第二管芯510的背面515上方形成。背面515上方的衬垫519可以是针对贯穿衬底通孔(TSV)(未示出)的衬垫,这些TSV虑及从有源表面514经过第二管芯510到达背面515的电连接。在实施例中,第一管芯507可以在第一过程节点处制造并且第二管芯510可以在第二过程节点处制造,该第二过程节点不如第一过程节点高级。
现在参考图5G,示出根据实施例在形成包括衬垫525和通孔524的RDL并且移除第二载体580之后的横截面图示。在实施例中,RDL利用光刻通孔工艺或SAP工艺制造,如本领域中已知的那样。如在图5G中示出的,模制层520包括多个可区分层。然而,要意识到在一些实施例中,在模制层520的层之间可以没有可辨别边界。
在实施例中,在模制层520的表面527上设置阻焊层522。在实施例中,阻焊层被图案化并且可以设置MLI 528。在实施例中,MLI 528可以包括焊料或类似物。此外,要意识到实现MLI形成而同时尺寸稳定的第二载体580仍附接到电子封装500。因此,如之前所公开的方法的情况那样,不需要附接额外的载体。
在实施例中,第二载体580被移除以使模制层520的表面509暴露。如在图5G中示出的,第一管芯507的背面508嵌入模制层520中。在一些实施例中,使HSIO管芯512的背面513暴露。然而,在其他实施例中,HSIO管芯512的背面513也可以嵌入模制层520中。
现在参考图6A-6C,示出根据实施例描绘了用于形成电子封装601的过程的一系列横截面图示,电子封装601与针对图2B描述的电子封装201相似。
现在参考图6A,示出根据实施例在多个第二管芯610耦合到第一管芯607之后的电子封装601的横截面图示。在实施例中,引入的电子封装601可以利用针对图5A-5E描述的大致相似的处理操作来制造。例如,第一管芯607的背面608和HSIO管芯612的背面613可以面对第二载体680,并且在HSIO管芯612上方可以形成通孔624。另外,具有通孔646的阻焊剂642可以被安置在第一管芯607和HSIO管芯612上方。
在实施例中,第二管芯610A和610B可以利用TCB工具附接到第一管芯607。因为TCB附接在封装组装早期发生(并且其中尺寸稳定的第二载体680仍在原处),翘曲的影响最小。因此,成品率损失最小或没有。
在实施例中,第二管芯610A和610B可以利用FLI 618耦合到第一管芯607和HSIO管芯612。例如,FLI 618可以通过阻焊剂642将第二管芯610的衬垫619耦合到通孔646。在实施例中,底部填充材料611可以环绕FLI 618以及第二管芯610的衬垫619。
在实施例中,第二管芯610可以采用面对面配置安装到第一管芯607。也就是说,第二管芯610的有源表面614可以面对第一管芯607的有源表面606。在实施例中,衬垫619也可以在第二管芯610的背面615上方形成。背面615上方的衬垫619可以是针对贯穿衬底通孔(TSV)(未示出)的衬垫,这些TSV虑及从有源表面614经过第二管芯610到达背面615的电连接。在实施例中,第一管芯607可以在第一过程节点处制造并且第二管芯610可以在第二过程节点处制造,该第二过程节点不如第一过程节点高级。
现在参考图6B,示出根据实施例在模制层620环绕第二管芯610并且桥630跨第二管芯610A和610B附接之后的电子封装601的横截面图示。在实施例中,桥630可以是EMIB或类似物,其在第二管芯610A与610B之间提供电耦合。第二管芯610的阵列与一个或多个桥630的互连提供管芯平铺架构。也就是说,多个第二管芯610可以充当单个管芯。这在第二管芯610的组合区超出用于制造第二管芯610的过程节点的标线限制时可以是特别有益的。
在实施例中,桥630可以包括衬垫631,其电耦合到第二管芯610的背面615上的衬垫619。在实施例中,衬垫619可以利用FLI 618电耦合到衬垫631。衬垫631和FLI 618可以被底部填充材料611环绕。虽然在图6B中示出单个桥630,但要意识到电子封装601可以包括多个桥630以在任何数量的第二管芯610之间提供连接。
现在参考图6C,示出根据实施例在形成包括衬垫625和通孔624的RDL并且移除第二载体680之后的横截面图示。在实施例中,RDL利用光刻通孔工艺或SAP工艺来制造,如本领域中已知的那样。如在图6C中示出的,模制层620包括多个可区分层。然而,要意识到在一些实施例中在模制层620的层之间可能没有可辨别边界。
在实施例中,在模制层620的表面627上方设置阻焊层622。在实施例中,阻焊层被图案化并且可以设置MLI 628。在实施例中,MLI 628可以包括焊料或类似物。此外,要意识到实现MLI形成而同时尺寸稳定的第二载体680仍附接到电子封装601。因此,如之前所公开的方法的情况那样,不需要附接额外的载体。
在实施例中,第二载体680被移除以使模制层620的表面609暴露。如在图6C中示出的,第一管芯607的背面608嵌入模制层620。在一些实施例中,HSIO管芯612的背面613暴露。然而,在其他实施例中,HSIO管芯612的背面613也可以嵌入模制层620中。
现在参考图7,示出根据实施例的电子系统750的横截面图示。在实施例中,电子系统750可以包括电子封装700,其包括多个管芯。例如,多个管芯可以包括第一管芯707和第二管芯710。在实施例中,第二管芯710可以通过桥730(诸如EMIB)而电耦合在一起。在一些实施例中,第一管芯707和第二管芯710采用面对面配置定向。在一些实施例中,第一管芯707在第一过程节点处制造并且第二管芯710在第二过程节点处制造,该第二过程节点不如第一过程节点高级。在实施例中,电子封装700可以是任何电子封装,诸如在上文更详细公开的那些。
在实施例中,电子封装700可以电耦合到板790。例如,电子封装700的MLI 728可以电且机械耦合到板790上的衬垫(未示出)。虽然MLI 728被图示为焊料凸点,但要意识到电子封装700可以利用任何适合的互连架构连接到板790。板790可以是任何适合的板,诸如印刷电路板(PCB)或类似物。
图8图示根据本发明的一个实现的计算设备800。该计算设备800容纳板802。板802可以包括多个部件,其包括但不限于处理器804和至少一个通信芯片806。处理器804物理且电耦合到板802。在一些实现中,至少一个通信芯片806也物理且电耦合到板802。在另外的实现中,通信芯片806是处理器804的一部分。
这些其他部件包括但不限于易失性存储器(例如,DRAM)、非易失性存储器(例如,ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片集、天线、显示器、触屏显示器、触屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速计、陀螺仪、扬声器、相机和海量存储设备(诸如硬盘驱动器、压缩盘(CD)、数字多功能盘(DVD)等等)。
通信芯片806能够实现无线通信以便向和从计算设备800传输数据。术语“无线”和它的派生词可以用于描述电路、设备、系统、方法、技术、通信通道(channel)等,其可以通过使用经调制的电磁辐射通过非固体介质来传递数据。该术语并不意味着相关联设备不包含任何线,然而在一些实施例中它们可能不包含。通信芯片806可以实现多种无线标准或协议中的任一种,包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物,以及指定为3G、4G、5G及以上的任何其他无线协议。计算设备800可以包括多个通信芯片806。例如,第一通信芯片806可以专用于短程无线通信,诸如W-Fi和蓝牙,并且第二通信芯片806可以专用于远程无线通信,诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等等。
计算设备800的处理器804包括封装在处理器804内的集成电路管芯。根据本文描述的实施例,在本发明的一些实现中,处理器的集成电路管芯可以封装在电子系统中,该电子系统包括封装衬底,其具有采用面对面配置的第一管芯和第二管芯。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据变换成可以存储在寄存器和/或存储器中的其他电子数据的任何设备或设备的一部分。
通信芯片806还包括封装在通信芯片806内的集成电路管芯。根据本文描述的实施例,根据本发明的另一个实现,通信芯片的集成电路管芯可以封装在电子系统中,该电子系统包括封装衬底,其具有采用面对面配置的第一管芯和第二管芯。
本发明的图示实现的上述描述(包括摘要中所描述的)不意在为穷举的或将本发明限制在所公开的精确形式。虽然出于说明性目的在本文中描述了本发明的特定实现和示例,但各种等同修改在本发明的范围内是可能的,如相关领域技术人员将认识到的那样。
鉴于上文详细的描述,可以对本发明进行这些修改。在下面的权利要求中使用的术语不应解释为将本发明限制于说明书和权利要求书中所公开的特定实现。相反,本发明的范围要完全通过下面的权利要求来确定,这些权利要求将根据权利要求解释的既定原则来解释。
示例1:一种电子封装,其包括:模制层,该模制层具有第一表面和与该第一表面相对的第二表面;嵌入模制层中的多个第一管芯,其中该多个第一管芯中的每个具有与模制层的第一表面大致共面的表面;和嵌入模制层中的第二管芯,其中该第二管芯被安置在多个第一管芯与模制层的第二表面之间。
示例2:示例1的电子封装,其中多个第一管芯利用第一级互连(FLI)电耦合到第二管芯。
示例3:示例1或示例2的电子封装,其中多个第一管芯的有源表面定向成面对第二管芯的有源表面。
示例4:示例1-3的电子封装,其中多个第一管芯包括在第一过程节点处制造的管芯,并且其中第二管芯在第二过程节点处制造,该第二过程节点不如第一过程节点高级。
示例5:示例1-4的电子封装,进一步包括:嵌入模制层中的多个高速输入/输出(HSIO)管芯。
示例6:示例1-5的电子封装,其中多个HSIO管芯电耦合到第二管芯。
示例7:示例1-6的电子封装,其中多个HSIO管芯中的每个具有与模制层的第一表面大致共面的表面。
示例8:示例1-7的电子封装,进一步包括:多个第二管芯。
示例9:示例1-8的电子封装,其中多个第二管芯通过嵌入模制层中的桥而彼此电耦合。
示例10:示例1-9的电子封装,其中多个第二管芯被安置在桥与多个第一管芯之间。
示例11:示例1-10的电子封装,进一步包括:从模制层的第二表面延伸的中级互连(MLI)。
示例12:示例1-11的电子封装,其中MLI通过嵌入模制层中的导电柱和衬垫而电耦合到多个第一管芯和第二管芯。
示例13:一种电子封装,包括:模制层,该模制层具有第一表面和与该第一表面相对的第二表面;嵌入模制层中的多个第一管芯;和嵌入模制层中的第二管芯,其中该第二管芯被安置在多个第一管芯与模制层的第二表面之间;以及多个第一管芯与第二管芯之间的阻焊层。
示例14:示例13的电子封装,其中多个第一管芯中的每个完全嵌入模制层中。
示例15:示例13或示例14的电子封装,进一步包括:电耦合到第二管芯的多个高速输入/输出(HSIO)管芯。
示例16:示例13-15的电子封装,其中多个HSIO管芯具有第一厚度并且多个第一管芯具有第二厚度,该第二厚度与第一厚度不同。
示例17:示例13-16的电子封装,其中多个第一管芯在第一过程节点处制造,并且其中第二管芯在第二过程节点处制造,该第二过程节点不如第一过程节点高级。
示例18:示例13-17的电子封装,进一步包括:多个第二管芯,其中第二管芯中的每个通过嵌入模制层中的一个或多个桥而彼此电耦合。
示例19:一种制造电子封装的方法,包括:将多个第一管芯放置在载体上;在多个第一管芯上方设置第一模制层,其中使第一管芯的接触衬垫暴露;利用第一级互连(FLI)将第二管芯附接到多个第一管芯;以及在第二管芯上方设置第二模制层。
示例20:示例19的方法,其中利用管芯安装器将第一管芯放置在载体上,并且其中利用热压接合(TCB)工具将第二管芯附接到多个第一管芯。
示例21:示例19或示例20的方法,进一步包括:在第二管芯之上制造重分布层;在该重分布层上方设置阻焊剂;在该阻焊剂中形成开口;在开口中设置中级互连(MLI);以及移除载体。
示例22:一种电子系统,包括:板;耦合到该板的多管芯封装,其中该多管芯封装包括:模制层,其具有第一表面和第二表面;多个第一管芯,其中该多个第一管芯嵌入模制层中;以及耦合到多个第一管芯的第二管芯,其中第一管芯的有源表面面对第二管芯的有源表面,其中第二管芯嵌入模制层中,并且其中第二管芯在第一管芯的有源表面与模制层的第二表面之间。
示例23:示例22的电子系统,其中多个第一管芯是第一过程节点管芯,并且其中第二管芯是第二过程节点管芯,其中第一过程节点比第二过程节点更高级。
示例24:示例23的电子系统,进一步包括:嵌入模制层中的多个高速输入/输出(HSIO)管芯。
示例25:示例23或示例24的电子系统,其中多个HSIO管芯电耦合到第二管芯。
Claims (21)
1.一种多管芯电子封装,包括:
第一模制层中的第一管芯,所述第一管芯包括互连;
所述第一模制层中的第一通孔和第二通孔,所述第一通孔和所述第二通孔与所述第一管芯的第一侧横向相邻,所述第一通孔和所述第二通孔中的每个从所述第一模制层的顶表面延伸到所述第一模制层的底表面;
所述第一模制层中的第三通孔和第四通孔,所述第三通孔和所述第四通孔与所述第一管芯的第二侧横向相邻,所述第三通孔和所述第四通孔中的每个从所述第一模制层的所述顶表面延伸到所述第一模制层的所述底表面;
电耦合到所述第一管芯的第二管芯,并且所述第二管芯电耦合到所述第一通孔和所述第二通孔;
电耦合到所述第一管芯的第三管芯,所述第三管芯通过所述第一管芯的所述互连电耦合到所述第二管芯;以及
在所述第二管芯和所述第三管芯之间并与所述第二管芯和所述第三管芯接触的第二模制层,所述第二模制层具有与所述第二管芯的上表面共面的上表面,所述第二模制层在所述第二管芯和所述第一管芯之间,并且所述第二模制层在所述第三管芯和所述第一管芯之间。
2.如权利要求1所述的多管芯电子封装,其中所述第一管芯与所述第一模制层直接接触。
3.如权利要求2所述的多管芯电子封装,其中所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔中的每个与所述第一模制层直接接触。
4.如权利要求1所述的多管芯电子封装,进一步包括:
所述第一模制层中的第四管芯,所述第四管芯与所述第一管芯横向隔开。
5.如权利要求4所述的多管芯电子封装,进一步包括:
电耦合到所述第四管芯的第五管芯。
6.如权利要求1所述的多管芯电子封装,其中所述第二模制层的所述上表面与所述第三管芯的上表面共面。
7.如权利要求1所述的多管芯电子封装,其中所述第二管芯通过直接在所述第三管芯和所述第二管芯之间的电通路电耦合到所述第三管芯。
8.如权利要求1所述的多管芯电子封装,其中所述第三管芯与所述第二管芯共面。
9.如权利要求1所述的多管芯电子封装,进一步包括:
在所述第二管芯和所述第三管芯之间的第四管芯,所述第四管芯耦合到所述第一管芯。
10.如权利要求1所述的多管芯电子封装,进一步包括:
竖直地在所述第一管芯之下的多个中级互连。
11.如权利要求10所述的多管芯电子封装,进一步包括:
在所述第一管芯之下的阻焊剂,其中所述多个中级互连在所述阻焊剂中。
12.一种多管芯电子封装,包括:
第一模制层中的第一管芯,所述第一管芯包括互连;
所述第一模制层中的第一通孔和第二通孔,所述第一通孔和所述第二通孔与所述第一管芯的第一侧横向相邻,所述第一通孔和所述第二通孔中的每个从所述第一模制层的第一表面延伸到所述第一模制层的第二表面;
所述第一模制层中的第二多个通孔,所述第二多个通孔与所述第一管芯的第二侧横向相邻,所述第二多个通孔中的每个从所述第一模制层的所述第一表面延伸到所述第一模制层的所述第二表面;
电耦合到所述第一管芯的第二管芯,并且所述第二管芯电耦合到所述第一通孔和所述第二通孔;
电耦合到所述第一管芯的第三管芯,所述第三管芯通过所述第一管芯的所述互连电耦合到所述第二管芯;以及
在所述第二管芯和所述第三管芯之间并与所述第二管芯和所述第三管芯接触的第二模制层,所述第二模制层具有与所述第二管芯的表面共面的表面,所述第二模制层在所述第二管芯和所述第一管芯之间,并且所述第二模制层在所述第三管芯和所述第一管芯之间。
13.如权利要求12所述的多管芯电子封装,其中所述第一管芯与所述第一模制层直接接触。
14.如权利要求13所述的多管芯电子封装,其中所述第一通孔、所述第二通孔、所述第三通孔和所述第四通孔中的每个与所述第一模制层直接接触。
15.如权利要求12所述的多管芯电子封装,进一步包括:
所述第一模制层中的第四管芯,所述第四管芯与所述第一管芯横向隔开。
16.如权利要求15所述的多管芯电子封装,进一步包括:
电耦合到所述第四管芯的第五管芯。
17.如权利要求12所述的多管芯电子封装,其中所述第二管芯通过直接在所述第三管芯和所述第二管芯之间的电通路电耦合到所述第三管芯。
18.如权利要求12所述的多管芯电子封装,其中所述第三管芯与所述第二管芯共面。
19.如权利要求12所述的多管芯电子封装,进一步包括:
在所述第二管芯和所述第三管芯之间的第四管芯,所述第四管芯耦合到所述第一管芯。
20.如权利要求12所述的多管芯电子封装,进一步包括:
靠近所述第一管芯的与所述第二管芯和所述第三管芯相对的表面的多个中级互连。
21.如权利要求20所述的多管芯电子封装,进一步包括:
靠近所述第一管芯的与所述第二管芯和所述第三管芯相对的所述表面的阻焊剂,其中所述多个中级互连在所述阻焊剂中。
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CN111554671A (zh) | 2020-08-18 |
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SG10201913812YA (en) | 2020-09-29 |
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TWI827782B (zh) | 2024-01-01 |
US11973041B2 (en) | 2024-04-30 |
US20220115334A1 (en) | 2022-04-14 |
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