CN115248997A - Multi-channel data stream configuration method, circuit architecture, device, medium and terminal - Google Patents

Abstract

The invention provides a multichannel data stream configuration method, a circuit architecture, a device, a medium and a terminal, which are oriented to an MIPI CSI-2 protocol, introduce additional read-write control logic and a buffer matrix aiming at the problems of poor flexibility and insufficient configurability in the design of the traditional MIPI CSI-2 protocol, and adopt a control mode of a plurality of read pointers, so that the segmentation of the data stream is flexibly realized, meanwhile, the change of the number of channels and the sending requirements brought by different data formats are well adapted, and the continuity and the integrity of data sending are ensured; aiming at a buffer register group adopted in protocol design, through data stream packing and the construction of a circular buffer area, the flexibility and the configuration function of the MIPI circuit are effectively improved, and meanwhile, more storage units are not introduced, so that the balance is achieved on the aspects of operation speed and resource consumption; a circuit architecture of a group cladding layer is constructed through a pipeline structure, a read-write control module and a circular buffer area, so that the flexibility, the continuity and the correctness of data stream reading are improved.

Description

Multi-channel data stream configuration method, circuit architecture, device, medium and terminal

Technical Field

The present invention relates to the field of integrated circuit chip design, and in particular, to a method, a circuit architecture, a device, a medium, and a terminal for configuring a multi-channel data stream.

Background

In recent years, with the development of high and new information technology, the requirements of the fields of artificial intelligence, computer vision, automatic driving, security monitoring, mobile equipment and the like on the resolution of a camera sensor are increasingly increased. A CSI-2 (Camera Serial Interface 2) high-definition Camera based on an MIPI (Mobile Industry Processor Interface) protocol solves the contradiction between the high bandwidth requirement of high-definition image (video) transmission and the low speed of a traditional Interface, and simultaneously provides a uniform standard for the whole Industry, thereby shortening the development period of products and enhancing the compatibility of products of different manufacturers. Nowadays, the CSI-2 high-definition camera is widely applied to various embedded image devices, such as smart phones, televisions, wearable devices, virtual reality technology products, ADAS systems, and the like. Due to the increasing complexity of application scenarios, the requirements for transmission rate and extremely low power consumption are higher and higher, the design complexity is continuously increased, and very serious challenges are brought to the design of the traditional MIPI CSI-2 interface and the flexible transmission of data volume.

According to the MIPI CSI-2 protocol specification, the MIPI circuit architecture can be basically divided into an application layer, a group-envelope layer, a protocol layer, and a path management layer. The MIPI group module completes the recombination, packing and sending of high-speed data according to the requirements of a protocol, and plays an important role on a data link. The MIPI digital module has very close interaction with other modules, is used as the front end of the MIPI digital module to complete receiving and connecting functions, and simultaneously packs scattered data according to certain protocol requirements to generate data meeting protocol specifications. Because the last MIPI output may be a channel or a plurality of channels, if the MIPI output is a plurality of channels, data needs to be distributed for each channel according to a certain sequence, and flexible adaptation is needed when the number of the channels changes; in addition, because the number of each row of data transmitted is various, various data formats exist, for example, when four channels are transmitted, a signal which is not an integral multiple of four bytes is likely to remain, and finally three bytes or two bytes or one Byte may remain, and at this time, different transmission requirements caused by different numbers of data and different channel allocations need to be adapted, so how to skillfully plan and how to perform handshake interaction with other modules in the design process is an urgent problem to be solved.

Early implementation of an MIPI interface based on an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA) mainly focuses on implementation of a functional layer and promotion of a single channel rate, and there is no relevant research on flexible configuration of the number of channels and packing and sending of a scattered data stream. Moreover, because the existing mature MIPI CSI-2IP core supports 4-channel data transmission at most, especially under the condition of less number of channels, the problems of channel configuration and scattered data streams are not complicated, but the complexity of the problems is greatly improved as the number of channels is increased to 8 channels or even 16 channels, and the reasonable design of the MIPI group package layer circuit architecture is very important for the whole protocol.

Disclosure of Invention

In view of the foregoing drawbacks of the prior art, an object of the present invention is to provide a multi-channel data stream configuration method, a circuit architecture, an apparatus, a medium and a terminal, which solve the technical problem of insufficient flexibility of data channel configuration of the conventional MIPI CSI-2 protocol.

To achieve the above and other related objects, a first aspect of the present invention provides a multi-channel data stream configuration method applied to an MIPI CSI-2 protocol, the method including: acquiring a data stream to be configured; storing the data streams to be configured in sequence to construct a circular cache matrix; and reading the data in the circular buffer matrix by using a plurality of read pointers based on the number of the current data channels.

In some embodiments of the first aspect of the present invention, the circular buffer matrix is constructed in a manner that: controlling the write-in operation of the data stream to be configured so as to write the data stream to be configured into a storage unit in sequence to form a cache matrix; and enabling the first bit of the read address to point to the first row of the cache matrix, and so on until the last bit of the read address points to the last row of the cache matrix, and the last row comprises the first storage unit of the first row, so as to obtain the circular cache matrix.

In some embodiments of the first aspect of the present invention, the reading manner of the circular buffer matrix includes: and setting the number of the read pointers based on the number of the data channels, wherein the addresses of the read pointers are uniformly set corresponding to the number of the data channels and are synchronously overlapped with the reading of the data.

In some embodiments of the first aspect of the present invention, the multi-channel data stream configuration method comprises: under the condition that the number of the current data channels is lower than a preset value, part of the read pointers in the plurality of read pointers play a role to control the reading operation; some of the plurality of read pointers are inactive and do not control the read operation.

To achieve the above and other related objects, a second aspect of the present invention provides a circuit architecture for a multi-channel data stream configuration, comprising: the cutting module is used for cutting the data stream to be configured; the packaging module is used for arranging and conveying the cut data stream outwards; the packaging module is used for packaging the data output by the packaging module and the corresponding packet head information and packet tail information; and the read-write control module is used for forming a cache matrix by the data encapsulated by the encapsulation module according to a certain sequence and outputting the data based on the current data channel number.

In some embodiments of the second aspect of the present invention, the read/write control module includes: the device comprises a write control module, a cache matrix module and a read control module; the write control module writes the packaged data streams into the storage units in sequence; the data sent by the write control module of the buffer matrix module is integrated and packaged, and a buffer matrix is constructed; the reading control module is used for controlling the reading of the data.

In some embodiments of the second aspect of the present invention, the circuit architecture of the multi-channel data stream configuration further comprises: a packet header generation module: generating packet header information and sending the packet header information to the packaging module; a cyclic redundancy check module: receiving the data sent by the packaging module, generating corresponding package tail information and sending the package tail information to the packaging module; the packet tail information comprises a cyclic redundancy check sequence used for data check; FIFO stack module: and outputting the pre-stored data stream to the cutting module.

To achieve the above and other related objects, a third aspect of the present invention provides a multi-channel data stream configuration apparatus, comprising: the data acquisition module is used for acquiring a data stream to be configured; the data storage module is used for storing the data streams to be configured in sequence to construct a circular cache matrix; and the data reading module reads the data in the circular buffer matrix by using a plurality of read pointers based on the number of the current data channels.

To achieve the above and other related objects, a fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the multi-channel data stream configuration method.

To achieve the above and other related objects, a fifth aspect of the present invention provides an electronic terminal, comprising: a processor and a memory; the memory is used for storing computer programs, and the processor is used for executing the computer programs stored by the memory so as to enable the terminal to execute the multi-channel data stream configuration method.

As described above, the multichannel data stream configuration method, circuit architecture, device, medium and terminal according to the present invention have the following advantages: aiming at the problems of poor flexibility and insufficient configurability in the traditional MIPI CSI-2 protocol design, the invention introduces additional read-write control logic and a storage matrix, adopts a control mode of a plurality of read pointers, flexibly realizes the segmentation of data streams, well adapts to the change of different channel numbers and the sending requirements brought by different data formats, and ensures the continuity and the integrity of data sending; aiming at a buffer register group adopted in protocol design, through data stream packing and the construction of a circular buffer area, the flexibility and the configuration function of the MIPI circuit are effectively improved, and meanwhile, no more storage units are introduced, so that the balance is achieved on the aspects of operation speed and resource consumption; a packet layer circuit design framework facing to an MIPI CSI-2 protocol is provided, and flexibility, continuity and correctness of data stream reading are improved through a pipeline framework, a read-write control module and a circular buffer area.

Drawings

Fig. 1 is a flowchart illustrating a multi-channel data stream configuration method for MIPI protocol according to an embodiment of the present invention.

Fig. 2 is a circuit architecture diagram of an MIPI CSI-2 set cladding in an embodiment of the invention.

Fig. 3 is a schematic circuit diagram of a read/write control module according to an embodiment of the invention.

Fig. 4 is a schematic diagram illustrating a structure of a cache matrix according to an embodiment of the invention.

Fig. 5 is a schematic diagram illustrating a data flow reading process according to an embodiment of the invention.

Fig. 6 is a schematic structural diagram of a multi-channel data stream configuration apparatus according to an embodiment of the invention.

Fig. 7 is a schematic structural diagram of an electronic terminal according to an embodiment of the invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It is noted that in the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "above," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," "retained," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "a, B or C" or "a, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.

The invention provides a multichannel data stream configuration method, a circuit architecture, a device, a medium and a terminal, and solves the technical problem that the data channel configuration flexibility of the traditional MIPI CSI-2 protocol is insufficient.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention are further described in detail by the following embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.

Example one

As shown in fig. 1, this embodiment provides a multi-channel data stream configuration method facing to the MIPI protocol, so as to adapt to different sending requirements under different data lengths or different data channel allocations. The specific steps of the MIPI protocol-oriented multi-channel data stream configuration method include steps S11 to S13, which can be described as follows:

and S11, acquiring a data stream to be configured. The data stream is a set of ordered data sequences of bytes with a start point and an end point, and comprises an input stream, an output stream and a buffer stream, and can be divided into a byte stream and a character stream according to the types of read-write data of the data stream. If the data is different in nature and format, the data stream is processed in different manners. The present embodiment is oriented to the MIPI CSI-2 protocol, and therefore the data stream to be configured is generally a video data stream (image data stream).

In a preferred embodiment of this embodiment, the acquiring method of the data stream to be configured includes: preprocessing original video data to obtain an original FIFO (first-in first-out stack) data stream; partitioning an original FIFO data stream to a certain extent; performing Cyclic Redundancy Check (CRC) on the segmented data to generate corresponding packet tail information and generate corresponding packet header information; and encapsulating the segmented data and correspondingly generated packet header information and packet tail information to obtain a data stream to be configured.

And S12, storing the data streams to be configured in sequence to construct a circular buffer matrix, wherein the sequence is generally the time sequence of the data streams and is determined by the transmission persistence characteristic of the data streams. Specifically, the write operation of the data stream to be configured is controlled, so that the data stream to be configured is written into a storage unit in sequence to form a cache matrix; and enabling the first bit of the read address to point to the first row of the cache matrix, and so on until the last bit of the read address points to the last row of the cache matrix, and the last row comprises the first storage unit of the first row, so as to obtain the circular cache matrix. Preferably, the circular buffer areas are connected end to end and have fixed sizes, so that unnecessary space waste and information redundancy caused by repeated storage of data are avoided.

And S13, reading the data in the circular cache matrix by using a plurality of read pointers based on the number of the current data channels. Specifically, the reading operation of the data is controlled through the read enable signal and the read address, the read pointers adaptive to the number of the data channels are arranged, and the addresses of the read pointers are uniformly arranged corresponding to the number of the data channels and are synchronously overlapped with the reading of the data.

In a preferred embodiment of this embodiment, the pointers are flexibly allocated according to the current number of data channels, and when the current number of data channels is lower than a preset value, a part of the read pointers in the plurality of read pointers play a role to control the reading operation; and part of the read pointers in the plurality of read pointers do not play a role and do not control the reading operation, so that the number of the current data channels is adapted, and the reading and the output of the data are flexibly controlled.

For example, when there are eight data channels, two read pointers (read pointer 1 and read pointer 2) may be provided; when the number of data channels is sixteen, four read pointers may be provided. For another example, when eight data channels read eight bits of data at a time, the address of the read pointer 2 is read pointer 1 plus four, and every time one data is read, two read pointers are increased by four at a time, two sets of data, that is, two sets of four buffer register data, are read, and the two most significant Byte data correspond to channel eight and channel four, respectively, and then decrease downwards in sequence; when four channels read four bytes at a time or two channels read two bytes at a time, the read pointer 2 does not work any more, only the read pointer 1 controls the read operation, and when two channels, the read pointer is increased by two at a time, and when four channels are increased by four at a time.

In some embodiments, the method may be applied to a controller, such as an ARM (Advanced RISC Machines) controller, an FPGA (Field Programmable Gate Array) controller, an SoC (System on Chip) controller, a DSP (Digital Signal Processing) controller, or an MCU (Microcontroller Unit) controller, among others. In some embodiments, the methods are also applicable to a computer including components such as memory, a memory controller, one or more processing units (CPUs), a peripheral interface, RF circuitry, audio circuitry, speakers, a microphone, an input/output (I/O) subsystem, a display screen, other output or control devices, and an external port; the computer includes, but is not limited to, personal computers such as desktop computers, notebook computers, tablet computers, smart phones, smart televisions, personal Digital Assistants (PDAs), and the like. In other embodiments, the method may also be applied to servers, which may be arranged on one or more physical servers, or may be formed of a distributed or centralized cluster of servers, depending on various factors such as function, load, etc.

Example two

As shown in fig. 2, the present embodiment proposes a schematic diagram of an overall circuit architecture of a MIPI CSI-2 group-cladding based on a pipeline structure, wherein, the inside blocks of the group-cladding are indicated in solid line boxes; solid arrows represent data paths; the dashed line represents a module interacting with the packet layer, such as a header module (packet header generation module), a Cyclic Redundancy Check (CRC) module, a first-in first-out stack (FIFO) module, and the like, where the header module is configured to generate packet header information for the protocol module, the CRC module is configured to receive data sent by the packing module and correspondingly generate a CRC sequence for data check attached to the packet tail, and the FIFO module is mainly configured to output a data stream processed by the front-end module.

The group layer includes four functional modules: the system comprises a Slicing module (cutting module), a Packet module (packing module), a packing module (Packaging module) and a read-write control module (W/R _ CTL), wherein the Slicing module is used for cutting an asynchronous FIFO data stream input by the FIFO module; the Packet module is used for sorting the cut data stream and transmitting the cut data stream to other modules, for example, for a 10-bit pixel data stream with a YUV format, original data of 40 bits is required to be divided into 4 parts, each lower two bits of the 4 parts are taken out to synthesize 8-bit data, and each part of the remaining 8-bit data is one part; the packing module combines the received header information and the Packet tail information with the data arranged by the Packet module; the W/R _ CTL module is the most important part, and the data added with the header information and the trailer information by the packing module form a circular buffer matrix according to a certain sequence, and the data is read by fully considering the influence of different line numbers and different channel numbers on data reading.

As shown in fig. 3, the present embodiment provides a schematic circuit structure diagram of a read/write control module, including: the writing control module (Wr _ ctrl), the buffer matrix module and the reading control module (Rd _ ctrl) have the following specific working procedures:

wr _ ctrl module: the packed continuous data stream (such as byte0, byte1, byte2, byte3 and byte 4) is written into storage units (such as f0-f31 and thirty-two storage units with eight bits) in a certain sequence under the control of a write enable signal Wr _ en and a write address signal Wr _ addr.

A cache matrix module: and integrating and packaging the data sent by the Wr _ ctrl module through a Package, and constructing a circular cache matrix. As shown in fig. 4, in this embodiment, taking data stored in thirty-two eight-bit memory units f0 to f31 as an example, a schematic diagram of a buffer matrix structure is provided, in which a first bit of a Read address signal (Read _ addr) is 5 ″ -d 0: rd _ dat points to the f0-f3 four eight-bit buffers, and so on, until the last 5'd31: rd _ dat points to four eight-bit buffers f31-f2, thereby constructing a loop, and realizing a function similar to a loop buffer (ring buffer). When the buffer matrix is constructed, each eight-bit data does not need to be repeatedly stored for four times, the circular buffer area is connected end to end and fixed in size, and only a read pointer needs to be additionally introduced to control the range of read data.

Rd _ ctrl module: in order to adapt to different data forms, lengths and channel numbers, the Rd _ ctrl module is controlled by the enable signal Rd _ en and the Read address signal Read _ addr, and two Read pointers (a first Read pointer A1 and a second Read pointer A2) are used for controlling data reading. As shown in fig. 5, this embodiment provides a schematic diagram of a Data stream reading process, taking the cache matrix constructed in fig. 3 as an example, when eight channels (Data _ lane0, data _ lane1,', data _ lane6, data _ lane 7) read eight-bit Data at a time, the address of the second read pointer A2 is the first read pointer A1 plus four, and every time one Data is read, two read pointers add four at a time, two sets of Data, that is, two sets of four buffer register Data, are read altogether, two most significant bit Data correspond to the channel 8 and the channel 4, and then sequentially decrease downward to correspond to the channels 7, 6, 5 or 3, 2, 1; when four channels read four bits at a time or two channels read two bits at a time, the second read pointer A2 does not play a role any more, only the first read pointer A1 controls the reading operation, and when two channels, the first read pointer A1 is increased by two once after reading one data; in four channels, four times are added after the first read pointer A1 reads one datum; and the subsequent data module also performs corresponding processing according to the activation condition of the eight channels.

In summary, in this embodiment, the Read-write control module writes loose data streams into the plurality of buffer registers according to a certain sequence to adapt to the change of the number of data channels, and finally reads the data according to the change, the data points to the buffer registers of the preset group according to the requirement of the Read address signal Read _ addr during each reading, each group of Read data corresponds to each current data channel one to one, so as to achieve flexible, continuous and accurate reading of the data, and achieve flexible configuration of the multi-channel data stream

EXAMPLE III

As shown in fig. 6, the present embodiment provides a multi-channel data stream configuration apparatus, including: a data obtaining module 61, configured to obtain a data stream to be configured; a data storage module 62, configured to store the data streams to be configured in sequence to construct a circular buffer matrix; and a data reading module 63, configured to read data in the circular buffer matrix by using a plurality of read pointers based on the number of current data channels.

It should be noted that the modules provided in this embodiment are similar to the methods and embodiments provided above, and therefore, the description thereof is omitted. It should be noted that the division of the modules of the above apparatus is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. And these modules can all be implemented in the form of software invoked by a processing element; or can be implemented in the form of hardware; and part of the modules can be realized in the form of calling software by the processing element, and part of the modules can be realized in the form of hardware. For example, the data reading module may be a processing element separately set up, or may be implemented by being integrated in a chip of the apparatus, or may be stored in a memory of the apparatus in the form of program code, and a processing element of the apparatus calls and executes the functions of the data reading module. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.

For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

Example four

The present embodiment proposes a computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the multi-channel data stream configuration method described above.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the above method embodiments may be performed by hardware associated with a computer program. The aforementioned computer program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

EXAMPLE five

As shown in fig. 7, an embodiment of the present invention provides a schematic structural diagram of an electronic terminal. The electronic terminal provided by the embodiment comprises: processor 71, memory 72, communicator 73; the memory 72 is connected to the processor 71 and the communicator 73 through a system bus and is used for completing mutual communication, the memory 72 is used for storing computer programs, the communicator 73 is used for communicating with other devices, and the processor 71 is used for running the computer programs so as to enable the electronic terminal to execute the steps of the multi-channel data stream configuration method.

The above-mentioned system bus may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The system bus may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus. The communication interface is used for realizing communication between the database access device and other devices (such as a client, a read-write library and a read-only library). The Memory may include a Random Access Memory (RAM), and may further include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory.

The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.

In summary, the present invention provides a method, a circuit architecture, a device, a medium and a terminal for configuring a multi-channel data stream, and aims at the problems of poor flexibility and insufficient configurability in the design of the conventional MIPI CSI-2 protocol, the present invention introduces additional read-write control logic and a memory matrix, and adopts a control mode of two read pointers, so as to flexibly implement the segmentation of the data stream, and meanwhile, well adapt to the change of different channel numbers and the sending requirements brought by different data formats, and ensure the continuity and integrity of data sending; aiming at a buffer register group adopted in protocol design, through data stream packing and the construction of a circular buffer area, the flexibility and the configuration function of the MIPI circuit are effectively improved, and meanwhile, no more storage units are introduced, so that the balance is achieved on the aspects of operation speed and resource consumption; a package layer circuit design framework facing an MIPI CSI-2 protocol is provided, and flexibility, continuity and accuracy of data stream reading are improved through a pipeline framework, a read-write control module and a circular buffer area. Therefore, the present invention effectively overcomes various disadvantages of the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A multi-channel data stream configuration method applied to MIPICSI-2 protocol, the method comprising:

acquiring a data stream to be configured;

storing the data streams to be configured in sequence to construct a circular cache matrix;

and reading the data in the circular cache matrix by using a plurality of read pointers based on the number of the current data channels.

2. The multi-channel data stream configuration method according to claim 1, wherein the circular buffer matrix is constructed in a manner comprising:

controlling the write-in operation of the data stream to be configured so as to write the data stream to be configured into a storage unit in sequence to form a cache matrix; and enabling the first bit of the read address to point to the first row of the cache matrix, and so on until the last bit of the read address points to the last row of the cache matrix, and the last row comprises the first storage unit of the first row, so as to obtain the circular cache matrix.

3. The multi-channel data stream configuration method according to claim 1, wherein the reading manner of the circular buffer matrix comprises: and setting the number of the read pointers based on the number of the data channels, wherein the addresses of the read pointers are uniformly set corresponding to the number of the data channels and are synchronously overlapped with the reading of the data.

4. The multi-channel data stream configuration method according to claim 1, comprising: under the condition that the number of the current data channels is lower than a preset value, part of the read pointers in the plurality of read pointers play a role to control the reading operation; some of the plurality of read pointers are inactive and do not control the read operation.

5. A circuit architecture for a multi-channel data stream configuration, comprising:

the cutting module is used for cutting the data stream to be configured;

the packaging module is used for arranging and conveying the cut data stream outwards;

the packaging module is used for packaging the data output by the packaging module and the corresponding packet head information and packet tail information;

and the read-write control module is used for forming a circular cache matrix by the data encapsulated by the encapsulation module according to a certain sequence and outputting the data based on the current data channel number.

6. The circuit architecture of claim 5, wherein the read-write control module comprises: the device comprises a write control module, a cache matrix module and a read control module; the write control module writes the packaged data streams into the storage units in sequence; the buffer matrix module integrates and packs the data sent by the write control module and constructs a circular buffer matrix; the reading control module is used for controlling the reading of the data.

7. The circuit architecture of claim 5, further comprising:

a packet header generation module: generating packet header information and sending the packet header information to the packaging module;

a cyclic redundancy check module: receiving the data sent by the packaging module, generating corresponding package tail information and sending the package tail information to the packaging module; the packet tail information comprises a cyclic redundancy check sequence used for data check;

FIFO stack module: and outputting the pre-stored data stream to the cutting module.

8. A multi-channel data stream configuration apparatus, comprising:

the data acquisition module is used for acquiring a data stream to be configured;

the data storage module is used for storing the data streams to be configured in sequence to construct a circular cache matrix;

and the data reading module reads the data in the circular buffer matrix by using a plurality of read pointers based on the number of the current data channels.

9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the multi-channel data stream configuration method of any one of claims 1 to 4.

10. An electronic terminal, comprising: a processor and a memory;

the memory is configured to store a computer program, and the processor is configured to execute the computer program stored by the memory to cause the terminal to perform the multi-channel data stream configuration method according to any one of claims 1 to 4.

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