CN115244523A - 一种时钟展频协商方法、高速外围组件互联设备及系统 - Google Patents

一种时钟展频协商方法、高速外围组件互联设备及系统 Download PDF

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Publication number
CN115244523A
CN115244523A CN202080098309.2A CN202080098309A CN115244523A CN 115244523 A CN115244523 A CN 115244523A CN 202080098309 A CN202080098309 A CN 202080098309A CN 115244523 A CN115244523 A CN 115244523A
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China
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pcie
indication information
pcie device
clock
ordered set
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Pending
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CN202080098309.2A
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English (en)
Inventor
聂耳
王坤
李攀
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN115244523A publication Critical patent/CN115244523A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)

Abstract

一种时钟展频协商方法、高速外围组件互联设备及系统，用以在高速外围组件互联系统中实现发送端和接收端关于SSC能力的动态协商。方法包括：第二PCIe设备生成第一指示信息，该第一指示信息用于指示第二PCIe设备是否具备时钟展频能力；第二PCIe设备向第一PCIe设备发送第一指示信息。第一PCIe设备根据第一指示信息判断是否对第一PCIe设备的参考时钟进行时钟展频。

Description

PCT国内申请，说明书已公开。

Claims (27)

  1. PCT国内申请，权利要求书已公开。
CN202080098309.2A 2020-03-24 2020-03-24 一种时钟展频协商方法、高速外围组件互联设备及系统 Pending CN115244523A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/080976 WO2021189267A1 (zh) 2020-03-24 2020-03-24 一种时钟展频协商方法、高速外围组件互联设备及系统

Publications (1)

Publication Number Publication Date
CN115244523A true CN115244523A (zh) 2022-10-25

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CN202080098309.2A Pending CN115244523A (zh) 2020-03-24 2020-03-24 一种时钟展频协商方法、高速外围组件互联设备及系统

Country Status (4)

Country Link
US (1) US20240104046A1 (zh)
EP (1) EP4116835A4 (zh)
CN (1) CN115244523A (zh)
WO (1) WO2021189267A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116414753A (zh) * 2021-12-31 2023-07-11 华为技术有限公司 控制展频的方法和装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5683142B2 (ja) * 2010-06-18 2015-03-11 キヤノン株式会社 情報処理装置又は情報処理方法
CN102708086B (zh) * 2012-05-10 2015-05-20 无锡华大国奇科技有限公司 一种应用于usb3.0的弹性缓冲结构及方法
US8879680B2 (en) * 2012-11-06 2014-11-04 Ati Technologies Ulc Adaptive clock mismatch compensation symbol insertion in signal transmissions
US9946683B2 (en) * 2014-12-24 2018-04-17 Intel Corporation Reducing precision timing measurement uncertainty
KR102507714B1 (ko) * 2016-05-02 2023-03-09 삼성전자주식회사 SRIS를 지원하는 PCIe 장치
US10241536B2 (en) * 2016-12-01 2019-03-26 Intel Corporation Method, apparatus and system for dynamic clock frequency control on a bus
US10860449B2 (en) * 2017-03-31 2020-12-08 Intel Corporation Adjustable retimer buffer
US11630480B2 (en) * 2017-10-05 2023-04-18 Intel Corporation System, method, and apparatus for SRIS mode selection for PCIe
US11341073B2 (en) * 2019-06-25 2022-05-24 Vast Data Ltd. Redundant paths to single port storage devices

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Publication number Publication date
WO2021189267A1 (zh) 2021-09-30
US20240104046A1 (en) 2024-03-28
EP4116835A4 (en) 2023-04-12
EP4116835A1 (en) 2023-01-11

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