CN115244523A - 一种时钟展频协商方法、高速外围组件互联设备及系统 - Google Patents
一种时钟展频协商方法、高速外围组件互联设备及系统 Download PDFInfo
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- CN115244523A CN115244523A CN202080098309.2A CN202080098309A CN115244523A CN 115244523 A CN115244523 A CN 115244523A CN 202080098309 A CN202080098309 A CN 202080098309A CN 115244523 A CN115244523 A CN 115244523A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000001228 spectrum Methods 0.000 title claims abstract description 32
- 230000002093 peripheral effect Effects 0.000 title claims abstract description 23
- 230000007480 spreading Effects 0.000 claims description 69
- 230000006870 function Effects 0.000 description 22
- 230000003993 interaction Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000002457 bidirectional effect Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 238000011084 recovery Methods 0.000 description 4
- 230000011664 signaling Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000000819 phase cycle Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
Abstract
一种时钟展频协商方法、高速外围组件互联设备及系统,用以在高速外围组件互联系统中实现发送端和接收端关于SSC能力的动态协商。方法包括:第二PCIe设备生成第一指示信息,该第一指示信息用于指示第二PCIe设备是否具备时钟展频能力;第二PCIe设备向第一PCIe设备发送第一指示信息。第一PCIe设备根据第一指示信息判断是否对第一PCIe设备的参考时钟进行时钟展频。
Description
PCT国内申请,说明书已公开。
Claims (27)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2020/080976 WO2021189267A1 (zh) | 2020-03-24 | 2020-03-24 | 一种时钟展频协商方法、高速外围组件互联设备及系统 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115244523A true CN115244523A (zh) | 2022-10-25 |
Family
ID=77890890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202080098309.2A Pending CN115244523A (zh) | 2020-03-24 | 2020-03-24 | 一种时钟展频协商方法、高速外围组件互联设备及系统 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20240104046A1 (zh) |
EP (1) | EP4116835A4 (zh) |
CN (1) | CN115244523A (zh) |
WO (1) | WO2021189267A1 (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116414753A (zh) * | 2021-12-31 | 2023-07-11 | 华为技术有限公司 | 控制展频的方法和装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5683142B2 (ja) * | 2010-06-18 | 2015-03-11 | キヤノン株式会社 | 情報処理装置又は情報処理方法 |
CN102708086B (zh) * | 2012-05-10 | 2015-05-20 | 无锡华大国奇科技有限公司 | 一种应用于usb3.0的弹性缓冲结构及方法 |
US8879680B2 (en) * | 2012-11-06 | 2014-11-04 | Ati Technologies Ulc | Adaptive clock mismatch compensation symbol insertion in signal transmissions |
US9946683B2 (en) * | 2014-12-24 | 2018-04-17 | Intel Corporation | Reducing precision timing measurement uncertainty |
KR102507714B1 (ko) * | 2016-05-02 | 2023-03-09 | 삼성전자주식회사 | SRIS를 지원하는 PCIe 장치 |
US10241536B2 (en) * | 2016-12-01 | 2019-03-26 | Intel Corporation | Method, apparatus and system for dynamic clock frequency control on a bus |
US10860449B2 (en) * | 2017-03-31 | 2020-12-08 | Intel Corporation | Adjustable retimer buffer |
US11630480B2 (en) * | 2017-10-05 | 2023-04-18 | Intel Corporation | System, method, and apparatus for SRIS mode selection for PCIe |
US11341073B2 (en) * | 2019-06-25 | 2022-05-24 | Vast Data Ltd. | Redundant paths to single port storage devices |
-
2020
- 2020-03-24 CN CN202080098309.2A patent/CN115244523A/zh active Pending
- 2020-03-24 EP EP20926440.7A patent/EP4116835A4/en active Pending
- 2020-03-24 WO PCT/CN2020/080976 patent/WO2021189267A1/zh unknown
-
2022
- 2022-09-23 US US17/951,473 patent/US20240104046A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
WO2021189267A1 (zh) | 2021-09-30 |
US20240104046A1 (en) | 2024-03-28 |
EP4116835A4 (en) | 2023-04-12 |
EP4116835A1 (en) | 2023-01-11 |
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