CN115224122A - Trench gate IGBT device and manufacturing method thereof - Google Patents

Trench gate IGBT device and manufacturing method thereof Download PDF

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Publication number
CN115224122A
CN115224122A CN202110425234.0A CN202110425234A CN115224122A CN 115224122 A CN115224122 A CN 115224122A CN 202110425234 A CN202110425234 A CN 202110425234A CN 115224122 A CN115224122 A CN 115224122A
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trench
groove
filler
forming
region
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方冬
肖魁
卞铮
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to PCT/CN2022/078973 priority patent/WO2022222610A1/en
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Abstract

The invention relates to a trench gate IGBT device and a manufacturing method thereof, wherein the trench gate IGBT device comprises: the drift region is provided with a first conductive type and is provided with a first groove; the first groove wall insulating medium is arranged on the side wall of the first groove; the control grid is arranged at the upper part in the first groove; a first trench fill of a second conductivity type disposed in the first trench between the control gate and a device backside; the first insulation isolation structure is arranged between the control gate and the first groove filler; the drain electrode, also serving as a collector, is provided on the back surface of the device. According to the invention, the second conductive type filler is arranged at the bottom of the trench gate, and the filler is positioned between the control gate and the drain, so that the gate-drain capacitance of the device can be shielded, the switching capacitance of the device can be reduced, and the switching loss of the device can be reduced.

Description

Trench gate IGBT device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a trench gate IGBT device and a manufacturing method of the trench gate IGBT device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is used as a Bipolar device, integrates the operating mechanism of a MOSFET and the operating mechanism of the Bipolar Transistor, has the advantages of both, and is an improved power device. Compared with a bipolar transistor, the IGBT is a voltage control type device, and the gain is high under large current; compared with the MOSFET, the IGBT can bear higher voltage, the on-state voltage is reduced under large current, and the power consumption is small.
There is a desire in the industry to further reduce switching losses through structural improvements to insulated gate bipolar transistors.
Disclosure of Invention
Based on this, there is a need to provide a trench gate IGBT device with low switching losses.
A trench-gate IGBT device having opposing first and second surfaces, comprising: the drift region is provided with a first conductive type and a first groove, and the bottom of the first groove extends to the second surface; the first groove wall insulating medium is arranged on the side wall of the first groove; the control grid is arranged at the upper part in the first groove; a first trench fill of a second conductivity type disposed in the first trench and between the control gate and the second surface; the first conductivity type and the second conductivity type are opposite conductivity types; the first insulation isolation structure is arranged between the control gate and the first groove filler; the drain electrode also serves as a collector electrode and is provided on the second surface.
In one embodiment, the drift region further defines a second trench, a bottom of the second trench extends toward the second surface, and the trench gate IGBT device further includes: a source region having a first conductivity type and located between the first trench and the second trench; the second groove wall insulating medium is arranged on the side wall of the second groove; a second trench filler of a second conductivity type disposed in the second trench; and the source electrode is also used as an emitter and electrically connected with the source region and the second groove filling material.
In one embodiment, the semiconductor device further comprises a second conductive type doped region located in the drift region and at the bottom of the first trench, wherein the second conductive type doped region is in direct contact with the bottom of the first trench filler.
In one embodiment, the first groove extends in a first direction in a horizontal direction, and the second groove has a plurality arranged in the first direction.
In one embodiment, the drift region is further provided with a third trench communicated with the first trench, the third trench extends along a second direction on a horizontal plane, and the second direction is perpendicular to the first direction; the trench gate IGBT device further comprises: the third groove wall insulating medium is arranged on the side wall of the third groove; a third trench filler of a second conductivity type disposed in the third trench and having an L-shaped structure, a bottom of the L-shaped structure extending along the second direction; and the second insulating isolation structure is arranged between the control gate and the third groove filler, and the second insulating isolation structure and the first insulating isolation structure form an L-shaped structure.
In one embodiment, the first trench fill, second trench fill and third trench fill are second conductivity type doped silicon and the drift region is first conductivity type doped silicon.
In one embodiment, the method further comprises the following steps: the well region is provided with a second conductive type and is formed between the first groove and the second groove, and the source region is formed in the well region; the interlayer dielectric is arranged on the drift region and the control gate; the source electrode is arranged on the interlayer medium, the source electrode is electrically connected with the source region and the second groove filler through a conductive material filled in a contact hole, and the contact hole penetrates through the interlayer medium downwards; and the contact region is of the second conduction type, is positioned in the well region and is positioned at the bottom of the contact hole.
In one embodiment, the semiconductor device further includes a first conductive type doping layer and a second conductive type doping layer disposed between the drift region and the drain electrode, the first conductive type doping layer is disposed adjacent to the drift region, and the second conductive type doping layer is disposed adjacent to the drain electrode.
It is also necessary to provide a method of manufacturing a trench gate IGBT device.
A manufacturing method of a trench gate IGBT device comprises the following steps: obtaining a substrate, wherein the substrate is provided with a first conductive type; forming a first groove extending to the back surface on the front surface of the substrate; forming a first groove wall insulating medium on the side wall of the first groove and exposing the bottom inner wall of the first groove; filling a first trench filler into the first trench; the first trench filler has a second conductivity type, the first and second conductivity types being opposite conductivity types; forming a first insulating isolation structure on the first trench filler in the first trench; forming a control gate on the first insulating isolation structure in the first trench; and carrying out a back process to form a drain electrode which also serves as a collector.
In one embodiment, the step of forming a first trench extending to the back side on the front side of the substrate forms a second trench extending to the back side on the front side of the substrate; forming a first groove wall insulating medium on the side wall of the first groove, and simultaneously forming a second groove wall insulating medium on the side wall of the second groove and exposing the bottom inner wall of the first groove; filling a first groove filler into the first groove, and filling a second groove filler into the second groove, wherein the first groove filler and the second groove filler are made of the same material; after the step of filling the first trench with the first trench filler and before the step of forming the first insulating isolation structure on the first trench filler in the first trench, the method further comprises the steps of photoetching and etching the first trench filler to a required height; the manufacturing method of the trench gate IGBT device further comprises the step of forming a source region of the first conductivity type between the first trench and the second trench; the step of forming a source electrode is further included after the step of forming a source region of the first conductivity type between the first trench and the second trench; the source electrode is electrically connected with the source region and the second groove filling material, and the source electrode also serves as an emitter.
In one embodiment, after the step of forming the first trench extending to the back surface on the front surface of the substrate and before the step of filling the first trench with the first trench filler, a step of forming a second conductivity type doped region located at the bottom of the first trench in the substrate is further included; and the bottom of the first trench filler formed in the step of filling the first trench filler into the first trench is in direct contact with the second conductive type doped region.
In one embodiment, the step of forming a first trench wall insulating medium on the sidewall of the first trench includes: growing an insulating oxide layer on the inner surface of the first groove through thermal oxidation; the step of forming a second conductive type doped region located at the bottom of the first trench in the substrate includes: implanting second conductive type ions after the insulating oxide layer is grown to form the second conductive type doped region; and etching the insulating oxide layer at the bottom of the first trench after the step of forming the second conductive type doped region.
In one embodiment, after the step of filling the first trench with the first trench filler and before the step of forming the first insulating isolation structure located on the first trench filler in the first trench, a step of etching a first trench wall insulating medium above the first trench filler is further included; the method further comprises a step of forming a gate insulating medium on the side wall of the first trench above the first insulating isolation structure after the step of forming the first insulating isolation structure on the first trench filler and before the step of forming the control gate on the first insulating isolation structure in the first trench.
According to the trench gate IGBT device, the second conductive type filler is arranged at the bottom of the trench gate and is located between the control gate and the drain electrode, so that the gate-drain capacitance of the device can be shielded, the switching capacitance of the device is reduced, and the switching loss of the device can be reduced.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.
FIG. 1 is a schematic cross-sectional view of a trench gate IGBT device according to an embodiment;
FIG. 2 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A device taken along line A-A' of FIG. 1 in one embodiment;
FIG. 3 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A device of another embodiment taken along line A-A' of FIG. 1;
FIG. 4 is a schematic cross-sectional view of a trench gate IGBT device according to another embodiment;
FIG. 5 is a schematic cross-sectional view taken along line B-B' of FIG. 4;
FIG. 6 is a flow chart of a method of manufacturing a trench gate IGBT device according to an embodiment;
FIGS. 7 a-7 f are schematic cross-sectional views of devices in an embodiment during fabrication of a trench gate IGBT device using the method of FIG. 6;
fig. 8 is a schematic cross-sectional structure of a comparative trench gate IGBT.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
Fig. 1 is a schematic cross-sectional view of a trench gate IGBT device according to an embodiment. The device includes drift region 110, first trench wall insulating medium 152, control gate 160, first trench fill 142, first insulating isolation structure 158, and drain electrode 184. In the embodiment shown in fig. 1, the drift region 110 is a silicon wafer, the drift region 110 has a first conductivity type, and the device has a first trench formed downward on the upper surface of the drift region 110. A first trench wall insulating medium 152 is formed on the sidewall of the first trench, and the first trench is sequentially filled with a first trench filler 142, a first insulating isolation structure 158, and a control gate 160 from bottom to top. The bottom of the first trench is not provided with an insulating medium so that the bottom of the first trench fill 142 is in direct contact with the underlying silicon, i.e. the first trench fill 142 directly covers the bottom inner wall of the first trench. The first trench fill 142 has a second conductivity type. Drain electrode 184 also serves as a collector and is provided on the lower surface of the device.
Compared with the trench gate IGBT of the comparative example shown in the figure 8, the trench gate IGBT device has the advantages that the filling material of the second conductivity type is arranged at the bottom of the trench gate, and the filling material is located between the control gate and the drain electrode, so that the gate-drain capacitance of the device can be shielded, the switching capacitance of the device can be reduced, and the switching loss of the device can be reduced. The second conductive type filler at the bottom of the trench gate is directly contacted with the semiconductor structure outside the trench, and holes can be stored and released at the bottom of the trench gate, so that the extraction of the holes in the drift region and the recombination of electrons are accelerated, the switching speed of the device is improved, and the switching loss of the device is reduced.
In the embodiment shown in fig. 1, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type.
In the embodiment shown in fig. 1, the device further includes a source region 172 having the first conductivity type. The drift region 110 further has a second trench formed downward on the upper surface thereof, and the source region 172 is located between the first trench and the second trench. A second trench wall insulating medium 154 is formed on the sidewall of the second trench, and the second trench is filled with a second trench filler 144, wherein the second trench filler 144 has the second conductivity type. In the embodiment shown in fig. 1, no insulating dielectric is provided at the bottom of the second trench, so that the bottom of the second trench filler 144 is in direct contact with the underlying silicon, i.e. the second trench filler 144 directly covers the bottom inner wall of the second trench. Source electrode 182 (also acting as an emitter) electrically connects source region 172 and second trench fill 144.
By providing the second trench and filling the second conductive type filler therein, and connecting the potential of the filler to the emitter, the on-state voltage drop of the device can be reduced. In one embodiment of the present application, the potential of the first trench fill 142 is connected to the emitter. In other embodiments, the potential of the first trench fill 142 floats.
In one embodiment of the present application, the device further includes a second conductive-type doped region 112 located within the drift region 110 and at the bottom of the first trench. The second conductive-type doped region 112 is in direct contact with the bottom of the first trench fill 142. In the embodiment shown in fig. 1, the second-conductivity-type doped region 112 is a P-type groove that completely covers the first trench fill 142 at the bottom of the first trench without being isolated by the first trench wall insulating medium 152. The P-type groove at the bottom of the first trench can further store and release holes, and the hole extraction and electron recombination speed of the drift region 110 is further increased, so that the switching speed of the device is higher, and the switching loss is smaller. In addition, the P-type groove can transfer breakdown to a P-N junction, so that the problem of electric field concentration at the bottom of the groove is solved, and the reliability of the device is improved.
In the embodiment shown in fig. 1, the bottom of the second trench is also provided with a second conductivity-type doped region 112, which also completely covers the second trench fill 144 at the bottom of the second trench without being isolated by the second trench wall insulating medium 154. The second conductive type doped region 112 is also disposed at the bottom of the second trench, so that the switching speed and reliability of the device can be further enhanced.
FIG. 2 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A device of one embodiment taken along line A-A' of FIG. 1. Referring to fig. 2, in one embodiment of the present application, the first trench extends in a first direction (i.e., Y direction in fig. 2) in a horizontal direction, and the second trench is a long-bar-type groove extending in the first direction.
Fig. 3 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A device of another embodiment taken along linebase:Sub>A-base:Sub>A' of fig. 1. Referring to fig. 3, in one embodiment of the present application, the first groove also extends in the horizontal direction in the first direction, and the second groove has a plurality of grooves arranged in the first direction.
Fig. 4 is a schematic cross-sectional view of a trench gate IGBT device according to another embodiment, and fig. 5 is a schematic cross-sectional view taken along line B-B' in fig. 4. In the embodiment shown in fig. 4, the drift region 110 is further opened with a third trench (indicated by a box in fig. 4) communicating with the first trench. Referring also to fig. 5, the third trenches extend in the second direction (X direction in fig. 5) on the horizontal plane. The sidewalls of the third trench are provided with a trench wall insulating medium (not shown in fig. 4), and the third trench is provided with a third trench filling 146, wherein the third trench filling 146 has the second conductivity type and is in an L-shaped structure. The inner wall of the bottom of the third trench is not provided with an insulating medium, i.e., the third trench filler 146 directly covers the inner wall of the bottom of the third trench. The L-shaped structure comprises a vertical part and a transverse part positioned at the bottom, wherein the transverse part extends along the second direction, and the extending direction of the vertical part is the vertical direction of the device (namely the direction of the connecting line of the upper surface and the lower surface of the device). A second insulating isolation structure 156 is also disposed in the third trench. The second isolation structure 156 is disposed between the control gate 160 and the third trench filler 146, and the second isolation structure 156 and the first isolation structure 158 form an L-shaped structure.
In one embodiment of the present application, the first trench fill 142, the second trench fill 144, and the third trench fill 146 are silicon doped with the second conductivity type. For embodiments in which the device substrate is made of other materials (i.e., not silicon), the first trench filling 142, the second trench filling 144, and the third trench filling 146 may be made of the same material as the substrate (and doped with the same type of conductivity impurities, and the doping type is opposite to that of the drift region 110, i.e., the drift region 110 has the first conductivity type, and the first trench filling 142, the second trench filling 144, and the third trench filling 146 have the second conductivity type).
In the embodiment shown in fig. 1, the device further includes a well region (body region) 174. Well region 174 has the second conductivity type and is formed between the first trench and the second trench, and source region 172 is formed in well region 174.
In the embodiment shown in fig. 1, the device further includes an interlayer dielectric (ILD) 159. An interlayer dielectric 159 is provided over drift region 110 and control gate 160. The source electrode 182 is disposed on the interlayer dielectric 159 and electrically connects the source region 172 and the second trench filling 144 through the conductive material filled in the contact hole 171 that penetrates down through the interlayer dielectric 159.
In the embodiment shown in fig. 1, the device further comprises a contact region 176. Contact region 176, having the second conductivity type, is located within well region 174 and at the bottom of contact hole 171.
In the embodiment shown in fig. 1, the device further includes a first conductive-type doped layer 120 and a second conductive-type doped layer 130 disposed between the drift region 110 and the drain electrode 184. The second conductive type doping layer 130 is disposed on the drain electrode 184, and the first conductive type doping layer 120 is disposed on the second conductive type doping layer 130.
In the embodiment shown in fig. 4, the device also includes a well region 174, a contact region 176, an interlayer dielectric 159, a first conductivity-type doped layer 120, and a second conductivity-type doped layer 130.
The application correspondingly provides a manufacturing method of the trench gate IGBT device, which can be used for manufacturing the trench gate IGBT device in the corresponding embodiment. Fig. 6 is a flow chart of a method of manufacturing a trench gate IGBT device according to an embodiment, including the steps of:
s610, obtaining a substrate.
In one embodiment of the present application, a first conductivity type doped silicon wafer is obtained, and a portion of the structure of the silicon wafer is subsequently used as the doped region 110 of the device.
S620, a first groove extending to the back surface is formed on the front surface of the substrate.
In one embodiment of the present application, the first trench is formed by etching down the front side of the substrate. Referring to fig. 7a, a first trench 111 may be formed by photolithography and etching after forming a hard mask 112 on the front surface of the substrate. In one embodiment of the present application, the hard mask 112 may be made of silicon nitride.
S630, a first trench wall insulating medium is formed on the sidewall of the first trench.
In the embodiment shown in fig. 7a, an insulating oxide layer is thermally oxidized and grown on the inner surface of the first trench 111 by a thermal oxidation process to serve as the first trench wall insulating medium 152.
S640, filling the first trench with a first trench filler.
In one embodiment of the present application, the bottom inner wall of the first trench 111 needs to be exposed before filling the first trench filler.
In one embodiment of the present application, the first trench fill 142 is a second conductivity type doped silicon. The first trench fill 142 formed in the first trench 111 needs to be controlled to a desired height.
In one embodiment of the present application, the first trench fill 142 may be lithographically etched to a desired height after the first trench fill 142 is deposited. The hard mask 112 is removed prior to photolithography and etching of the first trench fill 142.
In one embodiment of the present application, a step of forming a second conductive-type doped region 112 located at the bottom of the first trench 111 in the drift region 110 is further included between the steps S630 and S640. Specifically, the second conductive type ions may be implanted into the bottom of the first trench 111 through an ion implantation process. Referring to fig. 7b, the hard mask 112 may act as an implant stop during implantation. In one embodiment of the present application, the second conductive type ions are implanted and then etched to remove the excess first trench wall insulating medium 152 at the bottom of the first trench 111. The first trench filler 142 is in direct contact with the second conductive-type doped region 112.
S650, a first insulation isolation structure on the first trench filler is formed in the first trench.
In one embodiment of the present application, the first insulating isolation structure 158 may be formed on the first trench fill 142 by a deposition process.
In the embodiment shown in fig. 7d, after the etching of the first trench filling 142 to the required height and before the step S650, a step of etching the first trench wall insulating medium 152 above the first trench filling 142 is further included, i.e. the first trench wall insulating medium 152 above the first trench filling 142 is etched before the first insulating isolation structure 158 is formed.
And S660, forming a control gate on the first insulation isolation structure in the first trench.
In one embodiment of the present application, control gate 160 may be obtained by depositing polysilicon into first trench 111 and then etching back the polysilicon to the desired height.
In the embodiment shown in fig. 7e, a step of forming a gate insulating dielectric 153 on the sidewall of the first trench 111 above the first insulating isolation structure 158 is further included between steps S650 and S660. Specifically, the gate insulating dielectric 153 may be formed by growing silicon dioxide by thermal oxidation.
And S670, carrying out a back process to form a drain electrode.
According to the trench gate IGBT device manufactured by the manufacturing method of the trench gate IGBT device, the second conductive type filler is arranged at the bottom of the trench gate and is positioned between the control gate and the drain electrode, and the gate leakage capacitance of the device can be shielded, so that the switching capacitance of the device is reduced, and the switching loss of the device can be reduced. The second conductive type filler at the bottom of the trench gate is directly contacted with the semiconductor structure outside the trench, and holes can be stored and released at the bottom of the trench gate, so that the extraction of the holes in the drift region and the recombination of electrons are accelerated, the switching speed of the device is improved, and the switching loss of the device is reduced.
In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type.
In the embodiment shown in fig. 7a, step S620 is to form the first trench 111 by an etching process and simultaneously form the second trench 113 by etching. Further, in step S630, at the same time of forming the first trench wall insulating medium 152, the second trench wall insulating medium 154 is formed on the sidewall of the second trench 113. Further, when the first trench filler 142 is filled into the first trench 111 in the step S640, the second trench filler 144 is also filled into the second trench 113; the second trench filler 144 may be the same material as the first trench filler 142. In the embodiment shown in fig. 7b, after filling the first trench filling 142 and the second trench filling 144, the first trench filling 142 is etched and etched to a desired height. Further, when the second conductive-type doped region 112 is formed, the second conductive-type doped region 112 contacting the second trench filler 144 is also formed at the bottom of the second trench 113.
In an embodiment of the present application, after step S660 and before step S670, the following steps are further included:
and S662, forming a well region and a source region.
In the embodiment shown in fig. 7f, source regions 172 of the first conductivity type and well regions (body regions) 174 of the second conductivity type are formed by implanting ions of the first conductivity type and ions of the second conductivity type. Wherein the well region 174 is formed between the first trench 111 and the second trench 113 (not labeled in fig. 7 f), and the source region 172 is formed in the well region 174 and is also located between the first trench 111 and the second trench 113.
And S664, forming an interlayer medium.
An interlayer dielectric 159 is formed on the front side of the device, including over source regions 172, over control gate 160, and over second trench fill 144. Illustratively, the interlayer dielectric may be a silicon oxide layer, such as a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, and may be Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.
S666, forming a contact hole.
Interlayer dielectric 159 is etched and etched further down into well region 174 and into second trench 113 to form contact hole 171, and source region 172 is etched through.
And S668, forming a contact region.
Second conductivity type ions are implanted into the lower portion of contact hole 171 to form a contact region 176 of the second conductivity type in well region 174. After forming contact region 176, the contact hole is filled with a conductive material, such as a metal and/or alloy.
In one embodiment of the present application, the step S670 includes forming the first conductive-type doped layer 120 on the back surface of the silicon wafer, forming the second conductive-type doped layer 130 on the back surface of the first conductive-type doped layer 120, and forming the drain electrode 184 on the back surface of the second conductive-type doped layer 130. The cell structure of the device after step S670 is completed can be referred to fig. 1, and the drain electrode 184 also serves as a collector. In one embodiment of the present application, step S668 further includes a step of forming the source electrode 182. Source electrode 182 electrically connects source region 172 and second trench fill 144; the source electrode 182 also serves as an emitter. In one embodiment of the present application, both the source electrode 182 and the drain electrode 184 are metal electrodes.
It should be understood that, although the steps in the flowcharts of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowchart of the present application may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or the stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or the stages in other steps.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (12)

1. A trench-gate IGBT device having opposing first and second surfaces, comprising:
the drift region is provided with a first conductive type and a first groove, and the bottom of the first groove extends to the second surface;
the first groove wall insulating medium is arranged on the side wall of the first groove;
the control grid is arranged at the upper part in the first groove;
a first trench fill of a second conductivity type disposed in the first trench and between the control gate and the second surface; the first conductivity type and the second conductivity type are opposite conductivity types;
the first insulation isolation structure is arranged between the control gate and the first groove filler;
the drain electrode also serves as a collector electrode and is provided on the second surface.
2. The trench gate IGBT device according to claim 1, wherein the drift region further defines a second trench, a bottom of the second trench extends toward the second surface, and the trench gate IGBT device further includes:
a source region having a first conductivity type and located between the first trench and the second trench;
the second groove wall insulating medium is arranged on the side wall of the second groove;
a second trench filler having a second conductivity type disposed in the second trench;
and the source electrode is also used as an emitter and electrically connected with the source region and the second groove filling material.
3. The trench gate IGBT device of claim 1, further comprising a second conductivity type doped region within the drift region and at the bottom of the first trench, the second conductivity type doped region being in direct contact with the bottom of the first trench fill.
4. The trench gate IGBT device according to claim 2, wherein the first trench extends in a first direction in a horizontal direction, and the second trench has a plurality arranged in the first direction.
5. The trench gate IGBT device according to claim 1 or 2, wherein the drift region is further provided with a third trench communicated with the first trench, and the third trench extends in a second direction perpendicular to the first trench on a horizontal plane; the trench gate IGBT device further comprises:
the third groove wall insulating medium is arranged on the side wall of the third groove;
a third trench filler of a second conductivity type disposed in the third trench and having an L-shaped structure, a bottom of the L-shaped structure extending along the second direction;
and the second insulating isolation structure is arranged between the control gate and the third groove filler, and the second insulating isolation structure and the first insulating isolation structure form an L-shaped structure.
6. The trench gate IGBT device of claim 2, wherein the first and second trench fills are second conductivity type doped silicon and the drift region is first conductivity type doped silicon.
7. The trench gate IGBT device of claim 2, further comprising:
the well region is provided with a second conductive type and is formed between the first groove and the second groove, and the source region is formed in the well region;
the interlayer dielectric is arranged on the drift region and the control gate; the source electrode is arranged on the interlayer medium, the source electrode is electrically connected with the source region and the second groove filler through a conductive material filled in a contact hole, and the contact hole penetrates through the interlayer medium downwards;
and the contact region is of the second conduction type, is positioned in the well region and is positioned at the bottom of the contact hole.
8. A manufacturing method of a trench gate IGBT device comprises the following steps:
obtaining a substrate, wherein the substrate is provided with a first conductive type;
forming a first groove extending to the back surface on the front surface of the substrate;
forming a first groove wall insulating medium on the side wall of the first groove and exposing the bottom inner wall of the first groove;
filling a first trench filler into the first trench; the first trench filler has a second conductivity type, the first and second conductivity types being opposite conductivity types;
forming a first insulating isolation structure on the first trench filler in the first trench;
forming a control gate on the first insulating isolation structure in the first trench;
and carrying out a back process to form a drain electrode which also serves as a collector.
9. The method for manufacturing the trench gate IGBT device according to claim 8, wherein the step of forming the first trench extending to the back side on the front side of the substrate simultaneously forms the second trench extending to the back side on the front side of the substrate;
forming a first groove wall insulating medium on the side wall of the first groove, and simultaneously forming a second groove wall insulating medium on the side wall of the second groove and exposing the bottom inner wall of the first groove;
filling a first groove filler into the first groove, and filling a second groove filler into the second groove, wherein the first groove filler and the second groove filler are made of the same material;
after the step of filling the first trench with the first trench filler and before the step of forming the first insulating isolation structure on the first trench filler in the first trench, the method further comprises the steps of photoetching and etching the first trench filler to a required height;
the manufacturing method of the trench gate IGBT device further comprises the step of forming a source region of the first conductivity type between the first trench and the second trench;
the step of forming a source electrode is further included after the step of forming a source region of the first conductivity type between the first trench and the second trench; the source electrode is electrically connected with the source region and the second groove filling material, and the source electrode also serves as an emitter.
10. The method for manufacturing the trench gate IGBT device according to claim 8, wherein after the step of forming the first trench extending to the back surface on the front surface of the substrate and before the step of filling the first trench with the first trench filling material, further comprising the step of forming a second conductivity type doped region located at the bottom of the first trench in the substrate; and the bottom of the first trench filler formed in the step of filling the first trench filler into the first trench is in direct contact with the second conductive type doped region.
11. The method of manufacturing a trench gate IGBT device according to claim 10, wherein the step of forming a first trench wall insulating medium on the sidewalls of the first trench comprises: growing an insulating oxide layer on the inner surface of the first groove through thermal oxidation;
the step of forming a second conductive type doped region located at the bottom of the first trench in the substrate includes: implanting second conductive type ions after the insulating oxide layer is grown to form the second conductive type doped region;
and etching the insulating oxide layer at the bottom of the first trench after the step of forming the second conductive type doped region.
12. The method according to claim 8, wherein after the step of filling the first trench with the first trench filler and before the step of forming the first insulating isolation structure on the first trench filler in the first trench, the method further comprises a step of etching a first trench wall insulating medium above the first trench filler;
the method further comprises a step of forming a gate insulating medium on the side wall of the first trench above the first insulating isolation structure after the step of forming the first insulating isolation structure on the first trench filler and before the step of forming the control gate on the first insulating isolation structure in the first trench.
CN202110425234.0A 2021-04-20 2021-04-20 Trench gate IGBT device and manufacturing method thereof Pending CN115224122A (en)

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