CN115214209B

CN115214209B - Isolation film, manufacturing method of isolation film and manufacturing method of circuit board

Info

Publication number: CN115214209B
Application number: CN202110426800.XA
Authority: CN
Inventors: 王瑞琴
Original assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Current assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Priority date: 2021-04-20
Filing date: 2021-04-20
Publication date: 2024-05-10
Anticipated expiration: 2041-04-20
Also published as: CN115214209A

Abstract

The utility model provides an isolation membrane, includes along bearing membrane and the isolation layer of first direction pile, the isolation layer includes along first direction pile is located first insulating layer, glue film and second insulating layer, along the perpendicular to the second direction of first direction, the width of first insulating layer is less than the width of glue film, the width of bearing membrane is greater than the width of glue film. The application also provides a manufacturing method of the isolating film and a manufacturing method of the circuit board using the isolating film.

Description

Isolation film, manufacturing method of isolation film and manufacturing method of circuit board

Technical Field

The application relates to the field of circuit boards, in particular to a manufacturing method of a circuit board.

Background

The soft and hard combined board is an organic combination of the soft board and the hard board, so that a large space can be saved in the aspect of circuit board assembly, and the market demand of the soft and hard combined board is continuously increased. In the process of producing a rigid-flex board, there is generally an uncovering process to expose connection pads (e.g., pads, lands, conductive posts, fingers, etc.) for electrical connection to the rigid-flex board.

However, in the existing uncapping process, the problem of residual glue is easy to generate on the exposed connecting pad, namely, the residual glue is remained on the connecting pad, so that the connecting pad is not easy to apply solder paste or the solder paste is dropped off, and the conductivity of an electronic element or a circuit board electrically connected with the soft and hard combined board is further caused; in addition, the residual glue remains on the connecting pad, and the appearance of the product is also affected.

Disclosure of Invention

In view of the above, it is necessary to provide a release film that can avoid leaving no adhesive residue on the connection pad during the cover opening process, so as to solve the above-mentioned problems.

In addition, it is also necessary to provide a method for manufacturing the isolating film.

In addition, it is also necessary to provide a method for manufacturing a circuit board using the above-mentioned separator.

The utility model provides an isolation membrane, includes along bearing membrane and the isolation layer of first direction pile, the isolation layer includes along first direction pile is located first insulating layer, glue film and second insulating layer, along the perpendicular to the second direction of first direction, the width of first insulating layer is less than the width of glue film, the width of bearing membrane is greater than the width of glue film.

In some embodiments, along the first direction, the first insulating layer is located within a projected area of the glue layer.

In some embodiments, the first insulating layer and the second insulating layer are both made of polyimide.

A manufacturing method of a separation film comprises the following steps:

Providing a bearing film and a first insulating layer, superposing the first insulating layer on the surface of the bearing film along a first direction, and cutting the first insulating layer so that the width of the first insulating layer along a second direction perpendicular to the first direction is smaller than the width of the bearing film; and

And forming a glue layer and a second insulating layer on the surface of the first insulating layer, which is away from the bearing film, in sequence, wherein the width of the glue layer is larger than that of the first insulating layer along the second direction.

In some embodiments, the perimeter of the glue layer protrudes from the perimeter of the glue layer in the second direction.

A manufacturing method of a circuit board comprises the following steps: providing a first circuit substrate, wherein the first circuit substrate comprises a first dielectric layer and a first circuit layer positioned on the surface of the first dielectric layer, and the first circuit layer comprises a connecting pad; covering a cover layer on the surface of the first circuit layer, wherein the cover layer is provided with a window, and the connecting pad is exposed to the window; providing an isolation layer, placing the isolation layer on the surface of the covering layer, covering the window by the isolation layer, wherein the isolation layer comprises a first insulation layer, a glue layer and a second insulation layer which are stacked along a first direction, and the width of the first insulation layer is smaller than that of the glue layer along a second direction perpendicular to the first direction; forming a second circuit substrate on the surface of the covering layer, which is away from the first circuit substrate; and removing the isolation layer and the second circuit substrate corresponding to the isolation layer to form the circuit board with the connection pad exposed to the second circuit substrate.

In some embodiments of the present application, the first insulating layer is located in a projection area of the glue layer along the first direction.

In some embodiments of the application, the first insulating layer and the cover layer overlap in the second direction by a width of greater than or equal to 0.3mm.

In some embodiments of the present application, the step of forming a second circuit substrate on a surface of the cover layer facing away from the first circuit substrate includes: pressing a second dielectric layer on the surface of the covering layer, which is away from the first circuit substrate, wherein the second dielectric layer also covers the isolation layer; pressing a copper foil on the surface of the second dielectric layer, which is away from the first circuit substrate, and carrying out circuit manufacture on the copper foil to form a second circuit layer, wherein the second dielectric layer and the second circuit layer form a second circuit substrate; and opening a hole to form a through hole penetrating the second circuit substrate, the cover layer and the first circuit substrate, and forming a conductive hole in the through hole, wherein the conductive hole is used for electrically connecting the first circuit substrate and the second circuit substrate.

In some embodiments of the present application, the step of removing the isolation layer and the second circuit substrate corresponding to the isolation layer includes: forming a groove along a peripheral shape of the isolation layer on a second circuit substrate located at one side of the first circuit substrate; and forming an opening in a direction opposite to the recessed direction of the slot, wherein the isolation layer is exposed to the opening away from the bottom of the slot, and the isolation layer and the second circuit substrate corresponding to the isolation layer are ejected out through the opening.

The isolation film comprising the isolation layer provided by the application is characterized in that in the manufacturing process of a circuit board, the isolation layer is covered on a first circuit substrate with a connection pad before the cover opening treatment of the circuit board, and then the second circuit substrate is manufactured, and in the process of forming the second circuit substrate, the connection pad exposed on the first circuit substrate cannot be polluted (namely, residual glue) under the isolation effect of the isolation layer; and after the second circuit substrate is manufactured, uncovering treatment is carried out, and the waste material area is taken out, so that the pollution-free circuit board is obtained.

Drawings

Fig. 1 is a schematic cross-sectional view of a first circuit substrate with connection pads according to an embodiment of the present application.

Fig. 2 is a schematic cross-sectional view of the first circuit board shown in fig. 1 after a cover layer with a window is covered thereon.

Fig. 3 is a schematic cross-sectional view of the cover layer shown in fig. 2 after the cover layer is covered with an isolation layer and the isolation layer covers the window.

Fig. 4 is a schematic cross-sectional view of a stacked carrier film and a first insulating layer according to an embodiment of the present application.

Fig. 5 is a schematic cross-sectional view of the first insulating layer shown in fig. 4 after forming a glue layer and a second insulating layer thereon.

Fig. 6 is a schematic cross-sectional view of the cover layer shown in fig. 3 after a second dielectric layer is formed on a surface of the cover layer facing away from the first circuit substrate.

Fig. 7 is a schematic cross-sectional view of the second dielectric layer shown in fig. 6 after forming a second circuit layer on the surface thereof to obtain a second circuit substrate and forming conductive vias for connecting the second circuit substrate and the first circuit substrate.

Fig. 8 is a schematic cross-sectional view of the second circuit layer shown in fig. 7 after forming a first slot therein.

Fig. 9 is a schematic cross-sectional view of the first slot shown in fig. 8 after a second slot is formed therein.

Fig. 10 is a schematic cross-sectional view of the second circuit substrate, the isolation layer and the first circuit substrate after forming an opening.

Fig. 11 is a schematic cross-sectional view of the circuit board obtained after the scrap area of fig. 10 is removed.

Description of the main reference signs

The application will be further described in the following detailed description in conjunction with the above-described figures.

Detailed Description

In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. The embodiments of the present application and the features in the embodiments may be combined with each other without collision. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, and the described embodiments are merely some, rather than all, embodiments of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes all and any combination of one or more of the associated listed items.

In various embodiments of the present application, for convenience of description and not limitation, the term "coupled" as used in the specification and claims of the present application is not limited to physical or mechanical coupling, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which change accordingly when the absolute position of the object to be described changes.

Referring to fig. 1-11, an embodiment of the present application provides a method for manufacturing a circuit board 100, which includes steps S1-S5.

Step S1: referring to fig. 1, a first circuit substrate 10 is provided, the first circuit substrate 10 includes a first dielectric layer 12 and a first circuit layer 14 disposed on a surface of the first dielectric layer 12, and the first circuit layer 14 includes a connection pad 145.

The material of the first dielectric layer 12 may be one of flexible materials such as Polyimide (PI), liquid crystal polymer (liquid crystal polymer, LCP), and modified polyimide (modified polyimide, MPI). In this embodiment, the material of the first dielectric layer 12 is polyimide. That is, the first circuit board 10 is a flexible board.

In this embodiment, the number of the first circuit layers 14 is two, and the two first circuit layers are respectively located on two opposite surfaces of the first dielectric layer 12. At least one conductive hole (not shown) penetrating the first circuit layer 14 and the first dielectric layer 12 is formed in the first circuit substrate 10, so that the first circuit layers 14 on two opposite surfaces of the first dielectric layer 12 are connected.

The first circuit layer 14 includes a plurality of connection pads 145, and the connection pads 145 are used for electrically connecting with other circuit layers or electronic components. The connection pads 145 include, but are not limited to, bond pads, solder pads, conductive posts, gold fingers, and the like.

Step S2: referring to fig. 2, a cover layer 20 is disposed on the surface of the first circuit layer 14, the cover layer 20 has a window 22, and the connection pad 145 is exposed to the window 22.

The cover layer 20 is made of an insulating material, and the window 22 penetrates through the cover layer 20.

The cover layer 20 includes an adhesive layer 24 and a tie layer 26. The adhesive layer 24 is located between the connection layer 26 and the first circuit substrate 10, and the adhesive layer 24 is used for bonding the connection layer 26 and the first circuit substrate 10. The material of the adhesive layer 24 may satisfy a certain adhesive effect. In the present embodiment, the adhesive layer 24 is made of an acrylic hot melt Adhesive (AD). The material of the connection layer 26 is not sticky, and the connection layer 26 can isolate the adhesive layer 24 from the adhesive layer 34 formed in the subsequent process (see fig. 6), so that the connection layer 26 is separated from the adhesive layer 34.

Step S3: referring to fig. 3 to 5, a spacer layer 30 is provided, the spacer layer 30 is disposed on the surface of the covering layer 20, and the spacer layer 30 covers the window 22.

Wherein, the cover layer 20 has a certain thickness, and when the isolation layer 30 covers the window 22, a certain distance is provided between the isolation layer 30 and the connection pad 145, so that the isolation layer 30 and the connection pad 145 can be prevented from being directly contacted.

The isolation layer 30 includes a first insulation layer 32, a glue layer 34, and a second insulation layer 36 stacked in a thickness direction of the circuit board 100, which is illustrated as a first direction L1. The glue layer 34 is located between the first insulating layer 32 and the second insulating layer 36, and the glue layer 34 is used for bonding the first insulating layer 32 and the second insulating layer 36. The first insulating layer 32 is used for isolating the adhesive layer 34, and preventing the adhesive layer 34 from adhering to the connection pad 145 during the subsequent lamination process. The first insulating layer 32 is not limited under the condition that a certain hardness condition is satisfied and the first insulating layer 32 is not adhesive, wherein the first insulating layer 32 is not adhesive, so that the first insulating layer 32 is separated from the cover layer 20 later. The second insulating layer 36 is used to protect the glue layer 34, facilitating the use of the isolation layer 30, and preventing the surface of the glue layer 34 facing away from the first insulating layer 32 from adhering to other object surfaces. The material of the second insulating layer 36 is not limited. In the present embodiment, the first insulating layer 32 and the second insulating layer 36 are both made of polyimide.

Further, the width W1 of the first insulating layer 32 is smaller than the width W2 of the glue layer 34 along the second direction L2 perpendicular to the thickness direction of the circuit board 100, i.e., the first direction L1. So that the adhesive layer 34 with fluidity can at least partially cover the periphery of the first insulating layer 32 after the subsequent lamination process, and adhere the insulating layer 30 to the cover layer 20, thereby preventing the insulating layer 30 from being displaced during the subsequent lamination process.

Further, along the first direction L1, the first insulating layer 32 is located in a projection area of the adhesive layer 34, that is, the adhesive layer 34 is located on a surface of a central area of the first insulating layer 32, and the adhesive layer 34 protrudes from a periphery of the first insulating layer 32. So that the adhesive layer 34 with fluidity can cover the entire periphery of the first insulating layer 32 after the subsequent lamination process.

The periphery of the first insulating layer 32 is covered on the periphery of the covering layer 20 to form the window 22. Along the second direction L2, the width W3 of the first insulating layer 32 overlapping the cover layer 20 is greater than or equal to 0.3mm, which can effectively prevent the adhesive layer 34 from being connected to the connection pad 145 to cause residual adhesive on the connection pad 145, thereby causing poor appearance and quality defects.

The step of forming the isolation film 35 including the isolation layer 30 may include steps S31 to S32.

Step S31: referring to fig. 4, a carrier film 38 and a first insulating layer 32 are provided, the first insulating layer 32 is stacked on the surface of the carrier film 38, and the first insulating layer 32 is cut so that the width W1 of the first insulating layer 32 along the second direction L2 is smaller than the width of the carrier film 38.

Step S32: referring to fig. 5, the adhesive layer 34 and the second insulating layer 36 are sequentially formed on the surface of the first insulating layer 32 facing away from the carrier film 38, so as to obtain an isolation film 35 including the isolation layer 30. Wherein, the width W2 of the glue layer 34 along the second direction L2 is greater than the width W1 of the first insulating layer 32, and the width of the second insulating layer 36 along the second direction L2 is greater than or equal to the width W2 of the glue layer 34.

In use, the carrier film 38 is removed to provide the barrier layer 30.

Step S4: referring to fig. 6 and 7, a second circuit substrate 40 is formed on the surface of the cover layer 20 facing away from the first circuit substrate 10.

The second circuit substrate 40 includes a second dielectric layer 42 and a second circuit layer 44, where the second dielectric layer 42 is connected to the cover layer 20, and the second circuit layer 44 is located on a surface of the second dielectric layer 42 facing away from the cover layer 20.

The second circuit substrate 40 is a hard circuit substrate, and the material of the dielectric layer may be selected from one of Polypropylene (PP) and Polytetrafluoroethylene (PTFE).

The second circuit substrate 40 is electrically connected to the first circuit substrate 10.

The forming of the second circuit substrate 40 on the surface of the cover layer 20 facing away from the first circuit substrate 10 may specifically include steps S41-S43.

Step S41: referring to fig. 6, a second dielectric layer 42 is pressed on the surface of the cover layer 20 facing away from the first circuit substrate 10, and the second dielectric layer 42 also covers the isolation layer 30.

Step S42: referring to fig. 7, a copper foil is laminated on the surface of the second dielectric layer 42 facing away from the first circuit substrate 10, and the copper foil is subjected to circuit fabrication to form a second circuit layer 44, where the second dielectric layer 42 and the second circuit layer 44 are the second circuit substrate 40.

The second circuit substrate 40 is formed by adopting the two-step method of step S41 and step S42, that is, the second dielectric layer 42 is pressed first, and then the second circuit layer 44 is formed on the surface of the second dielectric layer 42. This is because the isolation layer 30 is disposed, the surface of the isolation layer 30 facing away from the first circuit substrate 10 and the surface of the cover layer 20 facing away from the first circuit substrate 10 are not on the same plane, and in the process of laminating the second dielectric layer 42, due to the flowability of the second dielectric layer 42, the space formed by the height difference can be filled, and the formed surface of the second dielectric layer 42 facing away from the first circuit substrate 10 is on the same plane, so that the flatness of the second circuit layer 44 formed on the surface of the second dielectric layer 42 is ensured.

Step S43: referring again to fig. 7, a hole is formed through the second circuit substrate 40, the cover layer 20 and the first circuit substrate 10 (not shown), and a conductive hole 54 is formed in the through hole, wherein the conductive hole 54 is used for electrically connecting the first circuit substrate 10 and the second circuit substrate 40.

Step S5: referring to fig. 8 to 11, the isolation layer 30 and the second circuit substrate 40 corresponding to the isolation layer 30 are removed, so as to form the circuit board 100 with the connection pad 145 exposed to the second circuit substrate 40.

The second circuit substrate 40 corresponding to the isolation layer 30 and the isolation layer 30 (i.e. the projection area corresponding to the isolation layer 30 along the stacking direction) is a waste area (not shown). After the scrap region is removed, the pads are exposed to the circuit board 100.

In some embodiments, taking the example that the second circuit substrate 40 is disposed on two opposite surfaces of the first circuit substrate 10, the step of removing the waste region may include:

Step S51: referring to fig. 8 and 9, a groove 56 is formed along the peripheral shape of the isolation layer 30 on the second circuit substrate 40 located at one side of the first circuit substrate 10.

The bottom of the slot 56 is located between the surface of the second insulating layer 36 facing away from the first circuit substrate 10 and the surface of the first circuit substrate 10.

Specifically, referring to fig. 8, the second circuit layer 44 on one side of the first circuit substrate 10 is etched along the peripheral shape of the isolation layer 30 to form a first slot 562. Referring to fig. 9, a second slot 564 is formed by cutting the second dielectric layer 42 in the first slot 562. The second slot 564 may be formed by laser cutting or mechanical cutting. The first slot 562 and the second slot 564 together form the slot 56.

The bottom of the second slot 564 is located between the surface of the second insulating layer 36 facing away from the first circuit substrate 10 and the surface of the first circuit substrate 10. In this embodiment, the bottom of the second slot 564 is located on the surface of the second insulating layer 36 facing away from the first circuit substrate 10. Wherein the second slot 564 is not in communication with the fenestration 22.

Step S52: referring to fig. 10, an opening 58 is formed through the other second circuit substrate 40, the other isolation layer 30 and the first circuit substrate 10 in a direction opposite to the recess direction of the slot 56, the bottom of the isolation layer 30 facing away from the second slot 564 is exposed to the opening 58, and a material (not shown) is inserted into the opening 58 to eject the waste region, thereby forming the circuit board 100 (refer to fig. 11).

Fig. 10 and 11 are schematic cross-sectional views of the respective planes along different planes but parallel to each other. It will be appreciated that by removing the scrap region in the manner described above by ejecting the scrap region, the opening of holes through the fenestration 22 can be avoided, thereby avoiding contamination of the connection pad 145 due to the falling of the adhesive residue formed by the openings 58 onto the connection pad 145.

In some embodiments, the step of forming the copper foil into the second wiring layer 44 may also be after the step of removing the scrap region.

In some embodiments, before forming the second circuit substrate on the surface of the first circuit substrate 10, a through hole (not shown) penetrating the first circuit substrate 10 is formed on the first circuit substrate 10 along the stacking direction; forming the isolation layer 30 covering the through hole; the second circuit substrate 40 having the opening 58 is formed again, and the opening 58 corresponds to the position of the through hole, so that the waste region is taken out.

It will be appreciated that in other embodiments, the circuit board 100 is not limited to include a first circuit board 10 and a second circuit board 40, and the number of circuit boards may be set as required.

In the process of manufacturing the circuit board 100, the isolation film 35 comprising the isolation layer 30 provided by the application is used for covering the isolation layer 30 on the first circuit substrate 10 with the connection pads 145 before the cover opening treatment of the circuit board 100, then forming the second circuit substrate 40, and in the process of forming the second circuit substrate 40, pollution (namely residual glue) can not be generated on the connection pads 145 exposed on the first circuit substrate 10 under the isolation action of the isolation layer 30; after the second circuit substrate 40 is manufactured, the cover opening process is performed, and the waste area is taken out, so that the pollution-free circuit board 100 is obtained.

The above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present application.

Claims

1. The manufacturing method of the circuit board is characterized by comprising the following steps:

providing a first circuit substrate, wherein the first circuit substrate comprises a first dielectric layer and a first circuit layer positioned on the surface of the first dielectric layer, and the first circuit layer comprises a connecting pad;

covering a cover layer on the surface of the first circuit layer, wherein the cover layer is provided with a window, and the connecting pad is exposed to the window;

Providing an isolation layer, wherein the isolation layer is arranged on the surface of the covering layer, the isolation layer covers the open window, the isolation layer comprises a first insulating layer, a glue layer and a second insulating layer which are stacked along a first direction, the width of the first insulating layer is smaller than that of the glue layer along a second direction perpendicular to the first direction, the periphery of the first insulating layer covers the covering layer to form the periphery of the open window, and the glue layer protrudes out of the periphery of the first insulating layer;

Forming a second circuit substrate on the surface of the covering layer, which is away from the first circuit substrate, wherein the isolation layer is pressed, and the adhesive layer covers the periphery of the first insulating layer and is adhered to the surface of the covering layer;

forming a groove along a peripheral shape of the isolation layer on the second circuit substrate located at one side of the first circuit substrate; and

And forming an opening in the direction opposite to the recessed direction of the slot, wherein the adhesive layer is exposed to the opening away from the bottom of the slot, and the isolation layer and the second circuit substrate corresponding to the isolation layer are ejected out through the opening to form the circuit board with the connection pad exposed to the second circuit substrate.

2. The method of manufacturing a circuit board according to claim 1, wherein a width of the first insulating layer overlapping with the cover layer in the second direction is greater than or equal to 0.3mm.

3. The method of manufacturing a circuit board according to claim 1, wherein the step of forming a second wiring substrate on a surface of the cover layer facing away from the first wiring substrate comprises:

Pressing a second dielectric layer on the surface of the covering layer, which is away from the first circuit substrate, wherein the second dielectric layer also covers the isolation layer; and

Pressing a copper foil on the surface of the second dielectric layer, which is away from the first circuit substrate, and carrying out circuit manufacture on the copper foil to form a second circuit layer, wherein the second dielectric layer and the second circuit layer form a second circuit substrate; and

And carrying out hole opening treatment to form a through hole penetrating through the second circuit substrate, the covering layer and the first circuit substrate, and forming a conductive hole in the through hole, wherein the conductive hole is used for electrically connecting the first circuit substrate and the second circuit substrate.

4. The method of claim 1, wherein the bottom of the slot is located between a surface of the second insulating layer facing away from the first circuit substrate and a surface of the first circuit substrate.