CN115173983A - Method and device for compensating internal delay of communication system equipment - Google Patents
Method and device for compensating internal delay of communication system equipment Download PDFInfo
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- CN115173983A CN115173983A CN202210779036.9A CN202210779036A CN115173983A CN 115173983 A CN115173983 A CN 115173983A CN 202210779036 A CN202210779036 A CN 202210779036A CN 115173983 A CN115173983 A CN 115173983A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
Abstract
The invention relates to a method and a device for compensating internal delay of communication system equipment, wherein the method comprises the following steps: digitizing an output clock of a clock disc, acquiring a first digital timestamp based on a reference clock source, and sending the first digital timestamp to a line disc; digitizing a feedback clock of the line disk output clock and acquiring a second digital timestamp based on the reference clock source; adjusting the line pad output clock based on a difference between the first digital timestamp and the second digital timestamp to align the line pad output clock with an output clock of the clock pad. Therefore, a feedback loop does not need to be designed on the equipment backplane based on the invention, the system design is simplified, and the design requirement on the system clock routing is reduced.
Description
Technical Field
The present invention relates to the field of clock synchronization technologies, and in particular, to a method and an apparatus for compensating for internal delay of a communication system device.
Background
Currently, in a 5G high-precision clock time system, the delay of a single-node device can reach 5ns, so that it is important to perform delay compensation inside the device, and the delay compensation needs to consider static delay compensation and dynamic compensation generated along with time and temperature.
In the delay compensation method provided in the related art, a feedback clock is looped back to a clock disk through a line disk, delay measurement is performed on the clock, and then the delay of the equipment is compensated. In the method, a back board is required to design a feedback loop when a system is designed, and the receiving/transmitting paths of the feedback loop are strictly consistent and are aligned in phase, so that the wiring design of a system clock is more complex and severe.
Disclosure of Invention
The embodiment of the invention provides a method and a device for compensating the internal delay of communication system equipment, which do not need to design a feedback loop on an equipment back plate, simplify the system design and reduce the design requirement on system clock routing.
In one aspect, an embodiment of the present invention provides a method for compensating for internal delay of a communication system device, where the method includes:
digitizing an output clock of a clock disc, acquiring a first digital timestamp based on a reference clock source, and sending the first digital timestamp to a line disc;
digitizing a feedback clock of the line disk output clock and acquiring a second digital timestamp based on the reference clock source;
adjusting the line disk output clock based on a difference between the first digital timestamp and the second digital timestamp to align the line disk output clock with an output clock of the clock disk.
In some embodiments, the output clock of the clock dial comprises a system clock used internally to the device generated based on an external source of time or free oscillation;
the external time source comprises: a satellite positioning system clock, a synchronous ethernet clock, or a clock specified by the communication protocol.
In some embodiments, the digitizing the output clock of the clock disk and obtaining the first digital timestamp based on the reference clock source comprises:
sampling the position information of the rising edge or the falling edge of the output clock of the clock disc based on the reference clock source to obtain first local timestamp information;
and acquiring the first digital timestamp based on the reference clock source on the basis of the first local timestamp information by combining with second timestamp information measured by the TDC.
In some embodiments, the manner of transmitting the first digital timestamp transmission line disk includes:
and sending by adopting a special hardware line and a bus or sending based on a message channel in the equipment.
In some embodiments, said adjusting said line board output clock based on a difference between said first digital timestamp and said second digital timestamp comprises the steps of:
inputting the filtered difference value into a digital oscillator built in the circuit board to obtain a control word for controlling the digital oscillator;
adjusting the line board output clock based on the control word.
On the other hand, an embodiment of the present invention provides a device for compensating for delay inside a communication system device, where the device includes:
the first digital timestamp generating module is used for digitizing the output clock of the clock disc, acquiring a first digital timestamp based on a reference clock source and sending the first digital timestamp to the circuit disc;
the second digital timestamp generation module is used for digitizing a feedback clock of the circuit board output clock and acquiring a second digital timestamp based on the reference clock source;
a clock alignment module to adjust the line pad output clock based on a difference between the first digital timestamp and the second digital timestamp to align the line pad output clock with an output clock of the clock pad.
In some embodiments, the output clock of the clock dial comprises a system clock used internally to the device generated based on an external source of time or free oscillation;
the external time source comprises: a satellite positioning system clock, a synchronous ethernet clock, or a clock specified by the communication protocol.
In some embodiments, the first digital timestamp generation module is further to:
sampling the position information of the rising edge or the falling edge of the output clock of the clock disc based on the reference clock source to obtain first local timestamp information;
and acquiring the first digital time stamp based on the reference clock source on the basis of the first local time stamp information by combining with the second time stamp information measured by the TDC.
In some embodiments, the manner of transmitting the first digital timestamp transmission line disk includes:
and sending by adopting a special hardware line and a bus or sending based on a message channel in the equipment.
In some embodiments, the clock alignment module is further configured to:
filtering the difference value and inputting the filtered difference value into a digital oscillator built in the circuit board to obtain a control word for controlling the digital oscillator;
adjusting the line board output clock based on the control word.
According to the technical scheme provided by the invention, the analog clock is converted into the digital timestamp, the timestamp phase discrimination between the two timestamps is carried out on the local digital timestamp and the digital timestamp of the clock disc on the line disc side, and the output clock of the line disc is adjusted based on the phase discrimination result. Therefore, a feedback measurement loop of the clock is not required to be formed between the clock disc and the circuit disc, and meanwhile, because the system clock output by the clock disc is digitized, the analog clock is converted into a digital timestamp, the path delay asymmetry in the transmission process of the analog clock and the uncertain delay brought by devices on the path are avoided, and the design of a high-precision clock system is greatly simplified.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a method for compensating delay inside a communication system device according to an embodiment of the present invention;
FIG. 2 is a block diagram of an embodiment of the present invention providing high precision phase compensation via a feedback loop;
fig. 3 is a block diagram illustrating a communication system apparatus for compensating for internal delay according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a TDC measurement according to an embodiment of the present invention;
fig. 5 is a diagram illustrating an internal delay compensation apparatus of a communication system device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a method for compensating for delay inside a communication system device, including:
s100, digitizing an output clock of a clock disc, acquiring a first digital timestamp based on a reference clock source, and sending the first digital timestamp to a line disc;
s200, digitizing a feedback clock of the circuit board output clock and acquiring a second digital timestamp based on the reference clock source;
and S300, adjusting the line disk output clock based on the difference value between the first digital time stamp and the second digital time stamp so as to align the line disk output clock with the output clock of the clock disk.
It should be noted that the output clock of the clock disk can be generated by a clock module on the clock disk, which can track an external timing source or generate the output clock by free oscillation. The clock module may be an analog PLL (Phase Locked Loop) or a digital PLL or other frequency generating unit.
It should be noted that the reference clock source is a high-stability clock source, and is used for providing a reference for the output clock of the clock dial. May be an OCXO (Oven Controlled Crystal Oscillator), a TCXO (Temperature compensated X' al (Crystal) Oscillator), a Temperature compensated Crystal Oscillator), an XO (Crystal Oscillator), or other highly stable clock source.
It should be noted that, as shown in fig. 2, in the related art, in order to ensure that the system clock generated by the clock board and the system clock delay after the circuit board is regenerated are as small as possible and that the delay is not changed due to the influence factors such as temperature, time, and aging of the device itself, a measurement feedback loop is usually added between the clock board and the circuit board to measure the phase difference (delay) between the clock board and the circuit board in real time and compensate the phase difference on the circuit board side. Therefore, the design difficulties caused by the related art include: the backboard clock loop must ensure the equal PCB path delay between the clock disc and the line disc and between the line disc and the clock disc; the electrical characteristics and the temperature characteristics of the driving device or the fan-out device in the sending direction and the receiving direction in the feedback loop are completely the same; the characteristics of time delay, electricity and temperature cannot be completely consistent, and the actual measurement error cannot reach ps magnitude.
Meanwhile, when a feedback measurement method is adopted for the clock board card and the circuit board card in the device based on the related technology, each partition (slot position) is required to feed back one clock to the clock disc, and the clocks of the partitions (slot positions) are measured on the clock disc in real time. And the problems caused thereby are: the clock dial needs more terminals, and each partition (slot position) needs to return a feedback clock of the clock dial; all partition (slot) delay measurement is completed on a clock dial, so that the real-time performance is poor; the requirement on the wiring of a clock disc and a circuit disc is high, and the clock disc and all the circuit discs need to consider the equal delay characteristic of the clock wiring in the sending and feedback directions.
In view of the foregoing problems, in the method for compensating delay inside a device provided in the embodiment of the present invention, an analog clock is converted into a digital timestamp, a timestamp between two timestamps is subjected to phase discrimination on a line board side by using a local digital timestamp and a digital timestamp of a clock board, and a line board output clock is adjusted based on a phase discrimination result. Therefore, a feedback measurement loop of the clock is not required to be formed between the clock disc and the circuit disc, and meanwhile, because the system clock output by the clock disc is digitized, the analog clock is converted into a digital timestamp, the path delay asymmetry in the transmission process of the analog clock and the uncertain delay brought by devices on the path are avoided, and the design of a high-precision clock system is greatly simplified.
In some embodiments, the output clock of the clock dial is used to synchronize external SyncE (synchronous ethernet), PTP (precision time protocol), GPS (global positioning system) clocks, generating system clocks used internally by the device.
As shown in fig. 3, the clock module generates an output clock _ out _1, which may be generated by the clock module according to free oscillation or by the clock module according to a synchronous input clock source (clock _ in). With the reference clock source as a reference, performing accurate delay measurement on the clock _ out _1 through a Time-to-Digital Converter (TDC), and measuring a ps-level phase deviation of the clock _ out _1 with respect to the reference clock source.
In some embodiments, S100 comprises the steps of:
s110, sampling the position information of the rising edge or the falling edge of the output clock of the clock disc based on the reference clock source to obtain first local timestamp information;
and S120, acquiring the first digital timestamp based on the reference clock source by combining the second timestamp information measured by the TDC on the basis of the first local timestamp information.
Preferably, the TDC can be implemented by an FPGA, and the clock _ out _1 and the reference clock source are both provided to the TDC, so that the relative phase difference between the clock _ out _1 and the reference clock source can be measured. Specifically, in S110, the reference clock source samples position information (first local timestamp information) of a rising edge/a falling edge of clock _ out _1, and generates a device internal timestamp stamp (i.e., a first digital timestamp) by combining with fine time information (second timestamp information) measured by the TDC, so that the analog clock _ out _1 can be converted into time stamp digital information using the reference clock source as a reference, and the time stamp digital information is sent to a service disk (line disk).
Specifically, from the start of counting by the reference clock source until the rising/falling edge of clock _ out _1 is detected, a coarse time information (accurate to s) may be generated, and the device internal timestamp stamp may be generated in combination with the fine time information (accurate to ps) measured by the TDC. As shown in fig. 4, when the reference clock samples the measured clock, relative to the starting points 0 and 3, the information is coarse time information, the sampling only knows which rising edge of the reference clock samples the measured clock, and the time difference shown by the dotted line cannot be determined, the time difference in the dotted line is measured by the TDC to generate a fine time stamp, and combining the coarse time stamp and the fine time stamp is the complete time stamp.
It should be noted that the device internal timestamp indicates that the timestamp is only provided internally, not externally. The time stamps generated by the coarse time information and the fine time information also refer to device internal time stamps, or local time stamps, which describe how the device internal time stamps are generated.
In some embodiments, the manner of transmitting the first digital timestamp transmission line disk includes: and sending by adopting a special hardware line and a bus or sending based on a message channel in the equipment.
The bus may be a hardware bus or an inter-disk communication method. The time stamp information is communicated through a communication channel between the clock dial and the line.
In step 200, a service disk (line disk) uses the same reference clock source as the clock disk, and performs accurate phase measurement through the TDC using the reference clock source as a reference, thereby performing time stamping (digitization) on a local clock (line disk output clock) generated by the service disk PLL.
In some embodiments, in S300, a difference between the digitized second digital timestamp of the service disk and the first digital timestamp sent by the clock disk is calculated (phase-detected), and the control end of the PLL on the line disk is controlled by the difference, so as to meet the requirement that the phases of the clock _ out _2 output by the PLL on the line disk and the clock _ out _1 output by the clock disk are aligned.
Note that, the method of generating the time stamp by the line board is the same as that of the clock board, and the measured clock is digitized (used) by the reference clock. Since the sampled clock is the feedback clock of the line disk dpll, the feedback clock of the line disk dpll is still divided into s level and ps level after being digitalized. When the time stamps of the clock disk and the line disk are subjected to difference value calculation (phase discrimination), a difference value is taken between the second(s) and the second(s), and a difference value is taken between the picosecond (ps) and the picosecond (ps), so that the difference value comprises the difference value of two levels.
Preferably, S300 includes:
s310, inputting the filtered difference value into a digital oscillator arranged in the circuit board to obtain a control word for controlling the digital oscillator;
and S320, adjusting the output clock of the circuit board based on the control word.
It should be noted that, when the control terminal of the PLL on the circuit board is controlled by the difference, the output of the DCO can be controlled by adjusting the control word of the DCO according to the control method of the DPLL (Digital phase locked loop), in which case the DPLL corresponds to the DCO (Digital Crystal Oscillator). Therefore, the difference is filtered first, and there are many algorithms for filtering, such as PID (Proportional, integral, differential) filtering, the difference is sent to a PID filter, the PID filters and converts the difference, the control word of the DPLL is controlled by the output of the PID, and finally the output clock control of the DPLL is completed.
As shown in fig. 5, an embodiment of the present invention further discloses an internal delay compensation device for a communication system device, which includes:
the first digital timestamp generating module is used for digitizing the output clock of the clock disc, acquiring a first digital timestamp based on a reference clock source and sending the first digital timestamp to the circuit board;
the second digital timestamp generating module is used for digitizing a feedback clock of the line disk output clock and acquiring a second digital timestamp based on the reference clock source;
a clock alignment module to adjust the line disk output clock based on a difference between the first digital timestamp and the second digital timestamp to align the line disk output clock with an output clock of the clock disk.
In some embodiments, the output clock of the clock dial comprises a system clock used internally by the device generated based on an external clock source or free oscillation; and the external time source comprises: a satellite positioning system clock, a synchronous ethernet clock, or a clock specified by the communication protocol.
In some embodiments, the first digital timestamp generation module is further to:
sampling the position information of the rising edge or the falling edge of the output clock of the clock disc based on the reference clock source to obtain first local timestamp information;
and acquiring the first digital timestamp based on the reference clock source on the basis of the first local timestamp information by combining with second timestamp information measured by the TDC.
In some embodiments, the manner of transmitting the first digital timestamp to the line disk comprises:
and sending by adopting a special hardware line and a bus or sending based on a message channel in the equipment.
In some embodiments, the clock alignment module is further to:
inputting the filtered difference value into a digital oscillator built in the circuit board to obtain a control word for controlling the digital oscillator;
adjusting the line board output clock based on the control word.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable storage media, which may include computer readable storage media (or non-transitory media) and communication media (or transitory media).
It is noted that, in the present invention, relational terms such as "first" and "second", and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The above description is merely illustrative of particular embodiments of the invention that enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for compensating delay inside a communication system device, comprising the steps of:
digitizing an output clock of a clock disc, acquiring a first digital timestamp based on a reference clock source, and sending the first digital timestamp to a line disc;
digitizing a feedback clock of the line disk output clock and acquiring a second digital timestamp based on the reference clock source;
adjusting the line pad output clock based on a difference between the first digital timestamp and the second digital timestamp to align the line pad output clock with an output clock of the clock pad.
2. The method of claim 1, wherein the output clock of the clock dial comprises a system clock used inside the device generated based on an external source or free oscillation;
the external time source comprises: a satellite positioning system clock, a synchronous ethernet clock, or a clock specified by the communication protocol.
3. The method for compensating for delay inside a communication system device according to claim 1, wherein said digitizing an output clock of a clock dial and obtaining a first digital time stamp based on a reference clock source comprises the steps of:
sampling the position information of the rising edge or the falling edge of the output clock of the clock disc based on the reference clock source to obtain first local timestamp information;
and acquiring the first digital time stamp based on the reference clock source on the basis of the first local time stamp information by combining with the second time stamp information measured by the TDC.
4. The method of claim 1, wherein the transmitting the first digital time stamp via a transmission line board comprises:
and sending by adopting a special hardware line and a bus or sending based on a message channel in the equipment.
5. The method of claim 1, wherein said adjusting said line card output clock based on the difference between said first digital timestamp and said second digital timestamp, comprises the steps of:
inputting the filtered difference value into a digital oscillator built in the circuit board to obtain a control word for controlling the digital oscillator;
adjusting the line board output clock based on the control word.
6. An apparatus for compensating for delay in a communication system, comprising:
the first digital timestamp generating module is used for digitizing the output clock of the clock disc, acquiring a first digital timestamp based on a reference clock source and sending the first digital timestamp to the circuit disc;
the second digital timestamp generating module is used for digitizing a feedback clock of the line disk output clock and acquiring a second digital timestamp based on the reference clock source;
a clock alignment module to adjust the line disk output clock based on a difference between the first digital timestamp and the second digital timestamp to align the line disk output clock with an output clock of the clock disk.
7. The apparatus for compensating for delay inside a communication system apparatus according to claim 6, wherein the output clock of said clock dial comprises a system clock used inside the apparatus generated based on an external time source or free oscillation;
the external time source comprises: a satellite positioning system clock, a synchronous ethernet clock, or a clock specified by the communication protocol.
8. The apparatus for compensating delay time inside a communication system device of claim 6, wherein the first digital timestamp generating module is further configured to:
sampling the position information of the rising edge or the falling edge of the output clock of the clock disc based on the reference clock source to obtain first local timestamp information;
and acquiring the first digital time stamp based on the reference clock source on the basis of the first local time stamp information by combining with the second time stamp information measured by the TDC.
9. The apparatus for compensating for delay inside a communication system device of claim 6, wherein said means for transmitting said first digital time stamp transmission line board comprises:
and sending by adopting a special hardware line and a bus or sending based on a message channel in the equipment.
10. The apparatus for compensating for delay inside a communication system device of claim 6, wherein said clock alignment module is further configured to:
filtering the difference value and inputting the filtered difference value into a digital oscillator built in the circuit board to obtain a control word for controlling the digital oscillator;
adjusting the line board output clock based on the control word.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115357093A (en) * | 2022-10-21 | 2022-11-18 | 北京紫光青藤微系统有限公司 | Output frequency control method, device, clock generation circuit and memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115357093A (en) * | 2022-10-21 | 2022-11-18 | 北京紫光青藤微系统有限公司 | Output frequency control method, device, clock generation circuit and memory |
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