CN212675179U

CN212675179U - Controllable clock module based on satellite common view

Info

Publication number: CN212675179U
Application number: CN202021596116.3U
Authority: CN
Inventors: 张思德
Original assignee: Beijing Navcompass Science & Technology Co ltd
Current assignee: Beijing Navcompass Science & Technology Co ltd
Priority date: 2020-08-04
Filing date: 2020-08-04
Publication date: 2021-03-09
Anticipated expiration: 2030-08-04

Abstract

The utility model discloses a controllable clock module based on satellite looks altogether comprises FPGA treater, rubidium clock module, phase discriminator, loop filter, OCXO crystal oscillator, high accuracy delay line chip and GNSS looks module altogether. The utility model discloses a satellite looks comparison method altogether looks the module through GNSS and gathers the time signal that the clock module produced again through corresponding module to frequency difference adjustment, phase adjustment, reduces signal phase noise to increased atomic clock 1PSS signal output, still effectual reinforcing short-term signal stability makes the clock module function abundanter, and the time signal of production is more stable. Therefore, the time precision of the satellite common-view receiver can be effectively improved.

Description

Controllable clock module based on satellite common view

Technical Field

The utility model relates to a clock module technical field specifically is a controllable clock module based on satellite looks altogether.

Background

The time frequency data objects mainly measured by the satellite navigation common-view receiver mainly come from a clock module, time data generated by the clock module often deviate from standard time (namely, time frequency measurement reference of a national timekeeping laboratory), so that the time precision of the common-view receiver is reduced, and in order to effectively improve the time precision of the satellite navigation common-view receiver, the clock module needs to be enhanced and improved.

At present, an integrated module scheme for integrating a satellite common-view module and a clock module into an atomic clock in a satellite navigation common-view receiver in the market is not mature.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a controllable clock module based on satellite looks altogether to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides a controllable clock module based on satellite looks altogether, controllable clock module is looked the module by FPGA treater, rubidium clock module, phase discriminator, loop filter, OCXO crystal oscillator, high accuracy delay line chip and GNSS altogether and is constituteed, the FPGA treater is looked the module with rubidium clock module, clock branch module, high accuracy delay line chip and GNSS altogether respectively and is connected, rubidium clock module connects the phase discriminator, loop filter and OCXO crystal oscillator are connected respectively to the phase discriminator, loop filter connects the OCXO crystal oscillator, the OCXO crystal oscillator connects the clock branch module.

Preferably, the high-precision delay line chip and the clock shunt module are respectively connected to the GNSS common-view module.

Preferably, the GNSS common view module is connected to a national time-keeping laboratory time frequency measurement reference system.

Preferably, the FPGA processor model adopts EP3C25E144C 8N.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses a satellite looks comparison method altogether looks the module through GNSS and gathers the time signal that the clock module produced again through corresponding module to frequency difference adjustment, phase adjustment, reduces signal phase noise to increased atomic clock 1PSS signal output, still effectual reinforcing short-term signal stability makes the clock module function abundanter, and the time signal of production is more stable. Therefore, the time precision of the satellite common-view receiver can be effectively improved; by adding a controllable clock module based on satellite common view in the satellite navigation common view receiver, 1PPS signal output of an atomic clock can be increased, signal phase noise is reduced, and short-term signal stability is enhanced; the time frequency data of the satellite navigation common-view receiver can be compared with the time frequency data of the national time-keeping laboratory time frequency reference in real time, and the clock error can be kept within 10 ns; the time precision of the satellite navigation common-view receiver can be effectively improved.

Drawings

Fig. 1 is a control schematic block diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, the present invention provides a technical solution: a controllable clock module based on satellite common view is composed of an FPGA (field programmable gate array) processor 1, a rubidium clock module 2, a phase discriminator 3, a loop filter 4, an OCXO (optical clock oscillator) 5, a high-precision delay line chip 6 and a GNSS common view module 7, wherein the FPGA processor 1 is respectively connected with the rubidium clock module 2, a clock shunt module 8, the high-precision delay line chip 6 and the GNSS common view module 7, and the model of the FPGA processor 1 adopts EP3C25E144C 8N; the rubidium clock module 2 is connected with a phase discriminator 3, the phase discriminator 3 is respectively connected with a loop filter 4 and an OCXO crystal oscillator 5, the loop filter 4 is connected with the OCXO crystal oscillator 5, and the OCXO crystal oscillator 5 is connected with a clock shunt module 8; the high-precision delay line chip 6 and the clock shunt module 8 are respectively connected with the GNSS common-view module 7; the GNSS common view module 7 is connected with a time frequency measurement reference system 9 of a national time-keeping laboratory.

The FPGA processor controls 10MHZ signal deviation generated by a rubidium clock; dividing the 10MHZ signal divided by the receiving clock into 1PPS signals; the 1PPS delay can be controlled by the controllable high-precision delay line chip; receiving comparison information feedback of the GNSS common-view module; the phase discriminator receives a 10MHZ signal of a rubidium clock; monitoring a 10MHZ signal generated by an OCXO crystal oscillator; the three modules of the phase discriminator, the loop filter and the OCXO crystal oscillator are of a phase-locked structure and have a phase-locked function, wherein the loop filter has a filtering function; the OCXO crystal oscillator has a constant temperature function and can improve the stability of a 10MHZ signal; receiving a voltage control signal of a loop filter, and synchronizing a 10MHZ signal of the loop filter with a 10MHZ signal of a rubidium clock by controlling a voltage control pin; dividing a 10MHZ signal through a clock shunt circuit into three paths, one path is sent to an FPGA processor, the other path is sent to a GNSS common-view module, and the other path is used as output for external use; the GNSS common-view module can compare the time frequency data deviation of the local atomic clock and the time frequency measurement standard of the national time-keeping laboratory in real time; receiving 1PPS signals of a high-precision delay line chip and 10MHZ signals of a clock shunt circuit, and comparing the signals with 1PPS signals and 10MHZ signal data of a time frequency measurement reference of a national timekeeping laboratory; feeding back the time frequency signal deviation after comparison to an FPGA processor; and the 1PPS is output by the high-precision delay line chip and then is shunted to multiple paths.

The principle is as follows: the GNSS common-view module utilizes a satellite common-view principle to simultaneously acquire 10MHZ signals and 1PPS signal data output by a local atomic clock and compare the signals with 10MHZ signals and 1PPS signal data of a time frequency measurement reference of a state time-keeping laboratory, the compared signal deviation is fed back to the FPGA processor through a serial port, the FPGA processor receives the fed-back signal data deviation, the 10MHZ signal frequency difference is adjusted and the 1PPS signal is adjusted, and the signals are synchronized with the 10MHZ signals and the 1PPS signals of the time frequency measurement reference of the state time-keeping laboratory, so that the time precision of the navigation satellite common-view receiver is improved. The 10MHZ signal is obtained by adjusting the frequency difference of the 10MHZ signal generated by the rubidium clock through a serial port instruction by the FPGA processor, wherein the frequency difference range is 1e-15, and the offset is adjusted; when the phase discriminator detects that a 10MHZ signal output by the OCXO crystal oscillator is inconsistent with a 10MHZ signal output by the rubidium clock, a loop filter controls an OCXO crystal oscillator voltage control pin of the phase discriminator to change the synchronization of the 10MHZ signal output by the OCXO crystal oscillator and the adjusted 10MHZ signal output by the rubidium clock, and then the 10MHZ signal is divided into three paths, wherein the phase discriminator, the loop filter and the OCXO crystal oscillator are of a phase-locked loop structure, and the phase-locked loop has a phase-locked function by applying a phase-locked principle; the 1PPS is generated by frequency division of a corrected 10MHZ signal through an FPGA processor, the 1PPS signal passes through a high-precision delay line chip, the FPGA processor controls the high-precision delay line chip to change the delay of the 1PPS signal, the delay range is-500 ms- +500ms, the resolution is 5ns, the 1PPS signal is synchronous with the 1PPS signal fed back by the GNSS common-view module, and the 1PPS signal output by the high-precision delay line chip can be divided into multiple paths.

To sum up, the utility model discloses a satellite looks the comparison method altogether through GNSS looks the module altogether and gathers the time signal that the clock module produced through corresponding module to frequency difference adjustment, phase adjustment again, reduces signal phase noise to increased atomic clock 1PSS signal output, still effectual reinforcing short-term signal stability makes the clock module function abundanter, and the time signal of production is more stable. Therefore, the time precision of the satellite common-view receiver can be effectively improved; by adding a controllable clock module based on satellite common view in the satellite navigation common view receiver, 1PPS signal output of an atomic clock can be increased, signal phase noise is reduced, and short-term signal stability is enhanced; the time frequency data of the satellite navigation common-view receiver can be compared with the time frequency data of the national time-keeping laboratory time frequency reference in real time, and the clock error can be kept within 10 ns; the time precision of the satellite navigation common-view receiver can be effectively improved.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A controllable clock module based on satellite common view is characterized in that: controllable clock module is looked module (7) by FPGA treater (1), rubidium clock module (2), phase discriminator (3), loop filter (4), OCXO crystal oscillator (5), high accuracy delay line chip (6) and GNSS altogether and is constituteed, FPGA treater (1) looks module (7) with rubidium clock module (2), clock shunting module (8), high accuracy delay line chip (6) and GNSS altogether and is connected, phase discriminator (3) is connected in rubidium clock module (2), loop filter (4) and OCXO crystal oscillator (5) are connected respectively in phase discriminator (3), OCXO crystal oscillator (5) is connected in loop filter (4), OCXO crystal oscillator (5) are connected in OCXO crystal oscillator (5).

2. The controllable clock module based on satellite common view as claimed in claim 1, wherein: the high-precision delay line chip (6) and the clock shunt module (8) are respectively connected with the GNSS common view module (7).

3. The controllable clock module based on satellite common view as claimed in claim 1, wherein: the GNSS common view module (7) is connected with a time frequency measurement reference system (9) of a national time-keeping laboratory.

4. The controllable clock module based on satellite common view as claimed in claim 1, wherein: the FPGA processor (1) adopts EP3C25E144C 8N.