CN107483050B - Atomic clock stable switching system based on real-time tracking technology - Google Patents
Atomic clock stable switching system based on real-time tracking technology Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/26—Automatic control of frequency or phase; Synchronisation using energy levels of molecules, atoms, or subatomic particles as a frequency reference
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- G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
- G04F5/14—Apparatus for producing preselected time intervals for use as timing standards using atomic clocks
Abstract
A stable atomic clock switching system based on a real-time tracking technology relates to the technical field of satellite-borne atomic clock time-frequency generation and maintenance; the device comprises a double-mixing time difference circuit, an FPGA module, a frequency synthesis circuit, an electronic switch and an analog phase-locked loop; the FPGA module comprises a DDS module, a phase difference measuring module, an infinite impulse response digital filter module and a fault detection module; based on the DDS module and the double mixing time difference circuit, the measurement precision of the main and standby phase difference is improved through down-conversion; the FPGA module realizes high-precision measurement of the phase difference of the main clock and the standby clock, and filters and purifies an error signal through an infinite impulse response digital filter to obtain a frequency control word of the frequency control fine tuning DDS; the invention does not need to measure frequency and phase in a time-sharing way, ensures that the tracking period is equal to the measuring period through a real-time tracking algorithm, and ensures the frequency and phase jump indexes before and after switching.
Description
Technical Field
The invention relates to the technical field of satellite-borne atomic clock time-frequency generation and maintenance, in particular to an atomic clock stable switching system based on a real-time tracking technology.
Background
The Beidou second satellite takes the 10MHz frequency of an atomic clock as a satellite standard time reference signal, a time frequency generation and holding device reference frequency synthesizer receives the 10MHz signals output by the two atomic clocks, and a main frequency synthetic link and a standby frequency synthetic link are used for respectively generating two paths of 10.23MHz reference frequencies. One path is selected by the electronic switch to enter the phase-locked loop to lock the high-stability crystal oscillator, so that stable and reliable 10.23MHz reference frequency is provided for the navigation satellite.
When the atomic clock or the frequency synthesizer on the satellite working path fails, the 10.23MHz signal is discontinuous, including signal interruption, frequency jump and phase jump, which may cause navigation service interruption or positioning accuracy reduction. The time frequency generation and holding equipment reference frequency synthesizer of the big Dipper II adopts a redundant backup and switch switching mode to solve the problem, when a working path signal is abnormal, a fault detection module in the system can timely detect the abnormality, and the output frequency is switched to a hot backup path. In order to ensure stable transition of signals before and after switching, two basic conditions need to be met, namely, the frequency and the phase of a hot standby clock before switching are consistent with those of a working clock, and the switching process needs to be as fast as possible, so that the time for transmitting the abnormity is shortened.
The traditional satellite-borne time-frequency generation and holding system has no stable switching function, or has the stable switching function, but the measurement and tracking of the main clock and the standby clock are time-sharing processing and cannot be tracked in real time. The former can not guarantee the stability of output signals when the working clock fails, and in the latter, in the time interval of two tracking, the phase difference of the main clock and the standby clock can drift along with the frequency residual error of the main clock and the standby clock, so that the performance of phase jump before and after switching is reduced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a system for stably switching atomic clocks based on a real-time tracking technology, which does not need to measure frequency and phase in a time-sharing manner, ensures that a tracking period is equal to a measuring period through a real-time tracking algorithm, and ensures frequency and phase jump indexes before and after switching
The above purpose of the invention is realized by the following technical scheme:
a real-time tracking technology-based atomic clock stable switching system comprises a double mixing time difference circuit, an FPGA module, a frequency synthesis circuit, an electronic switch and an analog phase-locked loop; the FPGA module comprises a DDS module, a phase difference measuring module, an infinite impulse response digital filter module and a fault detection module;
a DDS module: receiving a frequency control signal transmitted by the infinite impulse response digital filter module; receiving an atomic clock main circuit signal transmitted from the outside, carrying out digital frequency synthesis processing on the atomic clock main circuit signal to generate a main circuit digital signal, wherein the main circuit digital signal is a frequency-adjustable main circuit digital signal under the action of a frequency control signal; sending the frequency-adjustable main circuit digital signal to a frequency synthesis circuit; receiving an atomic clock standby signal transmitted from the outside, carrying out digital frequency synthesis processing on the atomic clock standby signal to generate a standby digital signal, wherein the standby digital signal is a frequency-adjustable standby digital signal under the action of a frequency control signal; sending the frequency-adjustable standby digital signal to a frequency synthesis circuit;
the frequency synthesizer circuit: receiving a frequency-adjustable main circuit digital signal transmitted by the DDS module, performing digital-to-analog conversion processing on the frequency-adjustable main circuit digital signal to generate a main circuit analog signal, performing frequency mixing processing on the main circuit analog signal to generate two paths of main circuit frequency mixing signals, transmitting one path of main circuit frequency mixing signal to an electronic switch, and transmitting the other path of main circuit frequency mixing signal to a double frequency mixing time difference circuit; receiving a frequency-adjustable spare-path digital signal transmitted by a DDS module, performing digital-to-analog conversion processing on the frequency-adjustable spare-path digital signal to generate a spare-path analog signal, performing frequency mixing processing on the spare-path analog signal to generate two spare-path frequency mixing signals, transmitting one of the spare-path frequency mixing signals to an electronic switch, and transmitting the other spare-path frequency mixing signal to a double-frequency mixing time difference circuit;
double mixing time difference circuit: receiving a main circuit frequency mixing signal transmitted by the frequency synthesizer circuit, carrying out frequency mixing processing on the main circuit frequency mixing signal to generate a main circuit detection signal, sequentially carrying out low-pass filtering and shaping processing on the main circuit detection signal to generate two paths of processed main circuit detection signals, transmitting one path of processed main circuit detection signal to a phase difference measurement module, and transmitting the other path of processed main circuit detection signal to a fault detection module; receiving a standby mixing signal transmitted by a frequency synthesizer circuit, carrying out mixing processing on the standby mixing signal to generate a standby detection signal, sequentially carrying out low-pass filtering and shaping processing on the standby detection signal to generate two paths of processing backup detection signals, transmitting one path of the processing backup detection signals to a phase difference measuring module, and transmitting the other path of the processing backup detection signals to a fault detection module;
a phase difference measurement module: receiving a processed main circuit detection signal and a processed backup circuit detection signal transmitted by a double mixing time difference circuit, measuring a phase difference value of a main clock and a backup clock by using a high-frequency clock in an FPGA (field programmable gate array), taking the processed main circuit detection signal as a door opening signal and taking the processed backup circuit detection signal as a door closing signal, and outputting the phase difference value to an infinite pulse response digital filter module;
infinite impulse response digital filter module: receiving a phase difference value transmitted by the phase difference measuring module, filtering the phase difference value to generate a frequency control signal, and transmitting the frequency control signal to the DDS module;
a fault detection module: receiving a processed main circuit detection signal and a processed backup circuit detection signal transmitted by a double mixing time difference circuit, respectively measuring whether the processed main circuit detection signal and the processed backup circuit detection signal generate frequency hopping phase hopping, generating a switching control signal when the main circuit detection signal or the processed backup circuit detection signal generates the frequency hopping phase hopping, and outputting the switching control signal to an electronic switch;
an electronic switch: receiving a main circuit mixing signal and a standby circuit mixing signal transmitted by the frequency synthesizer circuit; receiving a switching control signal transmitted by a fault detection module; selecting one of the main-path mixing signal or the standby-path mixing signal according to the switching control signal and outputting the selected one to the analog phase-locked loop;
simulating a phase-locked loop: and receiving the main circuit mixing signal or the standby circuit mixing signal transmitted by the electronic switch, and sequentially carrying out signal phase discrimination and filtering processing on the main circuit mixing signal or the standby circuit mixing signal to generate an output signal of the whole machine.
In the atomic clock stable switching system based on the real-time tracking technology, the phase tracking precision of the atomic clock stable switching system is superior to 2ps, and the frequency tracking precision is superior to 1 e-14.
In the atomic clock stable switching system based on the real-time tracking technology, the external atomic clock main path signal and the external atomic clock main standby path signal are both 10 MHz.
In the atomic clock stable switching system based on the real-time tracking technology, the main path digital signal and the standby path digital signal are both 230 KHz; the frequency control resolution was 0.018. mu.Hz.
In the atomic clock stable switching system based on the real-time tracking technology, the main analog signal and the standby analog signal are both 230 KHz; the two main-path mixing signals and the two standby-path mixing signals are both 10.23 MHz.
In the atomic clock stable switching system based on the real-time tracking technology, the main circuit mixing signal and the standby circuit mixing signal are mixed with the common crystal oscillator of 10.229 MHz; the two processed main path detection signals and the two processed backup path detection signals are both 1 KHz.
In the atomic clock stable switching system based on the real-time tracking technology, the main circuit mixing signal or the standby circuit mixing signal and the 10.23MHz signal output by the high voltage stabilization controlled crystal oscillator VCXO are subjected to phase discrimination processing; the output signal of the whole machine is 10.23 MHz.
Compared with the prior art, the invention has the following advantages:
(1) the invention does not need to measure the phase difference and the frequency difference of the main clock and the standby clock respectively, only needs to obtain phase difference data, adopts an infinite impulse response digital filtering algorithm to carry out loop control, obtains a control signal and realizes the simultaneous tracking of the frequency and the phase. The high tracking precision is achieved on the basis of meeting the frequency range of the atomic clock. The phase tracking precision is better than 2ps, and the frequency tracking precision is better than 1 e-14;
(2) the invention has strong real-time performance of the tracking of the main clock and the standby clock, the hot standby clock can continuously keep consistent with the working clock in phase and frequency in real time after the loop is locked, the control of the hot standby clock is not delayed, and the condition that the jump of an output signal is overlarge due to the switching between two adjustment periods does not exist.
Drawings
FIG. 1 is a schematic diagram of a system for smooth switching of atomic clocks according to the present invention;
fig. 2 is a flow chart of the fault detection and autonomous handover according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and specific examples:
the DDS and the double mixing time difference circuit are used as hardware basis of the scheme, and the measurement precision of the main-standby phase difference is improved through down-conversion. And the FPGA module is used for realizing high-precision measurement of the phase difference of the main clock and the standby clock, filtering and purifying the error signal through an infinite impulse response digital filter to obtain a frequency control word of the DDS finely adjusted by the frequency control signal, and realizing loop locking. And a satellite clock rapid fault detection method is adopted in the FPGA to timely judge the rapid change fault of the working path signal and execute autonomous switching. The precision of real-time tracking of the main clock and the standby clock and the rapidity of fault detection ensure that the frequency and phase jump of output signals before and after switching are within a certain range.
The frequency synthesizer utilizes DDS technology to generate a 0.23MHz intermediate signal, which is mixed with a corresponding 10MHz signal to generate a 10.23MHz satellite reference frequency. The synchronous control function is mainly realized by FPGA software and mainly completes the following three functions: (1) and the precise tracking of two paths of 10.23MHz signals is realized. The method comprises the steps of high-precision phase discrimination of signals of a main standby path, filtering processing of error signals and fine adjustment of DDS frequency control words, and finally synchronization of signals of the hot standby path and working paths is completed. (2) And carrying out rapid fault detection on the main and standby paths of 10.23MHz signals, and generating corresponding alarm information when a certain path of signal is found to be abnormal. (3) The switching control of the satellite clock comprises two switching modes, namely autonomous switching logic under an abnormal condition and instruction switching under a normal state. The three functions supplement each other in the synchronous control process, and the continuous and reliable operation of the satellite clock under two switching modes is ensured together. After the analog phase-locked loop and the high-stability crystal oscillator link are positioned behind the electronic switch, the influence of the loop response time on the output frequency before and after switching is effectively reduced while the output 10.23MHz signal has good stability through adjusting the loop bandwidth and the time constant.
As shown in fig. 1, which is a schematic diagram of a system for smoothly switching an atomic clock, it can be known that a system for smoothly switching an atomic clock based on a real-time tracking technology is characterized in that: the device comprises a double-mixing time difference circuit, an FPGA module, a frequency synthesis circuit, an electronic switch and an analog phase-locked loop; the FPGA module comprises a DDS module, a phase difference measuring module, an infinite impulse response digital filter module and a fault detection module;
a DDS module: receiving a frequency control signal transmitted by the infinite impulse response digital filter module; receiving an atomic clock main circuit signal transmitted from the outside, carrying out digital frequency synthesis processing on the atomic clock main circuit signal to generate a main circuit digital signal, wherein the main circuit digital signal is a frequency-adjustable main circuit digital signal under the action of a frequency control signal; sending the frequency-adjustable main circuit digital signal to a frequency synthesis circuit; receiving an atomic clock standby signal transmitted from the outside, carrying out digital frequency synthesis processing on the atomic clock standby signal to generate a standby digital signal, wherein the standby digital signal is a frequency-adjustable standby digital signal under the action of a frequency control signal; sending the frequency-adjustable standby digital signal to a frequency synthesis circuit; the main circuit signal of the external atomic clock and the main circuit signal of the standby atomic clock are both 10 MHz; the main circuit digital signal and the standby circuit digital signal are both 230 KHz; the frequency control resolution was 0.018. mu.Hz.
The frequency synthesizer circuit: receiving a frequency-adjustable main circuit digital signal transmitted by the DDS module, performing digital-to-analog conversion processing on the frequency-adjustable main circuit digital signal to generate a main circuit analog signal, performing frequency mixing processing on the main circuit analog signal to generate two paths of main circuit frequency mixing signals, transmitting one path of main circuit frequency mixing signal to an electronic switch, and transmitting the other path of main circuit frequency mixing signal to a double frequency mixing time difference circuit; the method comprises the steps of receiving a frequency-adjustable spare-path digital signal transmitted by a DDS module, carrying out digital-to-analog conversion processing on the frequency-adjustable spare-path digital signal to generate a spare-path analog signal, carrying out frequency mixing processing on the spare-path analog signal to generate two spare-path frequency mixing signals, transmitting one of the spare-path frequency mixing signals to an electronic switch, and transmitting the other spare-path frequency mixing signal to a double-frequency mixing time difference circuit.
Double mixing time difference circuit: receiving a main circuit frequency mixing signal transmitted by a frequency synthesizer circuit, carrying out frequency mixing processing on the main circuit frequency mixing signal and a common crystal oscillator of 10.229MHz to generate a main circuit detection signal, sequentially carrying out low-pass filtering and shaping processing on the main circuit detection signal to generate two paths of processed main circuit detection signals, transmitting one path of processed main circuit detection signals to a phase difference measurement module, and transmitting the other path of processed main circuit detection signals to a fault detection module; receiving a standby mixing signal transmitted by a frequency synthesizer circuit, carrying out mixing processing on the standby mixing signal and a 10.229MHz public crystal oscillator to generate a standby detection signal, sequentially carrying out low-pass filtering and shaping processing on the standby detection signal to generate two paths of processing standby detection signals, transmitting one path of the processing standby detection signals to a phase difference measuring module, and transmitting the other path of the processing standby detection signals to a fault detection module; the two processed main path detection signals and the two processed backup path detection signals are both 1 KHz.
A phase difference measurement module: and receiving a processed main circuit detection signal and a processed backup circuit detection signal transmitted by the double mixing time difference circuit, measuring a phase difference value of the main clock and the backup clock by using a high-frequency clock in the FPGA, taking the processed main circuit detection signal as a door opening signal and the processed backup circuit detection signal as a door closing signal, and outputting the phase difference value to the infinite impulse response digital filter module.
Infinite impulse response digital filter module: receiving a phase difference value transmitted by the phase difference measuring module, filtering the phase difference value to generate a frequency control signal, and transmitting the frequency control signal to the DDS module;
a fault detection module: and receiving the processed main circuit detection signal and the processed backup circuit detection signal transmitted by the double mixing time difference circuit, respectively measuring whether the processed main circuit detection signal and the processed backup circuit detection signal generate frequency hopping phase hopping, generating a switching control signal when the main circuit detection signal or the processed backup circuit detection signal generates the frequency hopping phase hopping, and outputting the switching control signal to the electronic switch.
An electronic switch: receiving a main circuit mixing signal and a standby circuit mixing signal transmitted by the frequency synthesizer circuit; receiving a switching control signal transmitted by a fault detection module; and selecting one of the main-path mixing signal or the standby-path mixing signal according to the switching control signal and outputting the selected one to the analog phase-locked loop.
Simulating a phase-locked loop: receiving a main circuit mixing signal or a standby circuit mixing signal transmitted by the electronic switch, and sequentially carrying out signal phase discrimination and filtering processing on the main circuit mixing signal or the standby circuit mixing signal to generate an output signal of the whole machine; the main circuit mixing signal or the standby circuit mixing signal and a 10.23MHz signal output by the high voltage stabilization controlled crystal oscillator VCXO are subjected to phase discrimination processing; the output signal of the whole machine is 10.23 MHz.
The phase tracking precision of the atomic clock smooth switching system is better than 2ps, and the frequency tracking precision is better than 1 e-14.
Fig. 2 is a schematic flow chart of the fault detection and autonomous handover according to the present invention, which can be seen from the figure, including the following steps:
step 1, the double-mixing time difference circuit carries out down-conversion on two paths of 10.23MHz reference frequencies to obtain main and standby path 1KHz detection signals, the FPGA receives the main and standby path 1KHz detection signals, and a 61MHz high-frequency clock is used as a sampling clock to obtain high-precision main and standby phase difference data through measurement.
And 2, designing a first-order infinite impulse response digital filter in the FPGA, and setting loop parameters such as filter bandwidth and damping coefficient to balance between noise performance and dynamic range, so that loop locking can be realized within the limit accuracy range of the atomic clock, and the phase tracking precision is less than 2 ps.
And 3, superposing a direct current component on the voltage-controlled variable quantity obtained by smoothing the loop filter to obtain the adjustment quantity of the frequency control word, and acting on the DDS in an integration period to track the frequency and the phase of the hot standby circuit signal.
And 4, continuously detecting the integrity of the 10MHz and 10.23MHz reference frequencies of the atomic clock by a fault detection module in the FPGA, setting the state telemetering of the corresponding branch circuit as abnormal once signal interruption or abnormal frequency hopping and phase hopping exceeding a threshold range occurs, triggering an autonomous switching logic, and outputting a switching signal to control the electronic switch to complete switching.
And 5, re-locking the 10.23MHz signal output after the electronic switch is switched by the phase-locked loop to the 10.23MHz high voltage-stabilizing crystal control oscillator to finish the stable switching process.
In order to ensure the reliability, the system adopts a redundancy design, simultaneously receives 10MHz signals of two atomic clocks, respectively obtains main and backup 10.23MHz reference frequency signals through a main and backup frequency synthesizer, and selects one path as the reference of a phase-locked loop circuit by an electronic switch. The phase-locked loop circuit locks the output frequency of the 10.23MHz high-voltage-stabilization crystal-controlled oscillator on a reference signal, and the final output 10.23MHz signal keeps the long-term stability of a rubidium clock through reasonable parameter setting.
A real-time tracking algorithm of a master clock and a slave clock and a rapid detection method of satellite clock faults are the core of a stable satellite clock switching scheme. In order to realize precise tracking, the scheme adopts a DDS principle to generate main and standby 0.23MHz signals, and a DDS circuit adopts a 46bit phase accumulator and a frequency control word, so that the frequency control precision reaches 0.018 mu Hz. The main and standby path detection signals are obtained by a double mixing time difference method, and the main and standby phase difference measurement precision is improved to 1.6 ps. The tracking loop is ensured to have high measurement and control precision. After high-precision main and standby phase difference signals are obtained, a first-order infinite impulse response digital filter is used as a loop filter to perform PI adjustment on error signals, frequency increment signals are formed to control frequency control words of the hot standby DDS, and the whole loop is a second-order loop due to the integral characteristic of NCO, and the highest tracking precision can be obtained on the basis of meeting the dynamic range of the atomic clock frequency by reasonably selecting the loop bandwidth and the loop damping coefficient.
The real-time tracking algorithm ensures that the phases and frequencies of 10.23MHz signals of the hot standby circuit and the working circuit are kept in a synchronous state in any time period. At this time, if the working path signal has a fault, the reference frequency synthesizer autonomously switches the output signal to the hot standby path, and since the hot standby clock has tracked the working clock before, the phase frequency does not have large jump compared with the output signal after switching is completed, but the signal with the fault is transmitted through the phase-locked loop after the fault occurs and before switching is completed, and in order to reduce the sudden change of the output signal in the time period, the accuracy and the rapidity of fault detection need to be ensured at the same time. In the scheme, a fault detection module can respond to two fault modes of satellite clock signal interruption and frequency hopping phase hopping, the signal interruption fault is obtained by measuring a single-path atomic clock by using a high-precision clock, and the frequency hopping phase hopping detection needs to comprehensively judge according to the result of mutual comparison of two paths of signals besides detecting the single-path signal.
The fault detection time is an important factor influencing stable switching, the detection of signal interruption by the scheme can be completed in a plurality of 10MHz periods, and the detection time is controlled in microsecond order. The detection of the clock frequency hopping and phase hopping is finished in a plurality of periods of the detection signal and can be controlled within 10 ms. Because the loop time constant of the phase-locked loop is far greater than 10ms, abnormal signals cannot be output through the phase-locked loop in a time period after a fault occurs and before switching is completed, and the continuity of the signals in the time period is ensured.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (7)
1. The utility model provides a steady switching system of atomic clock based on real-time tracking technique which characterized in that: the device comprises a double-mixing time difference circuit, an FPGA module, a frequency synthesis circuit, an electronic switch and an analog phase-locked loop; the FPGA module comprises a DDS module, a phase difference measuring module, an infinite impulse response digital filter module and a fault detection module;
a DDS module: receiving a frequency control signal transmitted by the infinite impulse response digital filter module; receiving an atomic clock main circuit signal transmitted from the outside, carrying out digital frequency synthesis processing on the atomic clock main circuit signal to generate a main circuit digital signal, wherein the main circuit digital signal is a frequency-adjustable main circuit digital signal under the action of a frequency control signal; sending the frequency-adjustable main circuit digital signal to a frequency synthesis circuit; receiving an atomic clock standby signal transmitted from the outside, carrying out digital frequency synthesis processing on the atomic clock standby signal to generate a standby digital signal, wherein the standby digital signal is a frequency-adjustable standby digital signal under the action of a frequency control signal; sending the frequency-adjustable standby digital signal to a frequency synthesis circuit;
the frequency synthesizer circuit: receiving a frequency-adjustable main circuit digital signal transmitted by the DDS module, performing digital-to-analog conversion processing on the frequency-adjustable main circuit digital signal to generate a main circuit analog signal, performing frequency mixing processing on the main circuit analog signal to generate two paths of main circuit frequency mixing signals, transmitting one path of main circuit frequency mixing signal to an electronic switch, and transmitting the other path of main circuit frequency mixing signal to a double frequency mixing time difference circuit; receiving a frequency-adjustable spare-path digital signal transmitted by a DDS module, performing digital-to-analog conversion processing on the frequency-adjustable spare-path digital signal to generate a spare-path analog signal, performing frequency mixing processing on the spare-path analog signal to generate two spare-path frequency mixing signals, transmitting one of the spare-path frequency mixing signals to an electronic switch, and transmitting the other spare-path frequency mixing signal to a double-frequency mixing time difference circuit;
double mixing time difference circuit: receiving a main circuit frequency mixing signal transmitted by the frequency synthesizer circuit, carrying out frequency mixing processing on the main circuit frequency mixing signal to generate a main circuit detection signal, sequentially carrying out low-pass filtering and shaping processing on the main circuit detection signal to generate two paths of processed main circuit detection signals, transmitting one path of processed main circuit detection signal to a phase difference measurement module, and transmitting the other path of processed main circuit detection signal to a fault detection module; receiving a standby mixing signal transmitted by a frequency synthesizer circuit, carrying out mixing processing on the standby mixing signal to generate a standby detection signal, sequentially carrying out low-pass filtering and shaping processing on the standby detection signal to generate two paths of processing backup detection signals, transmitting one path of the processing backup detection signals to a phase difference measuring module, and transmitting the other path of the processing backup detection signals to a fault detection module;
a phase difference measurement module: receiving a processed main circuit detection signal and a processed backup circuit detection signal transmitted by a double mixing time difference circuit, measuring a phase difference value of a main clock and a backup clock by using a high-frequency clock in an FPGA (field programmable gate array), taking the processed main circuit detection signal as a door opening signal and taking the processed backup circuit detection signal as a door closing signal, and outputting the phase difference value to an infinite pulse response digital filter module;
infinite impulse response digital filter module: receiving a phase difference value transmitted by the phase difference measuring module, filtering the phase difference value to generate a frequency control signal, and transmitting the frequency control signal to the DDS module;
a fault detection module: receiving a processed main circuit detection signal and a processed backup circuit detection signal transmitted by a double mixing time difference circuit, respectively measuring whether the processed main circuit detection signal and the processed backup circuit detection signal generate frequency hopping phase hopping, generating a switching control signal when the main circuit detection signal or the processed backup circuit detection signal generates the frequency hopping phase hopping, and outputting the switching control signal to an electronic switch;
an electronic switch: receiving a main circuit mixing signal and a standby circuit mixing signal transmitted by the frequency synthesizer circuit; receiving a switching control signal transmitted by a fault detection module; selecting one of the main-path mixing signal or the standby-path mixing signal according to the switching control signal and outputting the selected one to the analog phase-locked loop;
simulating a phase-locked loop: and receiving the main circuit mixing signal or the standby circuit mixing signal transmitted by the electronic switch, and sequentially carrying out signal phase discrimination and filtering processing on the main circuit mixing signal or the standby circuit mixing signal to generate an output signal of the whole machine.
2. The atomic clock smooth switching system based on the real-time tracking technology as claimed in claim 1, wherein: the phase tracking precision of the atomic clock smooth switching system is better than 2ps, and the frequency tracking precision is better than 1 e-14.
3. The atomic clock smooth switching system based on the real-time tracking technology as claimed in claim 1, wherein: the atomic clock main path signal and the atomic clock standby path signal are both 10 MHz.
4. The atomic clock smooth switching system based on the real-time tracking technology as claimed in claim 3, wherein: the main circuit digital signal and the standby circuit digital signal are both 230 KHz; the frequency control resolution was 0.018. mu.Hz.
5. The atomic clock smooth switching system based on the real-time tracking technology as claimed in claim 1, wherein: the main circuit analog signal and the standby circuit analog signal are both 230 KHz; the two main-path mixing signals and the two standby-path mixing signals are both 10.23 MHz.
6. The atomic clock smooth switching system based on the real-time tracking technology as claimed in claim 1, wherein: the main circuit mixing signal and the standby circuit mixing signal are mixed with a common crystal oscillator of 10.229 MHz; the two processed main path detection signals and the two processed backup path detection signals are both 1 KHz.
7. The atomic clock smooth switching system based on the real-time tracking technology as claimed in claim 1, wherein: the main circuit mixing signal or the standby circuit mixing signal and a 10.23MHz signal output by the high voltage stabilization controlled crystal oscillator VCXO are subjected to phase discrimination processing; the output signal of the whole machine is 10.23 MHz.
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