CN103051335B - Frequency synthesizer and frequency combining method - Google Patents

Abstract

The invention provides a kind of frequency synthesizer, comprise one in order to provide the oscillator of a radio frequency clock, one couples oscillator, carries out phase change and provide the phase shifter of a translation radio frequency clock in order to radio frequency clock, and a time-to-digit converter, couple phase shifter, in order to quantize the time difference between a reference frequency clock and this translation radio frequency clock; Wherein, the scope contained needed for this time-to-digit converter is less than a complete cycle of this radio frequency clock.The present invention also provides a kind of frequency combining method.The present invention effectively can reduce hardware complexity.

Description

Frequency synthesizer and frequency combining method

[technical field]

The present invention about a kind of frequency synthesizer and frequency combining method, and especially in regard to a kind of frequency synthesizer of support periphery mechanism and the frequency combining method that comprise time figure conversion.

[background technology]

Communication system miscellaneous, similarly is radio frequency (RF, Radio Frequency) wireless communication system, is extensively used by advanced information society, and play an important role.One of core technology of Modern Communication System is frequency (and/or clock) synthesis, its be based on a frequency reference clock produce one have for the variable clock of frequency, with the performance making the stability of this variable clock, accuracy and frequency spectrum purity level all be associated with frequency reference clock.In the reflector of communication system, the variable clock provided by a local frequency synthesizer can be used as a local oscillations carrier wave, in order to fundamental frequency (baseband) or intermediate frequency (IF, Intermediate-Frequency) signal carries out rising the frequency translation turning (up-conversion), to form corresponding radiofrequency signal.On the other hand, in the receiver, the variable clock provided by a local frequency synthesizer can be used as a local oscillations carrier wave, is intermediate frequency/fundamental frequency signal in order to radiofrequency signal to be fallen turn (down-convert).

[summary of the invention]

In view of this, be necessary to provide a kind of frequency synthesizer and frequency combining method.

One embodiment of the invention provide a frequency synthesizer, comprise one in order to receive the frequency reference input of a frequency reference clock, one in order to provide a radio frequency clock through fine setting oscillator, one is coupled to through fine setting oscillator, in order to change the phase shifter of radio frequency clock phase place, and a time-to-digit converter, be coupled to frequency reference input and phase shifter; Wherein, the scope contained needed for time-to-digit converter is less than a complete cycle of radio frequency clock.

In one embodiment, export multiple phase places of radio frequency clock through fine setting oscillator, such as four quadrature phases (quadrature phases), and phase shifter selects one to change the phase place of radio frequency clock by this multiple phase place/quadrature phase.In one embodiment, the aggregate-value of phase shifter response frequency instruction character and select one of them by these phase places.

In one embodiment, described frequency synthesizer more comprises a translational controller, a variable phase accumulation device, a fixed phase integrating instrument and a retimer.Phase shifter is in order to change the phase place of radio frequency clock to provide a translation radio frequency clock.Time-to-digit converter provides one first decimal error correction signal in order to the time difference between response frequency reference clock and translation radio frequency clock.

Variable phase accumulation device couples through fine setting oscillator, in order to the periodicity of accumulative radio frequency clock, and provides a variable phase signal according to this.Reference clock when retimer is in order to provide one to reset when each transition place (as risen edge) of radio frequency clock resets frequency reference clock.Fixed phase integrating instrument is cumulative frequency instruction character in order to each cycle according to frequency reference clock, such as, say each transition place cumulative frequency instruction character of the reference clock when resetting.

Translational controller couples fixed phase integrating instrument and phase shifter, provides one second decimal error correction signal and a translational control signal in order to the aggregate-value (such as saying the decimal part of the aggregate-value being foundation frequency instruction character) of response frequency instruction character.Phase shifter in order to change the phase place of radio frequency clock according to translational control signal, and through fine setting oscillator in order to adjust the cycle of radio frequency clock according to the numerical value difference between the aggregate-value of frequency instruction character and variable phase signal and the numerical value summation between first and second decimal error correction signal.

In one embodiment, phase shifter makes the time difference between transition place of frequency reference clock and last transition place of translation radio frequency clock be less than a complete cycle of radio frequency clock when changing the phase place of radio frequency clock.

In one embodiment, for the scope of time figure conversion, time-to-digit converter responds when transition place of translation radio frequency clock occurs in the closely place of connecing of this scope with transition place of frequency reference clock; Then do not respond when transition place of translation radio frequency clock does not occur in the closely place of connecing of this scope with transition place of frequency reference clock.

One embodiment of the invention provide a frequency synthesizer, comprise an oscillator, a phase shifter, a translational controller, a time-to-digit converter, a fixed phase integrating instrument, a variable phase accumulation device and a retimer.Oscillator is in order to provide a variable clock; Phase shifter couples oscillator, in order to provide a translation variable clock, the phase one phase shift amount of its phase place and variable clock, and this phase shift amount makes the time difference between last transition place of transition place of a frequency reference clock and translation variable clock be less than a complete cycle of frequency reference clock.Time-to-digit converter couples phase shifter, in order to the time difference between sampling frequency reference clock and translation variable clock, and provides one first decimal error correction signal according to this.

Retimer couples oscillator and frequency reference clock, in order to when each transition place of variable clock resets frequency reference clock, and reference clock when providing to reset according to this.Fixed phase integrating instrument couples frequency reference clock, in order to each cycle each transition place of reference clock (such as when resetting) the cumulative frequency instruction character of response frequency reference clock, and provides a reference phase signal according to this.Translational controller couples phase shifter, provides one second decimal error correction signal and a translational control signal in order to respond reference phase signal.

Phase shift amount described in phase shifter sets in order to respond reference phase signal (decimal part of such as reference phase signal).In one embodiment, phase shifter comprises a frequency divider and a phase selector.Frequency divider couples oscillator, in order to the candidate displacement clock providing multiple phase place different according to variable clock.Phase selector couples frequency divider and translational controller, in order to foundation translational control signal by selecting one of them in these candidate displacement clocks as translation variable clock.

Variable phase accumulation device couples oscillator, provides a variable phase signal in order to the periodicity of cumulative variations clock.Oscillator is in order to adjust the cycle of variable clock according to reference phase signal, variable phase signal, the first decimal error correction signal and the second decimal error correction signal.

One embodiment of the invention provide a frequency synthesizer, comprise an oscillator, a time-to-digit converter, a translational controller, a phase shifter, a variable phase accumulation device and a fixed phase integrating instrument.Oscillator is in order to provide a variable clock.Time-to-digit converter provides one first decimal error correction signal in order to the time difference quantized between a frequency reference clock and a translation variable clock, wherein, and the phase place of translation variable clock and the phase one phase shift amount of variable clock.Translational controller provides one second decimal error correction signal in order to the aggregate-value of response frequency instruction character.Oscillator is more in order to adjust the cycle of variable clock according to the first decimal error correction signal, the second decimal error correction signal, the reference phase signal provided by fixed phase integrating instrument and the variable phase signal that provided by variable phase accumulation device.

One embodiment of the invention provide a kind of with the method providing a variable clock to synthesize a frequency, comprising: respond an oscillator adjustment signal and produce variable clock; By the phase deviation one phase shift amount of variable clock to obtain a translation variable clock; Further, by the time difference digitlization between translation variable clock and a frequency reference clock.Wherein, the scope that this digitlization is contained is less than the one-period of variable clock.

In one embodiment, the inventive method more comprises: adjustment phase shift amount, is less than or equal to time difference between transition place of frequency reference clock and last transition place of variable clock to make the time difference between last transition place of transition place of frequency reference clock and translation variable clock.

In one embodiment, the inventive method more comprises: each cycle according to frequency reference clock adds up a frequency instruction character to obtain the aggregate-value of frequency instruction character, and adjusts phase shift amount according to the decimal part of the aggregate-value of frequency instruction character; Obtain one first decimal error correction signal according to described digitlization, and measure to obtain one second decimal error correction signal according to phase shift, and, according to first and second decimal error correction signal adjustment oscillator adjustment signal.In one embodiment, the inventive method more comprises: select described phase shift amount by multiple phase places of variable clock.

Said frequencies synthesizer and frequency combining method effectively can reduce hardware complexity.

[accompanying drawing explanation]

What Fig. 1 illustrated is carry out digital embodiment of following the trail of to the phase place of a variable clock and a frequency reference clock.

Fig. 2 illustrates the embodiment of a time-to-digit converter.

Fig. 3 and Fig. 4 illustrates the frequency synthesizer of one embodiment of the invention and running thereof respectively.

Fig. 5 and Fig. 6 illustrates the frequency synthesizer of one embodiment of the invention and operation principles thereof respectively.

The frequency synthesizer of Fig. 7 and Fig. 8 difference one embodiment of the invention and running thereof.

Fig. 9 signal be frequency synthesizer according to one embodiment of the invention.

Figure 10 signal be an embodiment of management circuit of the present invention in Fig. 9.

Figure 11 signal be an embodiment of management circuit of the present invention in Fig. 9.

In Figure 12 example schematic 11, management circuit is according to the various runnings of one embodiment of the invention.

What Figure 13 illustrated is the schematic diagram realizing level sensor circuit in Figure 11 according to one embodiment of the invention.

[embodiment]

Please refer to Fig. 1, what it was illustrated is the conceptual embodiment of the phase place of two clock CKV and FREF being carried out to numeral tracking, is multiplied by a frequency instruction character FCW to make the frequency that the frequency of clock CKV is clock FREF.That is, by the corresponding frequency instruction character FCW of setting one, just can produce based on clock FREF the clock CKV that has expected frequence.The frequency reference clock of clock FREF to be one-period be Tr.The variable clock of clock CKV to be then one-period be Tv, it is produced by an oscillator 10, such as a numerically-controlled oscillator (DCO, Digitally Controlled Oscillator).For carrying out frequency synthesis, oscillator 10 can be finely tuned to make clock CKV to lock a clock CKR, and the frequency approach clock FREF of enable clock CKV and the product of frequency instruction character FCW, namely make average cycle T v equal Tr/FCW.Frequency instruction character FCW can make a general reference a real number, has an integer part and a decimal part; In the example in fig 1, frequency instruction character FCW is 9/4, and its integer part is 2, and decimal part then equals 1/4.

In order to will the phase place of digitally measurement clock CKV, a signal (as a numerical character) PHV [i] can be provided.Signal PHV [i] can be considered a variable phase signal, and it is in the accumulative unit count of each emphasis transition place (such as rising edge) of clock CKV; That is PHV [i+1]=PHV [i]+1, subscript i is a gomma, represent i-th emphasis transition place of clock CKV.That is, along with passage of time, the periodicity of variable phase signal PHV [i] meeting accumulative clock CKV, reflects the phase place of clock CKV in units of cycle T v.The value of signal PHV [i] is integer, because it is added up by integer and obtains.

In order to will the phase place of digitally measurement clock FREF, the phase information of clock FREF synchronously can present in emphasis transition place of clock CKV, to make the phase information of clock FREF mutually can compare with signal PHV [i], because signal PHV [i] upgrades in emphasis transition place of clock CKV.Therefore, clock FREF can by a retimer 12(as a trigger) be clock CKR when resetting.Retimer 12, in order to when each emphasis transition place of clock CKV resets clock FREF, provides clock CKR(i.e. reference clock when resetting according to this), make each transition place of clock CKR can and emphasis transition place of clock CKV align.The triggering of response clock CKR, can provide a signal PHR [k] digitally to reflect the phase place of clock FREF.Signal PHR [k] is a reference phase signal, and it is at each emphasis transition place cumulative frequency instruction character FCW of clock CKR, that is PHR [k+1]=PHR [k]+FCW, and subscript k is gomma, represents kth emphasis transition place of clock CKR.

According to the expection relation of frequency synthesis, the cycle T v that the cycle T r of clock FREF should be clock CKV is multiplied by frequency instruction character FCW, therefore, at each cycle cumulative frequency instruction character FCW of clock CKR, be the phase place for reflecting clock FREF in units of cycle T v.Because frequency instruction character FCW can have a decimal part, signal PHR [k] also can have a decimal part.

Because when clock CKR is reset by clock CKV, each emphasis transition place of clock CKR can and clock CKV in emphasis transition place align, and signal PHV [k], namely signal PHV [i] is in the value of kth emphasis transition place of clock CKR, mutually can compare with signal PHR [k].In the example in fig 1, signal PHV [i0] aligns with signal PHR [k0], and signal PHV [i0+3]=PHV [k0+1] namely can be synchronized with signal PHR [k0+1], by that analogy.As shown in Figure 1, be that clock CKR can cause an error e [k] when clock FREF being reset under the triggering of clock CKV, emphasis transition place representing clock FREF to clock CKV time emphasis transition place (i.e. immediate clock CKV emphasis transition place after this emphasis transition place of clock FREF) between time difference (phase error).

In the example in fig 1, when clock CKV is according to the relation Tv=Tr/FCW estimated during locked clock FREF, every four cycle T r can align nine cycle T v, because FCW=9/4.That is, equal accumulative nine times of unit count for four times, because FCW*4=(9/4) * 4=1*9 by accumulative for frequency instruction character FCW.Suppose that the emphasis transition of clock FREF and CKV is in time mark k0 and aligns and make signal PHR [k0] equal with PHV [i0], then after four circulations of clock CKR, emphasis transition place of clock FREF and CKV can be alignd once again, and the value of signal PHR [k0+4] also can meet the value of signal PHV [i0+9] (i.e. PHV [k0+4]), because PHR [k0+4]=PHR [k0]+FCW*4, and PHV [i0+9]=PHV [i0]+1*9.On the other hand, because frequency instruction character FCW has decimal part, even if clock CKV is locked clock FREF, but under each time mark k between time mark k0 to (k0+4), emphasis transition place of clock FREF to clock CKV time emphasis transition place between time difference can be still non-zero; This, missionary society was reflected as the numerical difference of signal PHV [k] and PHR [k] time.For example, as clock CKV locked clock FREF, at time mark (k0+1), emphasis transition place of clock FREF can lead over time emphasis transition place of clock CKV with the time difference of (3/4) * Tv, and numerical difference (PHV [k0+1]-PHR [k0+1])=(3-9/4)=3/4 between signal PHV [k0+1] and PHR [k0+1] namely reflects this time difference.Similarly, under time mark (k0+2), between emphasis transition place of clock FREF and CKV, unjustified time difference (1/2) * Tv can be reflected as (PHV [k0+2]-PHR [k0+2])=(5-18/4)=2/4=1/2.

Along with time mark k grows with each passing hour, signal PHV [k] can change with the difference (PHV [k]-PHR [k]) of PHR [k] periodic regularity, reflects certainty (nonrandom) time difference (i.e. the time difference of two clocks between emphasis transition place) (phase error) between clock FREF and CKV in units of cycle T v.Therefore, difference (PHV [k]-PHR [k]) becomes the certainty part of error e [k], and what it reflected is the rule phase difference caused by the decimal part of frequency instruction character FCW.That is as clock CKV locked clock FREF, error e [k] can equal (PHV [k]-PHR [k]), or equivalently, PHR [k]+e [k]-PHV [k]=0.

Clock FREF emphasis transition place to clock CKV time emphasis transition place between the unjustified difference of regularity can drop in the scope of a cycle T v; Equivalence, difference (PHV [k]-PHR [k]), namely the certainty part of error e [k], can be a decimal (or equalling zero).Since signal PHV [k] is integer, the certainty part of error e [k] can be associated with the decimal part of signal PHR [k].With regard to practical application, error e [k] also comprises the variation part of a random nature, the random phase error that reflection noise (noise as oscillator 10) causes.

More generally, suppose that frequency instruction character can be expressed as Nv/Nr, Nv and Nr is integer but Nv is not the integral multiple of Nr, then the certainty part of error e [k] can repeat at every Nr the periodic law of clock CKR, that is, error e [k] is equal with the certainty part of e [k+Nr], and can be predicted according to the decimal part of the aggregate-value of frequency instruction character FCW (i.e. signal PHR [k]) and signal PHV [k].Suppose that signal PHV [k0] is equal with PHR [k0] when time mark k0, if adjustment oscillator 10 just conforms to integer signal PHV [k] at interval of Nr the cycle (namely at time mark k0, (k0+Nr) etc.) of clock CKR to make the integer of signal PHR [k] part, namely imply reaching of Frequency Locking.But, Nr the cycle due to clock CKR can contain cycle of many clock CKV, if can not within every Nr the cycle of clock CKR complete monitoring error e [k], the cycle T v of clock CKV just can floating drift.For reaching meticulous PGC demodulation, a time-to-digit converter can be adopted, digitally to detect error e [k] in each cycle of clock CKR, oscillator 10 is made to export according to the digital translation of time-to-digit converter and to be adjusted, to guarantee that (PHR [k]+e [k]-PHV [k]) can at the equal convergence zero of each time mark k.

Please refer to Fig. 2, the embodiment of what it was illustrated an is time-to-digit converter 20.Time-to-digit converter 20 is coupled to two input 22a and 22b, receives two signal TDC_in and REF_in respectively; Time-to-digit converter 20 also exports a signal et [k] to export as a digital translation.When time-to-digit converter 20 is used to detect error e [k] in Fig. 1, clock FREF and CKV is received as signal REF_in and TDC_in respectively.Preferably, time-to-digit converter 20, in order to by the time difference dt digitlization (quantification) between a time emphasis transition place 16c of an emphasis transition place 16b of signal REF_in and signal TDC_in, makes error e [k] can be represented by digital signal et [k].In one embodiment, time-to-digit converter 20 is the systems meeting cause and effect (causal); Therefore it can not at time one liter of edge 16c rising edge 16b prediction signal TDC_in of signal REF_in.Therefore, desired error measures is from cycle T v, deduct time tr and indirectly reach.In one embodiment, the rise time tr between the emphasis transition place 16a of signal TDC_in and the follow-up emphasis transition place 16b of signal REF_in can be measured and quantification; Since dt=(Tv-tr), error e [k] can be derived as: e [k]=(dt/Tv)=(1-(tr/Tv)).In this embodiment, time-to-digit converter 20 does not directly produce error e [k], but the quantized value of time tr, and it by divided by cycle T v, or can be multiplied by 1/Tv_avg, and wherein, average period, Tv_avg was the long-term average of the cycle T v of variable clock CKV.Therefore, the direct output of time figure conversion is the quantized value of tr/Tv, corresponding to the negative value of error e [k].As those skilled in the art is apprehensible, in the input (discussing in Fig. 3) of adder 50, change sign, can easily reach negative value computing.So, being minimized by the difference time tr between two input signal REF_in and TDC_in, equivalence is exactly by error e [k] maximization (but its value can not be greater than 1).In formula (1-e [k]), because constant 1 can be absorbed easily in phase-lock loop system (PLL system), therefore (1-e [k]) can be designated as (-e [k]) easily.That is, for the emphasis transition place 16b of signal REF_in and two adjacent emphasis transition place 16a and the 16c of signal TDC_in, time difference between emphasis transition place 16b and follow-up emphasis transition place 16c can use error e [k] to represent, then available error (-e [the k]) representative of time difference between emphasis transition place 16b and last emphasis transition place 16a, the time difference (phase difference) that both all can be used between trace signals REF_in and TDC_in, thus visual application facilitate Analysis.

One embodiment of time-to-digit converter 20 includes the delay cell 18(such as inverter that multiple (L) is connected in series), multiple trigger 24 triggered by signal REF_in, and one yard of edge detector (code edgedetector) 26.Each delay cell 18 can introduce a unit delay time t_inv in signal TDC_in, and exports the trigger 24 of a correspondence and a time delay cell 18 to.When emphasis transition place of signal REF_in triggers each trigger 24 and obtains one by bit Q (1), Q (2) ... Q (L) formed digital time, the generation of emphasis transition place 16a can be reflected as the code edge (code edge) between bit Q (1) to Q (L); Accordingly, code edge detector 26 just can quantize rise time tr in units of unit delay time t_inv, and exports as signal et [k].That is the time quantization resolution of time-to-digit converter 20 depends on the unit delay time t_inv of each delay cell 18.The total L of delay cell 18 then determines the measuring range of time-to-digit converter 20, and this time digital translation scope can be estimated as L*t_inv.The time interval being shorter than this time digital translation scope can be detected, and the time interval of being longer than this time digital translation scope just cannot be detected by time-to-digit converter 20.When time-to-digit converter 20 is used to detect the error e [k] in Fig. 1, the scope of time figure conversion completely should contain one-period Tv.

In order to detect error e [k] to make the characteristic of clock CKV better with meticulousr resolution, unit delay time t_inv should much smaller than cycle T v.Jointly, it is extremely many that the total L of delay cell 18 that time-to-digit converter 20 needs will become, and is enough to contain cycle T v to make time figure conversion range.For example, take 7ps(1ps as 1,000,000/of microsecond) contain cycle of 2.4GHz, approximately need 60 delay cells 18 to realize time-to-digit converter 20.Delay cell more than 18 used, the power of consumption is larger, and its Interference from current caused (variation of such as supply voltage and/or reduction) is also more serious.Serious Interference from current to be settled out, just need use large-area decoupling capacitor, for thus the area realizing taking needed for an effective time-to-digit converter also will increase.Moreover the linearity that serious Interference from current also can make time figure change reduces, because unit delay time t_inv can drift about with supply voltage variation.Therefore, need the neighboring technology of support to reduce required delay cell number, and promote the linearity of time figure conversion.

Please refer to Fig. 3, what it was illustrated is according to the frequency synthesizer 30 of one embodiment of the invention.Frequency synthesizer 30 include one in order to receive a frequency instruction character FCW frequency instruction character input 32a, one in order to receive the frequency reference input 32b of a frequency reference clock FREF, fixed phase integrating instrument 34, variable phase accumulation device 36, primary Ioops filter 38, oscillator 10, phase shifter 46, translational controller 42, time-to-digit converter 40, adder 50 and a retimer 12.Oscillator 10 is in order to provide a variable clock CKV according to an oscillator adjustment character OTW, a such as radio frequency clock, can equal frequency instruction character FCW when variable clock CKV locking frequency reference clock FREF to make the frequency of variable clock CKV and be multiplied by frequency reference clock FREF.

Retimer 12 couples oscillator 10 and frequency reference clock FREF, in order to when emphasis transition place (such as rising edge) of variable clock CKV resets frequency reference clock FREF, and reference clock CKR when resetting to provide.Fixed phase integrating instrument 34 couples frequency reference clock FREF via frequency reference input 32b, in order to each cycle (such as saying each emphasis transition place of the reference clock CKR when resetting) the cumulative frequency instruction character FCW according to frequency reference clock FREF, provide a reference phase signal PHR [k] according to this.In figure 3, reference phase signal PHR [k] can be analyzed to a decimal part PHRf [k] and integer part PHRi [k].Variable phase accumulation device 36 couples oscillator 10, in order to the periodicity of cumulative variations clock CKV, provides a variable phase signal PHV [k] according to this.

Phase shifter 46 is coupled to oscillator 10 and translational controller 42, in order to change the phase place of variable clock CKV according to a translational control signal SEL, provides a translation variable clock CKV ' according to this.Or phase shifter 46 can by selecting one to carry out phase change in multiple phase places of variable clock CKV.The plurality of phase place can produce in phase shifter 46 inside.The function class of time-to-digit converter 40 is similar to the time-to-digit converter 20 shown in Fig. 2; Time-to-digit converter 40 couples phase shifter 46 and frequency reference input 32b, in order to frequency reference clock FREF and translation variable clock CKV ' is received as signal REF_in and TDC_in respectively, and provide a decimal error correction signal PHF1 [k] according to the time difference between frequency reference clock FREF and translation variable clock CKV '.That is time-to-digit converter 40 is in order to the time difference between emphasis transition place of detecting (quantification) frequency reference clock FREF and last emphasis transition place of translation variable clock CKV ', and reflects with a signal et [k] time difference detected; Decimal error correction signal PHF1 [k] measures this time difference in units of the cycle T v of variable clock CKV, its be by signal et [k] normalization to one average period Tv_avg and obtaining; Wherein, Tv_avg was the long-term average of the cycle T v of variable clock CKV, because cycle T v can make a general reference a variations per hour average period.

For with phase shifter 46 Collaboration, translational controller 42 couples phase shifter 46, in order to provide translational control signal SEL and another decimal error correction signal PHF2 [k].Adder 50 couples variable phase accumulation device 36, fixed phase integrating instrument 34, translational controller 42 and time-to-digit converter 40, in order to provide a signal PHE [k] according to reference phase signal PHR [k], variable phase signal PHV [k] and decimal error correction signal PHF1 [k] and the combinations of values (PHR [k]+PHF1 [k]+PHF2 [k]-PHV [k]) of PHF2 [k].Loop filter 38 is coupled between oscillator 10 and adder 50, provides oscillator to adjust character OTW in order to basis signal PHE [k].Via oscillator adjustment character OTW, namely oscillator 10 equivalence is the cycle length adjusting variable clock CKV according to reference phase signal PHR [k], variable phase signal PHV [k] and decimal error correction signal PHF1 [k] and PHF2 [k].

Please refer to Fig. 4, what it was illustrated is the time figure transition operation of frequency synthesizer 30 according to one embodiment of the invention.Phase shifter 46(Fig. 3) in order to introduce a phase shift amount PHoffset between variable clock CKV and translation variable clock CKV '.Due to this phase shift amount PHoffset, error (1-e [k]) between frequency reference clock FREF and last variable clock CKV can be reduced to less error (1-e ' [k]), namely reduces the difference time between frequency reference clock FREF and translation variable clock CKV '; Wherein ,-e [k]=-e ' [k]+PHoffset.In other words, phase shift amount PHoffset makes the time difference between emphasis transition place of frequency reference clock FREF and last emphasis transition place of translation variable clock CKV ' much smaller than the one-period Tv of variable clock CKV; That is, make error-e ' [k] that a part of cycle T v can not be greater than.Because translation variable clock CKV ' and frequency reference clock FREF are received as signal TDC_in and REF_in respectively, therefore a time-to-digit converter requirementization one is significantly less than the error-e ' [k] of cycle T v.That is the time figure conversion range of time-to-digit converter 40 only need contain the some of single cycle Tv, do not need completely to contain whole cycle T v.Equivalence, time-to-digit converter 40 just responds when emphasis transition place of translation variable clock CKV ' all betides the closely place of connecing of time figure conversion range with emphasis transition place of frequency reference clock FREF; When emphasis transition place of translation variable clock CKV ' and emphasis transition place of frequency reference clock FREF do not betide time figure conversion range closely meet place time, time-to-digit converter does not need to respond.Since time figure conversion range can be reduced, the delay cell that time-to-digit converter 40 only needs number less; Therefore, do not need the resolution of sacrificing time figure conversion, the hardware complexity of time-to-digit converter 40, power consumption, the layout area taken, Interference from current and nonlinearity also can effectively be reduced.

As discussed in fig. 1, error e [k] comprises change for the moment but predictable certainty part, corresponds to (PHR [k]-PHV [k]).Based on the certainty part of rule change in error-e [k], translational controller 42 dynamically can set phase shift amount PHoffset with translational control signal SEL, makes phase shift amount reduce from the certainty part of error-e [k] and to form error-e ' [k].For example, when the certainty part of error-e [k] is estimated to drop on 1/4(and be equivalent to the phase place of 90 degree) to 1/2(180 degree) scope in time, phase shift amount PHoffset can be set to 90 degree (being equivalent to 1/4), and error-e ' [k] can be maintained in the scope of 0 to 1/4.Similarly, pass in time, when error-e [k] certainty part by enter 1/2 to 3/4 scope in time, phase shift amount PHoffset is also set to 180 degree (namely cycle T v 1/2) thereupon, and error-e ' [k] is still maintained in the scope of 0 to 1/4.For compensating by the phase shift amount PHoffset reduced, translational controller 42 can inject decimal error correction signal PHF2 [k] to adder 50, to reflect phase shift amount PHoffset; Due to the error-e ' [k] that decimal error correction signal PHF1 [k] representative quantizes, therefore error-e [k] can be calculated as :-e [k]=(PHF1 [k]+PHF2 [k]), correspond to-e [k]=(-e ' [k]+PHoffset).So, when the cycle that oscillator 10 adjusts variable clock CKV so that signal PHE [k] is minimized time (when namely (PHR [k]-PHV [k]+e [k])=(PHR [k]-PHV [k]+PHF1 [k]+PHF2 [k]) being minimized, be assumed to be Equations of The Second Kind phase-lock loop herein), can frequency synthesis be reached.In other words, frequency synthesizer 30 is comparable is intended to be a digital phase-lock loop (ADPLL, All-Digital Phase Lock Loop).

In one embodiment, the variable phase signal PHV [k] of integer is a fixed point (fixed point) numerical character, is formed by WI bit.Reference phase signal PHR [k] is also certain point number word character, is formed by (WI+WF) individual bit, comprises the integer part of a WI bit and the decimal part of a WF bit.Two decimal error correction signal PHF1 [k] and PHF2 [k] can represent decimal with the fixed-point mathematics character of WF bit respectively.Signal PHE [k] is a fixed-point mathematics character with sign (signed), has (WI+WF) individual bit, comprises the integer part of a WI bit and the decimal part of a WF bit.

Please refer to Fig. 5, the phase shifter 46 of its citing signal one embodiment of the invention.In Figure 5, phase shifter 46 comprises frequency divider 44 and a phase selector 48.Frequency divider 44 couples oscillator 10, in order to carry out frequency division to variable clock CKV, with the candidate displacement clock CKVp (1) providing multiple phase place different according to variable clock CKV, CKVp (2) ..., CKVp (n) to CKVp (Np).For example, the phase place of candidate displacement clock CKVp (n) can differ (n-1) * 360/Np degree with the phase place of candidate displacement clock CKVp (1).Phase selector 48 couples frequency divider 44 and translational controller 42, selects one using as translation variable clock CKV ' in order to the translational control signal SEL according to translational controller 42 from candidate displacement clock CKVp (1) to CKVp (Np).

In one embodiment, frequency divider 44 in order to by the frequency of variable clock CKV divided by two, the candidate displacement clock CKVp (1) to CKVp (4) of four quadrature phases (quadrature phase) is provided according to this; That is, differ the phase shift amount that 90* (n-1) spends between candidate displacement clock CKVp (n) with variable clock CKV, for n=1 to 4.Please refer to Fig. 6, the time figure transition operation that what it was illustrated is based on quadrature phase.Originally, the complete distribution of error-e [k] is 360 degree (i.e. one-period Tv of variable clock CKV), but because one of them of four quadrature phases can be chosen as translation variable clock CKV ', therefore the scope of error-e [k] can be mapped to error-e ' [k] more among a small circle, it is only 90 degree, namely cycle T v 1/4th.

For example, according to reference phase signal PHR [k] decimal part PHRf [k] predict error-e [k] by enter by 0 to 90 degree scope S0 time, translational controller 42 can elect candidate displacement clock CKVp (1) as translation variable clock, in the scope that error-e ' [k] also can be spent 0 to 90; The decimal error correction signal PHF2 [k] being equivalent to 0 degree also can be injected into adder 50 by translational controller 42.When error-e [k] estimates to enter the scope S1 of 90 degree to 180 degree, translational controller 42 can change elects the candidate displacement clock CKVp (2) of 90 degree of phase places as translation variable clock CKV ', and error-e ' [k] is still restricted in the scope of 0 to 90 degree.Accordingly, the decimal error correction signal PHF2 [k] that translational controller 42 also can be equivalent to 90 degree (time in units of cycle T v 1/4) by is injected into adder 50.

Similarly, when error-e [k] will enter to the scope S2 of 180 degree to 270 degree, can be selected with the candidate displacement clock CKVp (3) of candidate displacement clock CKVp (1) difference 180 degree, make error-e ' [k] still be maintained at the scope of 0 to 90 degree; The decimal error correction signal PHF2 [k] being equivalent to 180 degree (numerical value 1/2) also can be injected into adder 50.When error-e [k] estimates to enter to the scope S3 of 270 degree to 360 degree, the candidate displacement clock CKVp (4) differing 270 degree with candidate displacement clock CKVp (1) can be selected, and allows error-e ' [k] still can be maintained at the scope of 0 to 90 degree; For compensating by the 270 degree of phase shift amounts reduced from error-e [k], the decimal error correction signal PHF2 [k] being equivalent to 270 degree can be injected into adder 50.

As shown in Figure 5, because time-to-digit converter 40 is in order to detect error-e ' [k] but not error-e [k], therefore the time figure conversion range of time-to-digit converter 40 only needs to contain 0 to 90 degree, namely variable clock CKV cycle T v 1/4th, and incomplete one-period Tv.

From the embodiment of Fig. 3 to Fig. 6, the present invention can be time-to-digit converter 40 and provides support periphery, comprises phase shifter 46 and translational controller 42.Because the certainty part become during rule in error-e [k] can be predicted based on the decimal part of reference phase signal PHR [k], therefore dynamically set the phase shift amount PHoffset of a correspondence, and it is reduced to provide another error-e ' [k] from error-e [k], make the distribution of error-e ' [k] be less than a complete cycle T v.Therefore, time figure conversion range needed for time-to-digit converter 40 just can reduce, make time-to-digit converter 40 can benefit from lower hardware complexity (such as less delay cell and/or decoupling capacitor), lower power consumption, less layout area, lower Interference from current, and the linearity of time figure conversion can be promoted, and do not need the resolution of sacrificing time figure conversion.Translational controller 42 available digital logical circuit realizes.

Please refer to Fig. 7, what it was illustrated is according to the frequency synthesizer 60 of one embodiment of the invention.The frequency synthesizer 60 be similar in the frequency synthesizer 30, Fig. 7 shown in Fig. 3 include one in order to receive a frequency instruction character FCW frequency instruction character input 32a, one in order to receive the frequency reference input 32b of a frequency reference clock FREF, fixed phase integrating instrument 34, variable phase accumulation device 36, primary Ioops filter 38, oscillator 10, translational controller 62, phase shifter 66, time-to-digit converter 40, adder 50 and a retimer 12.Oscillator 10 provides a variable clock CKV according to an oscillator adjustment character OTW, a such as radio frequency clock, with make the frequency of variable clock CKV equal when variable clock CKV locking frequency reference clock FREF frequency that frequency instruction character FCW is multiplied by frequency reference clock FREF.In frequency synthesizer 60, running and the function of fixed phase integrating instrument 34, variable phase accumulation device 36, time-to-digit converter 40, adder 50 and retimer 12 can be learnt by the similar elements inference in Fig. 3 frequency synthesizer 30.Variable phase accumulation device 36 couples oscillator 10, in order in the accumulative unit count of each emphasis transition place of variable clock CKV, provides a variable phase signal PHV [k] according to this.According to reference clock CKR during the resetting of retimer 12, emphasis transition place of reference clock CKR when fixed phase integrating instrument 34 response resets and cumulative frequency instruction character FCW, to provide a reference phase signal PHR [k].

Phase shifter 66, such as one digit time transducer (DTC, digital-to-time Converter), be coupled to frequency reference input 32b and time-to-digit converter 40, in order to postpone frequency reference clock FREF(according to a translational control signal SEL or to change its phase place), a translation reference clock FREF ' is provided according to this.Variable clock CKV and translation reference clock FREF ' inputs to time-to-digit converter 40 respectively as signal TDC_in and REF_in, therefore time-to-digit converter 40 detects (quantification) is error-e ' [k] (time difference) between emphasis transition place and last emphasis transition place of variable clock CKV of translation reference clock FREF ', and provide a decimal error correction signal PHF1 [k] according to this responsively.For with phase shifter 66 Collaboration, translational controller 62(such as one digit time conversion compensator) be coupled to phase shifter 66 and adder 50, a translational control signal (as a converting digital controls) SEL and another decimal error correction signal PHF2 [k] are provided in order to the decimal part PHRf [k] according to reference phase signal PHR [k].At translational controller 62 with under the support of phase shifter 66, the time figure conversion range of time-to-digit converter 40 can be less than a part of variable clock CKV cycle T v.

Please refer to Fig. 8, the Collaboration situation of phase shifter 66 that what it was illustrated is, translational controller 62 and time-to-digit converter 40.Between emphasis transition place of frequency reference clock FREF and last emphasis transition place of variable clock CKV, have error-e [k], and namely PGC demodulation needs the relevant information of this error-e [k]; To this, translational controller 62 can dynamically adjust translational control signal SEL and decimal error correction signal PHF2 [k] according to the decimal part of reference phase signal PHR [k], makes translational control signal SEL and decimal error correction signal PHF2 [k] can follow the certainty part of error-e [k] and upgrade.Phase shifter 66 is in order to make the phase change of frequency reference clock FREF (namely equivalence a postpones) phase shift amount PHdelay; This phase shift amount PHdelay is according to set by translational control signal SEL, it is the part making the error-e ' [k] between last emphasis transition place of emphasis transition place of translation reference clock FREF ' and variable clock CKV be less than cycle T v, is also less than or equal to error-e [k].Equivalently, phase shift amount PHdelay can be formed error-e ' [k] by reducing in error-e [k].Because the time-to-digit converter 40 error-e ' [k] that only requirementization is less but not error-e [k], therefore time-to-digit converter 40 can benefit from less time figure conversion range.The phase shift amount PHdelay that decimal error correction signal PHF2 [k] reduces in order to compensation, as illustrated in figs. 7 and 8.

For example, when in the scope of error-e [k] 1/4 to 1/2, phase shift amount PHdelay can be preferably set as (1/4) * Tv by translational controller 62, makes the required error-e ' [k] measured of time-to-digit converter 40 can between the scope of 0 to 1/4.When in the scope of error-e [k] 1/2 to 3/4, translational controller 62 can change phase shift amount PHdelay is preferably set as (1/2) * Tv, make the required error-e ' [k] measured of time-to-digit converter 40 still maintain the scope of 0 to 1/4, and non-zero to 1 full breadth.Because time-to-digit converter 40 responds when transition place of variable clock CKV occurs in the closely place of connecing of time figure conversion range with transition place of translation reference clock FREF ', then do not respond when transition place of variable clock CKV does not occur in the closely place of connecing of time figure conversion range with transition place of translation reference clock FREF ', therefore the hardware complexity of time-to-digit converter 40 (delay cell number as required) can effectively reduce, contribute to the improvement of the minimizing of power consumption, the reduction of Interference from current and the linearity.

In one embodiment, the frequency of frequency reference clock FREF is far below the frequency of radio frequency variable clock CKV, therefore phase shifter 66 only need operate in low speed.In one embodiment, phase shifter 66 with one digit time transducer realize, in order to the translational control signal SEL(of numeral and converting digital are controlled) be converted to a phase shift amount PHdelay(i.e. time of delay).This transducer available digital programmable delay line digit time (digitally programmable delay line) realizes.For guaranteeing that suitable vulnerability to jamming (immunity) is to resist processing procedure, supply power voltage and temperature variations, frequency synthesizer 60 can comprise correlation-corrected mechanism and/or the program of transducer digit time.

In the embodiment of Fig. 3, Fig. 5 and Fig. 7, oscillator 10 is the oscillators through fine setting; It is through adjusting to make variable clock CKV be able to track frequency reference clock FREF.The signal PHE [k] provided by adder 50 can feedback to oscillator 10 via loop filter 38, makes variable clock CKV be able to be finely tuned better further.In one embodiment, loop filter 38 is wave digital lowpass filters.Loop filter 38 can use finite impulse response (FIR) (FIR, Finite Impulse Response) filter and infinite impulse response (IIR, Infinite Impulse Response) filter bank framework to form.For example, in an embodiment, loop filter 38 linearly composite signal PHE and signal PHE aggregate-value and provide oscillator to adjust character, make frequency synthesizer be Equations of The Second Kind loop.

In the embodiment of Fig. 3, Fig. 5 and Fig. 7, time-to-digit converter 40 receives translation variable clock CKV ' (Fig. 3 and Fig. 5) at a high speed or variable clock CKV(Fig. 7) as signal TDC_in, and receive the frequency reference clock FREF (Fig. 3 and Fig. 5) of low speed or translation reference clock FREF ' (Fig. 7) as signal REF_in.Time difference between time-to-digit converter 40 quantized signal TDC_in and REF_in, and upgrade decimal error correction signal PHF1 [k] in each emphasis transition place of signal REF_in.But the renewal no matter whether decimal error correction signal PHF1 [k] is triggered, time-to-digit converter 40 all can receive the signal TDC_in of high speed thixotroping (toggling) constantly.High speed thixotroping can consume much power, causes serious Interference from current, and the related linearity deterioration that time figure is changed.For solving this difficult point, the present invention suppresses non-essential pulse in signal TDC_in with a power management mechanism, only retain time immediate Sing plus of emphasis transition place leading over signal REF_in, reduce power consumption and Interference from current accordingly, and normal time figure conversion also can not be affected.

Please refer to Fig. 9, what it was illustrated is according to the frequency synthesizer 70 of one embodiment of the invention.Be similar to frequency synthesizer 30 and 60, frequency synthesizer 70 comprises the frequency instruction character input 32a receiving a frequency instruction character FCW, in order to receive the frequency reference input 32b of a frequency reference clock FREF, in order to produce the oscillator 10 of a variable clock CKV, in order to when each emphasis transition place of variable clock CKV resets frequency reference clock FREF to provide one to reset time reference clock CKR retimer 12, according to reference clock CKR cumulative frequency instruction character FCW when resetting to provide the fixed phase integrating instrument 34 of a reference phase signal PHR [k], count at each emphasis transition place accumulative units of variable clock CKV with the variable phase accumulation device 36 providing a variable phase signal PHV [k], the time-to-digit converter 80 of one decimal error correction signal PHF1 [k] was also provided according to this in order to the time difference between quantized signal TDC_in and REF_in, in order to provide the adder 50 of signal PHE [k], and loop filter 38, an oscillator adjustment character OTW is provided to oscillator 10 in order to response signal PHE [k].

Moreover, frequency synthesizer 70 more comprise one in order to receive a signal TDC_in0 variable input end of clock 78a, one in order to receive frequency reference input 78b, translational controller 72, phase shifter 76 and a management circuit 74 of a signal REF_in0.Translational controller 72 provides another decimal error correction signal PHF2 [k] and a translational control signal SEL in order to the decimal part PHRf [k] according to reference phase signal PHR [k], makes adder 50 numerical difference (PHR [k]-PHV [k]) can be added with numerical value and (PHF1 [k]+PHF2 [k]) and provide signal PHE [k].Phase shifter 76 couples translational controller 72, and in order to change the phase place of variable clock CKV or frequency reference clock FREF, and signal TDC_in0 and REF_in0 just provides according to variable clock CKV and frequency reference clock FREF respectively.Management circuit 74 couples variable input end of clock 78a and frequency reference input 78b, and outputs signal REF_in and TDC_in; Wherein, signal TDC_in is provided as the Sing plus in signal TDC_in0, and it leads over time emphasis transition place of signal REF_in.

In one embodiment, translational controller 72 is similar to translational controller 42 and phase shifter 46(Fig. 3 with the Collaboration of phase shifter 76) Collaboration; Phase shifter 76 responds translational control signal SEL and by the phase change one phase shift amount PHoffset of variable clock CKV, and provides translation variable clock CKV ' as signal TDC_in0 accordingly.Translational controller 72 injects decimal error correction signal PHF2 [k] and is then provided to management circuit 74 using as signal REF_in0 with compensation of phase translational movement PHoffset, frequency reference clock FREF.

In another embodiment, translational controller 72 is then similar to translational controller 62 and phase shifter 66(Fig. 7 with the Collaboration of phase shifter 76) Collaboration; Frequency reference clock FREF is postponed a phase shift amount PHdelay according to translational control signal SEL by phase shifter 76, provides a translation reference clock FREF ' using as signal REF_in0 accordingly.Translational controller 72 injects decimal error correction signal PHF2 [k] with compensation of phase translational movement PHdelay, and variable clock CKV is then provided to management circuit 74 using as signal TDC_in0.

Via the Collaboration of translational controller 72 with phase shifter 76, the time difference (i.e. error-e ' [k]) between signal TDC_in0 and REF_in0 just can be distributed in a scope being less than complete cycle Tv.

Please refer to Figure 10, what it was illustrated is according to the management circuit 74A of one embodiment of the invention, and it can in order to realize the management circuit 74 shown in Fig. 9.Management circuit 74A comprises two gate 82a and 82b, and a delayer (delay element) 82c.Gate 82a couples signal REF_in0 and REF_in in two inputs, and the result in order to logical operation between basis signal REF_in0 and REF_in (as to the anti-phase work of signal REF_in0 and signal REF_in and computing) provides a bolt (gating) signal CON.Delayer 82c couples signal REF_in0 and gate 82a, in order to signal REF_in0 is postponed one time of delay Tdelay and signal REF_in is provided.Gate 82b couples latch signal CON and signal TDC_in0 respectively in its two input, in order between basis signal TDC_in0 and latch signal CON and the result of computing and provide signal TDC_in.

As signal REF_in0 at an emphasis transition place 84a by logical zero transition to logical one, gate 82a is in order to be set as logical one by latch signal CON; As signal REF_in at emphasis transition place 84b by logical zero transition to logical one, gate 82a is in order to set back logical zero by latch signal CON.So, latch signal CON will the window maintaining a logical one time of delay in Tdelay between emphasis transition place 84a and 84b.When latch signal CON is logical zero, gate 82b is in order to suppress the pulse in signal TDC_in0; When latch signal CON is logical one, gate 82b provides Sing plus 86a in order to follow signal TDC_in0 for signal TDC_in, and it can lead over a time emphasis transition place 84b.In other words, when basis signal TDC_in0 provides signal TDC_in, only have Sing plus 86a can be retained in signal TDC_in, other the inessential pulses in signal TDC_in0, such as pulse 86b and 86c, all can be suppressed by latch signal CON.Signal REF_in and TDC_in can be transferred to time-to-digit converter 80, and when time-to-digit converter 80 for the emphasis transition place 84c of pulse 86a and signal REF_in a time emphasis transition place 84b between time interval THA detect time difference corresponding to (quantification) time, error-e ' [k] can be obtained.

By suppressing inessential pulse and retained Sing plus before time emphasis transition place of signal REF_in, the high speed thixotroping to time-to-digit converter 80 can be avoided, also can not the normal function of influence time digital quantizer 80; Therefore, power consumption can effectively reduce, and the linearity of time figure conversion also can improve because Interference from current is suppressed thereupon.After the emphasis transition place 84b of signal REF_in, no matter whether there are another (or several) other pulses (such as pulse 86d) in signal TDC_in, the correct running of time-to-digit converter 80 all can not be influenced, because time interval THA can before emphasis transition place 86d just measured (renewal).But, other pulses in signal TDC_in, can cause negative effect to the running of voltage supply network, therefore these pulses are imperfect and lock of should trying one's best removes.

Due to translational controller 72 and the Collaboration of phase shifter 76, between signal TDC_in0 and REF_in0, the length of error-e ' [k] can drop in the time figure conversion range also shorter than a cycle T v, and time of delay, Tdelay can be set to be less than cycle T v.Otherwise, if the length of error-e ' [k] is distributed in a complete cycle Tv, time of delay, Tdelay just must be also longer than cycle T v, to guarantee that the window of Tdelay time of delay still can capture at least one emphasis transition place under the duration aspect that error-e ' [k] is longer in signal TDC_in.But, if time of delay, Tdelay was longer than cycle T v, its window can tend to catch multiple pulse in signal TDC_in, and therefore the linearity of time figure conversion also just reduces, understand because of the unnecessary pulse before the transition place 84b that attaches most importance to and cause higher Interference from current when measuring intervals of TIME THA.

For the suitable set point of Tdelay time of delay, time of delay, the lower limit of Tdelay was time figure conversion range, and the setting of its upper limit is then will avoid multiple-pulse before emphasis transition place 84b.Therefore, time of delay, the tolerable variation of Tdelay was positive and negative (Tv/2-Tc)/2, and wherein namely Tc represents time figure conversion range.

Please refer to Figure 11 and Figure 12; Figure 11 signal be that what to illustrate according to another management circuit 74B, Figure 12 of one embodiment of the invention is then management circuit 74B running in its two different states.Management circuit 74B can in order to realize the management circuit 74 shown in Fig. 9.Management circuit 74B comprises two gate 82a and 82b, a delayer 82c and a level sensor circuit 82d.Two inputs of gate 82a couple signal REF_in0 and REF_in respectively, and the result in order to logical operation between basis signal REF_in0 and REF_in provides a latch signal CON.Delayer 82c couples signal REF_in0 and gate 82a, in order to signal REF_in0 is postponed one time of delay Tdelay and signal REF_in is provided.Two inputs of level sensor circuit 82d couple signal TDC_in0 and latch signal CON, provide another latch signal CON ' in order to basis signal TDC_in0 and latch signal CON.Two inputs of gate 82b couple latch signal CON ' and signal TDC_in0, in order to provide signal TDC_in with the result of computing between basis signal TDC_in0 and latch signal CON '.

As shown in figure 12, be logical one at emphasis transition place 84a by logical zero transition as signal REF_in0, gate 82a is in order to be set as logical one by latch signal CON; Be logical one at emphasis transition place 84b by logical zero transition as signal REF_in, gate 82a is in order to set back logical zero by latch signal CON.As shown in the situation 1 of Figure 12, when latch signal CON is when transition place 90a is logical one by logical zero transition, if signal TDC_in0 is logical zero, then level sensor circuit 82d is in order to be set as logical one at transition place 90b by latch signal CON '.On the other hand, as shown in the situation 2 of Figure 12, when latch signal CON is when transition place 90a is logical one by logical zero transition, if signal TDC_in0 is logical one, then level sensor circuit 82d can wait signal TDC_in0 just at transition place 90c, latch signal CON ' to be set as logical one when logical zero is returned in transition after a while.Level sensor circuit 82d is more in order to set back logical zero when logical zero is returned in latch signal CON transition by latch signal CON '.In other words, at latch signal CON in the window that time of delay, Tdelay opened, when signal TDC_in0 is logical zero, level sensor circuit 82d can open a Second Window in latch signal CON '.

When latch signal CON ' is logical zero, gate 82b in order to suppress the pulse in signal TDC_in0, as pulse 88a and 88b.When latch signal CON ' is logical one, gate 82b then in order to follow signal TDC_in0 and to provide a Sing plus 86a for signal TDC_in, makes signal TDC_in before the emphasis transition place 84b of signal REF_in, only have the single emphasis transition place 84c of pulse 86a.Time-to-digit converter 80 can be measured the period between emphasis transition place 84c and 84b and detect error-e ' [k].In signal TDC_in, because only having Sing plus 86a before the transition place 84b that attaches most importance to, therefore the inessential thixotroping of time-to-digit converter 80 can be avoided, and promote the linearity of time-to-digit converter 80.

As shown in the situation 2 of Figure 12, if with latch signal CON grid except the pulse in (gate) signal TDC_in0, at emphasis transition place 90a and fall and have a unnecessary pulse between edge transition place 90d and be included in signal TDC_in, and this unnecessary pulse will reduce the linearity of time-to-digit converter 80.But because level sensor circuit 82d can avoid the period that signal TDC_in0 is logical one adaptively, therefore unnecessary pulse got rid of by the narrower window of available latch signal CON '; So, Sing plus is only had before just can guaranteeing emphasis transition place 84b, to safeguard the linearity.Under the running of level sensor circuit 82d, management circuit 74B can be more strong, has preferably vulnerability to jamming to variation time of delay of delayer 82c because time of delay Tdelay tolerable postpone variation can extended be positive and negative (Tv-Tc)/2.

Please refer to Figure 13, an example of what it was illustrated is level sensor circuit 82d, it includes inverter 94 and a SR latch, and this SR latch is formed by two NAND gate 92a and 92b.Two inputs of NAND gate 92a and an output couple signal TDC_in0, node n0 and node n1 respectively.Two inputs of NAND gate 92b and an output then couple latch signal CON, node n1 and node n0 respectively.Inverter 94 is coupled between NAND gate 92b and gate 82b.When signal TDC_in0 is logical one, latch signal CON ' can be latched as logical zero, and when signal TDC_in0 is logical zero, latch signal CON ' just can be released and be followed latch signal CON.

Sum up, the present invention is that the time-to-digit converter in digital frequency synthesizer provides relevant support periphery.When with time difference (phase error) between digital frequency synthesizer monitored variable clock and frequency reference clock, one of them phase place of variable clock and frequency reference clock can according to the aggregate-value translation adaptively of frequency instruction character, to make the described time difference can be maintained within the partial periodicity of variable clock, time figure conversion range also just can be set to the complete cycle being shorter than variable clock.Moreover, present and also can be removed by lock to the inessential high frequency thixotroping pulse to time-to-digit converter, and the normal function of not influence time digital translation.Less time figure conversion range and the lock of thixotroping bring many advantages except can be frequency synthesizer, the linearity improvement such as making time figure change, the demand reducing hardware complexity, reduce power consumption, reduce layout area, reduce decoupling capacitor, and can Interference from current be suppressed.

Claims (28)

1. a frequency synthesizer, is characterized in that, this frequency synthesizer comprises:

One frequency reference input, in order to receive a frequency reference clock;

Once fine setting oscillator, in order to provide a radio frequency clock;

One phase shifter, couples this through fine setting oscillator, in order to change the phase place of this radio frequency clock; And

One time-to-digit converter, couples this frequency reference input and this phase shifter, and wherein, the scope contained needed for this time-to-digit converter is less than a complete cycle of this radio frequency clock.

2. frequency synthesizer as claimed in claim 1, is characterized in that, wherein, this exports multiple phase places of this radio frequency clock through fine setting oscillator, and this phase shifter selects the plurality of phase place one of them.

3. frequency synthesizer as claimed in claim 1, is characterized in that, wherein, this exports multiple quadrature phases of this radio frequency clock through fine setting oscillator, and this phase shifter selects the plurality of quadrature phase one of them.

4. frequency synthesizer as claimed in claim 1, is characterized in that, wherein, this exports multiple phase places of this radio frequency clock through fine setting oscillator, and this phase shifter responds the aggregate-value of a frequency instruction character and selects one of them of the plurality of phase place.

5. frequency synthesizer as claimed in claim 1, it is characterized in that, wherein, this phase shifter is in order to change the phase place of this radio frequency clock to provide a translation radio frequency clock, this time-to-digit converter responds the time difference between this frequency reference clock and this translation radio frequency clock in order to digitlization and provides one first decimal error correction signal, and this frequency synthesizer more comprises:

One translational controller, provides one second decimal error correction signal in order to respond the aggregate-value of a frequency instruction character;

Wherein, this is through finely tuning oscillator in order to adjust the cycle of this radio frequency clock according to this first decimal error correction signal and this second decimal error correction signal.

6. frequency synthesizer as claimed in claim 5, it is characterized in that, this frequency synthesizer more comprises:

One variable phase accumulation device, couples this through fine setting oscillator, in order to the periodicity of this radio frequency clock accumulative, and provides a variable phase signal according to this; And

One fixed phase integrating instrument, adds up this frequency instruction character in order to respond each cycle of this frequency reference clock, and provides the aggregate-value of this frequency instruction character according to this;

Wherein, this more adjusts the cycle of this radio frequency clock according to the aggregate-value of this variable phase signal and this frequency instruction character through fine setting oscillator.

7. frequency synthesizer as claimed in claim 6, it is characterized in that, this frequency synthesizer more comprises:

One retimer, in order to the reference clock when transition place of this radio frequency clock retimes to provide to reset to this frequency reference clock;

Wherein, this fixed phase integrating instrument adds up this frequency instruction character in order to transition place of the reference clock when this resets.

8. frequency synthesizer as claimed in claim 6, it is characterized in that, wherein, this through fine setting oscillator in order to according to the difference between the aggregate-value of this frequency instruction character and this variable phase signal and this first decimal error correction signal and this second decimal error correction signal with and adjust cycle of this radio frequency clock.

9. frequency synthesizer as claimed in claim 5, it is characterized in that, wherein, this translational controller couples this phase shifter, more provide a translational control signal in order to respond the aggregate-value of this frequency instruction character, and this phase shifter is in order to change the phase place of this radio frequency clock according to this translational control signal.

10. frequency synthesizer as claimed in claim 9, it is characterized in that, wherein this translational controller provides this second decimal error correction signal and this translational control signal in order to the decimal part of the aggregate-value according to this frequency instruction character.

11. frequency synthesizers as claimed in claim 1, it is characterized in that, wherein this phase shifter is in order to change the phase place of this radio frequency clock and to provide a translation radio frequency clock according to this, with the complete cycle making the time difference between transition place of this frequency reference clock and last transition place of this translation radio frequency clock be less than this radio frequency clock.

12. frequency synthesizers as claimed in claim 1, it is characterized in that, wherein this time-to-digit converter responds when transition place of radio frequency clock after this change occurs in the closely place of connecing of this scope with transition place of this frequency reference clock, then do not respond when transition place of radio frequency clock after this change does not occur in the closely place of connecing of this scope with transition place of this frequency reference clock.

13. 1 frequency synthesizers, is characterized in that, this frequency synthesizer comprises:

One oscillator, in order to provide a variable clock;

One phase shifter, couple this oscillator, in order to provide a translation variable clock, the phase place of this translation variable clock is made to differ a phase shift amount with the phasetophase of this variable clock, wherein, the one-period of this phase shift amount in order to make the time difference between last transition place of transition place of a frequency reference clock and this translation variable clock be less than this variable clock; And

One time-to-digit converter, couples this phase shifter, provides one first decimal error correction signal for quantizing this time difference.

14. frequency synthesizers as claimed in claim 13, it is characterized in that, this frequency synthesizer more comprises:

One fixed phase integrating instrument, in order to respond each cycle of this frequency reference clock, an accumulative frequency instruction character also provides a reference phase signal according to this;

Wherein, this phase shifter sets this phase shift amount in order to respond this reference phase signal.

15. frequency synthesizers as claimed in claim 14, it is characterized in that, this frequency synthesizer more comprises:

One translational controller, couples this phase shifter, for responding this reference phase signal to provide one second decimal error correction signal;

Wherein, this oscillator is in order to adjust the cycle of this variable clock according to this first decimal error correction signal and this second decimal error correction signal.

16. frequency synthesizers as described in claim the 15, it is characterized in that, this frequency synthesizer more comprises:

One retimer, in order to the reference clock when transition place of this variable clock retimes to provide to reset accordingly to this frequency reference clock, wherein this fixed phase integrating instrument adds up this frequency instruction character in order to transition place of the reference clock when this resets; And

One variable phase accumulation device, couples this oscillator, in order to add up the periodicity of this variable clock to provide a variable phase signal;

Wherein, this oscillator more adjusts the cycle of this variable clock according to this variable phase signal and this reference phase signal.

17. frequency synthesizers as claimed in claim 15, is characterized in that, wherein, this translational controller is more in order to respond this reference phase signal to provide a translational control signal, and this phase shifter comprises:

One frequency divider, couples this oscillator, in order to the candidate displacement clock providing multiple phase place different according to this variable clock; And

One phase selector, couples this frequency divider and this translational controller, in order to according to this translational control signal by selecting one of them in those candidate displacement clocks as this translation variable clock.

18. 1 frequency synthesizers, is characterized in that, this frequency synthesizer comprises:

One oscillator, in order to provide a variable clock;

One time-to-digit converter, in order to the time difference between a frequency reference clock and a translation variable clock is quantized to provide one first decimal error correction signal, wherein, the phase place of this translation variable clock and the phase one phase shift amount of this variable clock; And

One translational controller, in order to respond the aggregate-value of a frequency instruction character to provide one second decimal error signal;

Wherein, this oscillator is more in order to adjust the cycle of this variable clock according to this first decimal error correction signal and this second decimal error correction signal.

19. frequency synthesizers as claimed in claim 18, it is characterized in that, this frequency synthesizer more comprises:

One phase shifter, couples this oscillator, in order to provide this translation variable clock.

20. frequency synthesizers as claimed in claim 18, it is characterized in that, this frequency synthesizer more comprises:

One fixed phase integrating instrument, adds up this frequency instruction character to provide the aggregate-value of this frequency instruction character in order to respond each cycle of this frequency reference clock.

21. frequency synthesizers as claimed in claim 20, it is characterized in that, this frequency synthesizer more comprises:

One variable phase accumulation device, couples this oscillator, in order to add up the periodicity of this variable clock to provide a variable phase signal;

Wherein, this oscillator more according to this variable phase signal and this frequency instruction character aggregate-value and adjust cycle of this variable clock.

22. 1 kinds of frequency combining methods, is characterized in that, this frequency combining method comprises:

Respond an oscillator adjustment signal to produce a variable clock;

By the phase deviation one phase shift amount of this variable clock to obtain a translation variable clock; And

By the time difference digitlization between this translation variable clock and a frequency reference clock, this scope of carrying out the digitized time difference is less than the one-period of this variable clock.

23. frequency combining methods as claimed in claim 22, is characterized in that, carry out the time difference between last transition place that this time difference digitized is this frequency reference clock one transition place and this translation variable clock.

24. frequency combining methods as claimed in claim 23, it is characterized in that, this frequency combining method more comprises:

Adjust this phase shift amount, make this time difference be less than or equal to time difference between transition place of this frequency reference clock and last transition place of this variable clock.

25. frequency combining methods as claimed in claim 24, it is characterized in that, this frequency combining method more comprises:

Each cycle according to this frequency reference clock adds up a frequency instruction character to obtain the aggregate-value of this frequency instruction character; And

Decimal part according to the aggregate-value of this frequency instruction character adjusts this phase shift amount.

26. frequency combining methods as claimed in claim 25, it is characterized in that, this frequency combining method more comprises:

One first decimal error correction signal is obtained according to this digitlization; And

This oscillator adjustment signal is adjusted according to this first decimal error correction signal.

27. frequency combining methods as claimed in claim 26, it is characterized in that, this frequency combining method more comprises:

One second decimal error correction signal is measured to obtain according to this phase shift;

More adjust this oscillator adjustment signal according to this second decimal error correction signal.

28. frequency combining methods as claimed in claim 24, it is characterized in that, this frequency combining method more comprises:

This phase shift amount is selected by multiple phase places of this variable clock.