CN102013970B - Clock synchronization method and device thereof as well as base station clock device - Google Patents
Clock synchronization method and device thereof as well as base station clock device Download PDFInfo
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- CN102013970B CN102013970B CN 201010602515 CN201010602515A CN102013970B CN 102013970 B CN102013970 B CN 102013970B CN 201010602515 CN201010602515 CN 201010602515 CN 201010602515 A CN201010602515 A CN 201010602515A CN 102013970 B CN102013970 B CN 102013970B
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Abstract
The embodiment of the invention discloses an IEEE1588 based clock synchronization method and device thereof as well as a base station clock device. The method comprises: data messages are exchanged between a secondary clock at a base station side and a system main clock by virtue of Ethernet, thus realizing clock synchronization; after synchronization, the crystal oscillator count value of the secondary clock and the crystal oscillator count value of a local clock at the base station are acquired; the crystal oscillator count value of the secondary clock and the crystal oscillator count value of the local clock are taken as a reference source, and the adjusted value of the local clock is calculated; and the adjusted value is utilized to adjust the local clock, so that the local clock outputs a clock signal synchronous with the main clock. In the embodiment of the invention, a 1588 message protocol is utilized, and the crystal oscillator count value is adopted to substitute the count value of an external clock signal under the condition that the local clock has no reliable external clock signal input, thus realizing accurate synchronization between the local clock at the base station side and the main clock.
Description
Technical field
The application relates to communication technical field, particularly relates to a kind of clock synchronizing method based on the IEEE1588 agreement, device and base station clock equipment.
Background technology
Clock is exactly the clock alignment that is distributed in various places synchronously, can select a clock as the standard time clock (also can be described as master clock) of system, other clocks (also can be described as local from clock) in the system are compared with standard time clock, and other clocks and system standard clock is synchronous in the realization system.In the prior art, local clock needs the outside reliable clock source of input when synchronous, with the input reference clock signal of this reliable clock source as local clock, realize that the clock between local clock and the master clock is synchronous.Usually outside reliable clock source is provided by 1588 controllers, and this reliable clock source is often referred to the 1PPS clock signal.
The inventor finds that in the research process to prior art in the communication environment of developing based on the IEEE1588 agreement, if the 1PPS clock signal that can't obtain outside reliable clock source of local clock, then local clock and master clock can't be realized synchronously.
Summary of the invention
The embodiment of the present application provides a kind of clock synchronizing method based on the IEEE1588 agreement, device and base station clock equipment, in the time of can't obtaining reliable clock source signals to solve existing local clock, is difficult to realize synchronous problem with master clock.
In order to solve the problems of the technologies described above, the embodiment of the present application discloses following technical scheme:
A kind of clock synchronizing method based on IEEE1588 comprises:
Base station side realize that by Ethernet interaction data message clock is synchronous from clock and system's master clock;
After synchronously, obtain described from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock;
The crystal oscillator count value of described crystal oscillator count value from clock and described local clock as the reference source, is calculated the adjusted value of local clock;
By described adjusted value local clock is adjusted, so that the output of described local clock and described master clock clock signal synchronous.
Described obtaining from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock comprises:
Receive first data message and second data message that described master clock sends continuously;
When receiving described first data message, read described from the first crystal oscillator count value of clock and the first crystal oscillator count value of described local clock, and when receiving described second data message, from described second data message, read described from the second crystal oscillator count value of clock and the second crystal oscillator count value of described local clock.
The adjusted value of described calculating local clock comprises:
By calculating described from the first crystal oscillator count value of clock and the time interval of the second crystal oscillator count value from the standard crystal oscillator count value of clock, the described first crystal oscillator count value and the second crystal oscillator count value from clock;
According to the standard crystal oscillator count value of local clock, the first crystal oscillator count value and the second crystal oscillator count value and the described time interval of local clock, the deviate of the crystal oscillator count value of local clock in the unit of account time;
The deviate that obtains when some master clocks that add up send datagram continuously obtains the Accumulated deviation value;
Calculate the mean value of the historical adjusted value of some local clocks;
This adjusted value according to described Accumulated deviation value and the described local clock of described mean value calculation.
Describedly by described adjusted value local clock adjustment is comprised:
Calculate the default voltage step long value of the crystal oscillator that is used for output local clock signal and the product of described this adjusted value, obtain voltage change;
The magnitude of voltage that the predeterminated voltage initial value addition of described voltage change and described crystal oscillator is obtained is as the adjustment magnitude of voltage of described crystal oscillator, so that the output of described crystal oscillator and described master clock clock signal synchronous.
A kind of clock synchronization apparatus based on IEEE1588 comprises:
Interactive unit is used for making from clock and system's master clock and realizes that by Ethernet interaction data message clock is synchronous;
Acquiring unit is used for obtaining described from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock after synchronously;
Computing unit, be used for will described crystal oscillator count value from clock and described local clock the crystal oscillator count value as the reference source, the adjusted value of calculating local clock;
Adjustment unit is used for by described adjusted value local clock being adjusted, so that the output of described local clock and described master clock clock signal synchronous.
Described acquiring unit comprises:
The message receiving element is used for receiving first data message and second data message that described master clock sends continuously;
The count value reading unit, be used for when receiving described first data message, read described from the first crystal oscillator count value of clock and the first crystal oscillator count value of described local clock, and when receiving described second data message, from described second data message, read described from the second crystal oscillator count value of clock and the second crystal oscillator count value of described local clock.
Described computing unit comprises:
The deviate computing unit, be used for by calculating described from the first crystal oscillator count value of clock and the time interval of the second crystal oscillator count value from the standard crystal oscillator count value of clock, the described first crystal oscillator count value and the second crystal oscillator count value from clock, and according to the standard crystal oscillator count value of local clock, the first crystal oscillator count value and the second crystal oscillator count value and the described time interval of local clock, the deviate of the crystal oscillator count value of local clock in the unit of account time;
The deviate unit that adds up is used for the deviate that adds up and obtain when some master clocks send datagram continuously, obtains the Accumulated deviation value;
Average calculation unit is for the mean value of the historical adjusted value that calculates some local clocks;
The adjustment calculation unit is used for this adjusted value according to described Accumulated deviation value and the described local clock of described mean value calculation.
Described adjustment unit comprises:
The adjustment calculation unit is used for calculating the default voltage step long value of the crystal oscillator that is used for output local clock signal and the product of described this adjusted value, obtains voltage change;
The magnitude of voltage adjustment unit, be used for magnitude of voltage that the predeterminated voltage initial value addition with described voltage change and described crystal oscillator obtains as the adjustment magnitude of voltage of described crystal oscillator, so that the output of described crystal oscillator and described master clock clock signal synchronous.
A kind of base station clock equipment comprises:
From clock module, be used for realizing that by Ethernet interaction data message clock is synchronous with the system master clock;
Soft phase-locked module, be used for described synchronous from clock and master clock after, obtain described crystal oscillator count value from clock, and the crystal oscillator count value by described base station local clock, the crystal oscillator count value of described crystal oscillator count value from clock and described local clock as the reference source, is calculated the adjusted value of local clock;
The crystal oscillator module is used for by described adjusted value local clock being adjusted, so that the output of described local clock and described master clock clock signal synchronous.
Also comprise:
The FPGA module is used for obtaining the crystal oscillator count value of described local clock, and the crystal oscillator count value of described local clock is offered described soft phase-locked module.
As can be seen from the above-described embodiment, base station side realizes that by Ethernet interaction data message clock is synchronous from clock and system's master clock in the embodiment of the present application, after synchronously, obtain from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock, will be from the crystal oscillator count value of the crystal oscillator count value of clock and described local clock as the reference source, calculate the adjusted value of local clock, by adjusted value local clock is adjusted, so that local clock output and master clock clock signal synchronous.By 1588 message protocols, do not have at local clock under the situation of reliable external timing signal input in the embodiment of the present application, by the count value of crystal oscillator count value instead of external clock signal, thereby realized the accurately synchronous of base station side local clock and master clock.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the first embodiment flow chart of the application's clock synchronizing method;
Fig. 2 is the second embodiment flow chart of the application's clock synchronizing method;
Fig. 3 is for using a kind of LET base station clock module diagram of the application's method embodiment;
Fig. 4 is the embodiment block diagram of the application's clock synchronization apparatus;
Fig. 5 is the embodiment block diagram of the application's base station clock equipment.
Embodiment
The following embodiment of the present invention provides clock synchronizing method and the device based on the IEEE1588 agreement.Make and be difficult to provide under the situation of 1PPS clock signal 1588 from clock, by 1588 protocol massages make synchronous from clock and master clock after, utilize 1588 to be reference from the crystal oscillator reading value of clock and the reading value of local OCXO (constant-temperature crystal oscillator), calculate the adjustment magnitude of voltage of OCXO, thereby clock signal and the master clock of the OCXO output of realization local clock are accurately synchronous.
In order to make those skilled in the art person understand technical scheme in the embodiment of the invention better, and the above-mentioned purpose of the embodiment of the invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing technical scheme in the embodiment of the invention is described in further detail.
Referring to Fig. 1, be the first embodiment flow chart of the application's clock synchronizing method:
Step 101: base station side realize that by Ethernet interaction data message clock is synchronous from clock and system's master clock.
Step 102: after synchronously, obtain from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock.
Concrete, receive first data message and second data message that master clock sends continuously, when receiving described first data message, read from the first crystal oscillator count value of clock and the first crystal oscillator count value of local clock, and when receiving second data message, from second data message, read from the second crystal oscillator count value of clock and the second crystal oscillator count value of local clock.
Step 103: will calculate the adjusted value of local clock from the crystal oscillator count value of the crystal oscillator count value of clock and local clock as the reference source.
Concrete, by the standard crystal oscillator count value from clock, calculate from the first crystal oscillator count value of clock and the time interval of the second crystal oscillator count value from the first crystal oscillator count value and the second crystal oscillator count value of clock, standard crystal oscillator count value according to local clock, the first crystal oscillator count value of local clock and second crystal oscillator count value and the time interval, the deviate of the crystal oscillator count value of local clock in the unit of account time, the deviate that obtains when some master clocks that add up send datagram continuously, obtain the Accumulated deviation value, calculate the mean value of the historical adjusted value of some local clocks, according to this adjusted value of Accumulated deviation value and mean value calculation local clock.
Step 104: by adjusted value local clock is adjusted, so that local clock output and master clock clock signal synchronous.
Concrete, calculate the default voltage step long value of the crystal oscillator that is used for output local clock signal and the product of this adjusted value, obtain voltage change, the magnitude of voltage that the predeterminated voltage initial value addition of voltage change and crystal oscillator is obtained is as the adjustment magnitude of voltage of crystal oscillator, so that crystal oscillator output and described master clock clock signal synchronous.
Referring to Fig. 2, be the second embodiment flow chart of the application's clock synchronizing method:
Step 201: base station side realize that by Ethernet interaction data message clock is synchronous from clock and system's master clock.
Wherein, system's master clock is when sending the Sync message from clock, stabs TM1 and time of reception stabs TS1 from the transmitting time of obtaining this Sync message of clock from this Sync message; , when sending the Delay_Req message to master clock, obtain the transmitting time of this Delay_Req message from clock and stab TS2 and time of reception stamp TM2 from clock
The timestamp that obtains when the clock utilization receives message and send message carries out following calculating:
Delay＝((TS1-TM1)+(TS2-TM2))÷2；
Offset＝TS1-TM1-Delay；
In the following formula, Delay is propagation delay time, and Offset is time error, according to this Delay and Offset realize from clock and system's master clock accurately synchronously, this synchronizing process is consistent with prior art, does not repeat them here.
Step 202: after synchronously, receive first data message and second data message that master clock sends continuously.
From clock and system's master clock synchronously after, from the polling tasks of clock by its MAC layer, receive at every turn data message that system's master clock sends the time, trigger 64 bit registers in the MAC layer and read crystal oscillator count value F from clock
1588, and trigger the crystal oscillator count value F that reads local clock by FPGA (Field-Programmable GateArray, field programmable gate array) register
Local
Step 203: read the crystal oscillator count value after receiving first data message and second data message.
When receiving described first data message, read from the first crystal oscillator count value of clock and the first crystal oscillator count value of local clock, and when receiving second data message, from second data message, read from the second crystal oscillator count value of clock and the second crystal oscillator count value of local clock.
Under the perfect condition, the 1588 standard crystal oscillator count values from clock are F
1588 (marks)(then this standard meter numerical value is 100M for the given standard frequency value of crystal oscillator, the crystal oscillator of 100M for example), the standard crystal oscillator count value of local clock is F
Local (mark)Appoint when getting the adjacent two data message that receives the continuous transmission of master clock, the crystal oscillator count value that obtains, when supposing to receive the datagram of master clock transmission for the first time, the crystal oscillator count value from clock that reads is F
1588 (1), the crystal oscillator count value of local clock is F
Local (1), when receiving for the second time the datagram of master clock transmission, the crystal oscillator count value from clock that reads is F
1588 (2), the crystal oscillator count value of local clock is F
Local (2)
Step 204: calculate from the first crystal oscillator count value of clock and the time interval of the second crystal oscillator count value.
By from the standard crystal oscillator count value of clock, calculate from the first crystal oscillator count value of clock and the time interval of the second crystal oscillator count value from the first crystal oscillator count value and the second crystal oscillator count value of clock.Concrete, can be according to following formula interval T computing time:
T=(F
1588 (2)-F
1588 (1))/F
1588 (marks)
Step 205: according to the deviate of this time interval unit of account crystal oscillator count value of local clock in the time.
According to the standard crystal oscillator count value of local clock, the first crystal oscillator count value and the second crystal oscillator count value and this time interval of local clock, the deviate of the crystal oscillator count value of local clock in the unit of account time.Concrete, can be according to following formula calculation deviation value TE:
TE＝(S1-S2)/T
In the following formula, S1 represents (being that local clock is accurately synchronous with master clock) under the perfect condition, the desirable difference of the crystal oscillator count value of adjacent twice local clock; S2 represents under the actual conditions, the difference of the crystal oscillator count value of adjacent twice local clock that reads; The deviate of the crystal oscillator count value of actual conditions and ideal situation in the TE representation unit time, wherein, S1 and S2 can calculate by following formula respectively:
S1=(F
1588 (2)-F
1588 (1)) * F
Local (mark)/ F
1588 (marks)
S2＝F
Local(2)-F
Local(1)
Step 206: the deviate that adds up and obtain according to the continuous data message that sends of some master clocks obtains the Accumulated deviation value.
Reach at local clock with from clock under the accurately synchronous situation, the value that TE should be arranged is 0, but in actual conditions, TE is not 0 usually, and therefore the cumulative errors value CTE of deviate behind k reading of the crystal oscillator count value of local clock then arranged
k, following formula calculates:
CTE
k＝TE
1+TE
2+...+TE
k
Step 207: the mean value that calculates the historical adjusted value of some local clocks.
When the mean value of the historical adjusted value that calculates local clock, at first need to begin from the historical adjusted value of certain local clock the historical adjusted value of the some local clocks of continuous drawing, and calculate the mean value of the historical adjusted value that extracts.
Concrete, can calculate this mean value correct according to following formula
Ref:
In the following formula, c
tBe the historical adjusted value of local clock, N is generally the integer value greater than 3000.
Step 208: according to this adjusted value of Accumulated deviation value and mean value calculation local clock.
Calculate this adjusted value c of local clock according to following formula
k:
c
k＝correct
ref-CTE
k÷damp
In the following formula, damp is constant value, for example, can value be 200.
Step 209: according to this adjustment calculation voltage change.
Calculate the default voltage step long value of the crystal oscillator that is used for output local clock signal and the product of this adjusted value, obtain voltage change.
Step 210: according to voltage change the voltage of crystal oscillator is adjusted, so that crystal oscillator output and master clock clock signal synchronous.
The magnitude of voltage that the predeterminated voltage initial value addition of described voltage change and described crystal oscillator is obtained is as the adjustment magnitude of voltage of crystal oscillator, so that crystal oscillator output and described master clock clock signal synchronous.
Concrete, suppose that default voltage step long value is OcxoAdjCoef, initial voltage value is InitVol, then voltage change Vol calculates according to following formula:
Vol＝InitVol+OcxoAdjCoef×c
k
Calculate the magnitude of voltage that each needs are adjusted by above formula, thereby make the clock signal clk 2 of crystal oscillator output to keep accurately synchronously with system's master clock.
Referring to Fig. 3, for using a kind of LET base station clock module diagram of the application's method embodiment:
Comprise 1588 from clock in the LET base station clock module among Fig. 3, soft phase-locked loop, FPGA and OCXC, wherein, 1588 comprise the MAC layer from clock, comprise 1588 controllers in the MAC layer.
By the mutual message data of Ethernet, 1588 controllers in the MAC layer contain the high accuracy phase locked algorithm to IEEE1588 master clock and 1588, can guarantee that 1588 is accurately synchronous from clock and master clock from clock.When 1588 reach accurately synchronously from clock and 1588 master clocks after, because the clock signal clk 1 of MAC layer can not offer local clock and use, therefore the polling tasks of MAC layer is receiving that at every turn 1588 master clocks send to 1588 in the data message of clock, and soft phase-locked loop can read the 1588 crystal oscillator count value F from clock by 64 bit registers in the MAC layer
1588, and read the crystal oscillator count value F of local clock by the FPGA register
LocalAs the reference source, the deviate that soft phase-locked loop utilizes above-mentioned reference source to calculate adjustment is adjusted OCXO, produces and the phase difference of the 1588 master clock signals reliable clock signal clk 2 in ± 1.5uS from making OCXC.The concrete process previous embodiment of adjusting deviate of calculating is described in detail, does not repeat them here.
Phase-locked loop (PLL) can utilize frequency and the phase place of the reference signal control loop internal oscillation signal of outside input and since phase-locked loop can realize output signal frequency to frequency input signal from motion tracking, so phase-locked loop is generally used for the closed loop tracking circuit.Phase-locked loop is in the process of work, and when output signal frequency equated with the frequency of input signal, output voltage and input voltage kept fixing phase difference value, and namely the phase place of output voltage and input voltage is lockable.Phase-locked loop is made up of phase discriminator (PD), loop filter (LF) and voltage controlled oscillator (VCO) three parts usually.Phase discriminator is used for differentiating the phase difference between input signal and the output signal, and output error voltage, noise in the error voltage and interference component are by the low-pass loop filter filtering, form control voltage of voltage-controlled oscillator Uc, the result that Uc acts on voltage controlled oscillator pulls to the loop input signal frequency to its output frequency of oscillation, when the two was equal, loop was locked, was called into lock.The control voltage of keeping locking is provided by phase discriminator, so leaves certain phase difference between two input signals of phase discriminator.
The embodiment of the present application is to be adjusted frequency and the phase place of the clock signal clk 2 of OCXO output, makes its and 1588 master clocks reach accurately synchronous, need to prove, this accurately can allow between the two error synchronously in certain scope.
Fig. 4 is the embodiment block diagram of the application's clock synchronization apparatus:
This clock synchronization apparatus comprises: interactive unit 410, acquiring unit 420, computing unit 430 and adjustment unit 440.
Wherein, interactive unit 410 is used for making from clock and system's master clock and realizes that by Ethernet interaction data message clock is synchronous;
Acquiring unit 420 is used for obtaining described from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock after synchronously;
Concrete, acquiring unit 420 can comprise (not shown among Fig. 4): the message receiving element is used for receiving first data message and second data message that described master clock sends continuously; The count value reading unit, be used for when receiving described first data message, read described from the first crystal oscillator count value of clock and the first crystal oscillator count value of described local clock, and when receiving described second data message, from described second data message, read described from the second crystal oscillator count value of clock and the second crystal oscillator count value of described local clock.
Concrete, computing unit 430 can comprise (not shown among Fig. 4): the deviate computing unit, be used for by calculating described from the first crystal oscillator count value of clock and the time interval of the second crystal oscillator count value from the standard crystal oscillator count value of clock, the described first crystal oscillator count value and the second crystal oscillator count value from clock, and according to the standard crystal oscillator count value of local clock, the first crystal oscillator count value and the second crystal oscillator count value and the described time interval of local clock, the deviate of the crystal oscillator count value of local clock in the unit of account time; The deviate unit that adds up is used for the deviate that adds up and obtain when some master clocks send datagram continuously, obtains the Accumulated deviation value; Average calculation unit is for the mean value of the historical adjusted value that calculates some local clocks; The adjustment calculation unit is used for this adjusted value according to described Accumulated deviation value and the described local clock of described mean value calculation.
Concrete, adjustment unit 440 can comprise (not shown among Fig. 4): the adjustment calculation unit, be used for calculating the default voltage step long value of the crystal oscillator that is used for output local clock signal and the product of described this adjusted value, and obtain voltage change; The magnitude of voltage adjustment unit, be used for magnitude of voltage that the predeterminated voltage initial value addition with described voltage change and described crystal oscillator obtains as the adjustment magnitude of voltage of described crystal oscillator, so that the output of described crystal oscillator and described master clock clock signal synchronous.
Referring to Fig. 5, be the embodiment block diagram of the application's base station clock equipment.
This base station clock equipment comprises:
From clock module 510, be used for realizing that by Ethernet interaction data message clock is synchronous with the system master clock;
Soft phase-locked module 520, be used for described synchronous from clock and master clock after, obtain described crystal oscillator count value from clock, and the crystal oscillator count value by described base station local clock, the crystal oscillator count value of described crystal oscillator count value from clock and described local clock as the reference source, is calculated the adjusted value of local clock;
Further, can also comprise: FPGA module 540 is used for obtaining the crystal oscillator count value of described local clock, and the crystal oscillator count value of described local clock is offered described soft phase-locked module.
By to the description of above execution mode as can be known, base station side realizes that by Ethernet interaction data message clock is synchronous from clock and system's master clock in the embodiment of the present application, after synchronously, obtain from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock, will be from the crystal oscillator count value of the crystal oscillator count value of clock and described local clock as the reference source, calculate the adjusted value of local clock, by adjusted value local clock is adjusted, so that local clock output and master clock clock signal synchronous.By 1588 message protocols, do not have at local clock under the situation of reliable external timing signal input in the embodiment of the present application, by the count value of crystal oscillator count value instead of external clock signal, thereby realized the accurately synchronous of base station side local clock and master clock.
The technology that those skilled in the art can be well understood in the embodiment of the invention can realize by the mode that software adds essential general hardware platform.Based on such understanding, the part that technical scheme in the embodiment of the invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product can be stored in the storage medium, as ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that a computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of some part of each embodiment of the present invention or embodiment.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and identical similar part is mutually referring to getting final product between each embodiment, and each embodiment stresses is difference with other embodiment.Especially, for system embodiment, because it is substantially similar in appearance to method embodiment, so description is fairly simple, relevant part gets final product referring to the part explanation of method embodiment.
Above-described embodiment of the present invention does not constitute the restriction to protection range of the present invention.Any modification of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the clock synchronizing method based on IEEE1588 is characterized in that, comprising:
Base station side realize that by Ethernet interaction data message clock is synchronous from clock and system's master clock;
After synchronously, obtain described from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock;
The crystal oscillator count value of described crystal oscillator count value from clock and described local clock as the reference source, is calculated the adjusted value of local clock;
By described adjusted value local clock is adjusted, so that the output of described local clock and described master clock clock signal synchronous;
Described obtaining from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock comprises:
Receive first data message and second data message that described master clock sends continuously;
When receiving described first data message, read the described first crystal oscillator count value F from clock
1588 (1)The first crystal oscillator count value F with described local clock
Local (1), and when receiving described second data message, from described second data message, read the described second crystal oscillator count value F from clock
1588 (2)The second crystal oscillator count value F with described local clock
Local (2)
The adjusted value of described calculating local clock comprises:
By the standard crystal oscillator count value F from clock
1588 (marks), the described first crystal oscillator count value F from clock
1588 (1)With the second crystal oscillator count value F
1588 (2)Calculate the time interval T of the described first crystal oscillator count value and the second crystal oscillator count value from clock; Wherein, T=(F
1588 (2)-F
1588 (1))/F
1588 (marks)
Standard crystal oscillator count value F according to local clock
Local (mark), local clock the first crystal oscillator count value F
Local (1)With the second crystal oscillator count value F
1588 (2)And described time interval T, the deviate TE of the crystal oscillator count value of local clock in the unit of account time; Wherein, TE=(S1-S2)/T, S1=(F
1588 (2)-F
1588 (1)) * F
Local (mark)/ F
1588 (marks), S2=F
Local (2)-F
Local (1)
The deviate that obtains when k the master clock that add up sends datagram continuously obtains Accumulated deviation value CTE
k
Calculate the mean value correctref of the historical adjusted value of some local clocks, wherein,
c
tBe the historical adjusted value of local clock, N is the integer value greater than 3000;
According to this adjusted value ck of described Accumulated deviation value and the described local clock of described mean value calculation, wherein, ck=correctref-CTEk ÷ damp, damp are constant value.
2. method according to claim 1 is characterized in that, describedly by described adjusted value local clock adjustment is comprised:
Calculate the default voltage step long value of the crystal oscillator that is used for output local clock signal and the product of described this adjusted value, obtain voltage change;
The magnitude of voltage that the predeterminated voltage initial value addition of described voltage change and described crystal oscillator is obtained is as the adjustment magnitude of voltage of described crystal oscillator, so that the output of described crystal oscillator and described master clock clock signal synchronous.
3. the clock synchronization apparatus based on IEEE1588 is characterized in that, comprising:
Interactive unit is used for making from clock and system's master clock and realizes that by Ethernet interaction data message clock is synchronous;
Acquiring unit is used for obtaining described from the crystal oscillator count value of clock and the crystal oscillator count value of base station local clock after synchronously;
Computing unit, be used for will described crystal oscillator count value from clock and described local clock the crystal oscillator count value as the reference source, the adjusted value of calculating local clock;
Adjustment unit is used for by described adjusted value local clock being adjusted, so that the output of described local clock and described master clock clock signal synchronous;
Described acquiring unit comprises:
The message receiving element is used for receiving first data message and second data message that described master clock sends continuously;
The count value reading unit is used for reading the described first crystal oscillator count value F from clock when receiving described first data message
1588 (1)The first crystal oscillator count value F with described local clock
Local (1), and when receiving described second data message, from described second data message, read the described second crystal oscillator count value F from clock
1588 (2)The second crystal oscillator count value F with described local clock
Local (2)
Described computing unit comprises:
The deviate computing unit is used for by the standard crystal oscillator count value F from clock
1588 (marks), the described first crystal oscillator count value F from clock
1588 (1)With the second crystal oscillator count value F
1588 (2)Calculate the time interval T of the described first crystal oscillator count value and the second crystal oscillator count value from clock, and according to the standard crystal oscillator count value F of local clock
Local (mark), local clock the first crystal oscillator count value F
Local (1)With the second crystal oscillator count value F
1588 (2And described time interval T, the deviate TE of the crystal oscillator count value of local clock in the unit of account time; Wherein, T=(F
1588 (2)-F
1588 (1))/F
1588 (marks)TE=(S1-S2)/T, S1=(F
1588 (2)-F
1588 (1)) * F
Local (mark)/ F
1588 (marks), S2=F
Local (2)-F
Local (1)
The deviate unit that adds up, the deviate of acquisition obtained Accumulated deviation value CTE when k the master clock that be used for adding up sent datagram continuously
k
Average calculation unit, for the mean value correctref of the historical adjusted value that calculates some local clocks, wherein,
c
tBe the historical adjusted value of local clock, N is the integer value greater than 3000;
The adjustment calculation unit is used for this adjusted value ck according to described Accumulated deviation value and the described local clock of described mean value calculation, and wherein, ck=correctref-CTEk ÷ damp, damp are constant value.
4. device according to claim 3 is characterized in that, described adjustment unit comprises:
The adjustment calculation unit is used for calculating the default voltage step long value of the crystal oscillator that is used for output local clock signal and the product of described this adjusted value, obtains voltage change;
The magnitude of voltage adjustment unit, be used for magnitude of voltage that the predeterminated voltage initial value addition with described voltage change and described crystal oscillator obtains as the adjustment magnitude of voltage of described crystal oscillator, so that the output of described crystal oscillator and described master clock clock signal synchronous.
5. a base station clock equipment is characterized in that, comprising:
From clock module, be used for realizing that by Ethernet interaction data message clock is synchronous with the system master clock;
Soft phase-locked module, be used for described synchronous from clock and master clock after, obtain described crystal oscillator count value from clock, and the crystal oscillator count value of the local clock by described base station, the crystal oscillator count value of described crystal oscillator count value from clock and described local clock as the reference source, is calculated the adjusted value of local clock;
The crystal oscillator module is used for by described adjusted value local clock being adjusted, so that the output of described local clock and described master clock clock signal synchronous;
Described soft phase-locked module is used for obtaining from the crystal oscillator count value of clock comprising:
Described soft phase-locked module is used for receiving first data message and second data message that described master clock sends continuously;
When receiving described first data message, read the described first crystal oscillator count value F from clock
1588 (1)The first crystal oscillator count value F with described local clock
Local (1), and when receiving described second data message, from described second data message, read the described second crystal oscillator count value F from clock
1588 (2)The second crystal oscillator count value F with described local clock
Local (2)
The adjusted value that described soft phase-locked module is used for the calculating local clock comprises:
Described soft phase-locked module is used for by the standard crystal oscillator count value F from clock
1588 (marks), the described first crystal oscillator count value F from clock
1588 (1)With the second crystal oscillator count value F
1588 (2)Calculate the time interval T of the described first crystal oscillator count value and the second crystal oscillator count value from clock; Wherein, T=(F
1588 (2)-F
1588 (1))/F
1588 (marks)
Standard crystal oscillator count value F according to local clock
Local (mark), local clock the first crystal oscillator count value F
Local (1)With the second crystal oscillator count value F
1588 (2)And described time interval T, the deviate TE of the crystal oscillator count value of local clock in the unit of account time; Wherein, TE=(S1-S2)/T, S1=(F
1588 (2)-F
1588 (1)) * F
Local (mark)/ F
1588 (marks), S2=F
Local (2)-F
Local (1)
The deviate that obtains when k the master clock that add up sends datagram continuously obtains Accumulated deviation value CTE
k
Calculate the mean value correctref of the historical adjusted value of some local clocks, wherein,
c
tBe the historical adjusted value of local clock, N is the integer value greater than 3000;
According to this adjusted value ck of described Accumulated deviation value and the described local clock of described mean value calculation, wherein, ck=correctref-CTEk ÷ damp, damp are constant value.
6. equipment according to claim 5 is characterized in that, also comprises:
The FPGA module is used for obtaining the crystal oscillator count value of described local clock, and the crystal oscillator count value of described local clock is offered described soft phase-locked module.
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| CN102158950A (en) * | 2011-04-26 | 2011-08-17 | 上海华为技术有限公司 | Clock synchronization method, system, device and base station |
| CN103560486B (en) * | 2013-11-07 | 2016-02-24 | 贵州电力试验研究院 | Be applicable to the voltage Phase-Locked Synchronous networking method of sampling of transformer differential protection |
| CN104184535B (en) * | 2014-09-12 | 2017-04-12 | 四川九洲电器集团有限责任公司 | Clock synchronization method and clock synchronization device |
| CN106301746A (en) * | 2015-05-28 | 2017-01-04 | 深圳市中兴微电子技术有限公司 | Clock recovery method and device |
| KR102188552B1 (en) * | 2016-05-18 | 2020-12-08 | 니폰 덴신 덴와 가부시끼가이샤 | Wireless communication system, wireless terminal and time synchronization method |
| CN107623556A (en) * | 2016-07-13 | 2018-01-23 | 北京捷联微芯科技有限公司 | Clock synchronizing method and its system in communication system |
| CN108023723B (en) | 2016-11-04 | 2021-07-09 | 华为技术有限公司 | Method for frequency synchronization and slave clock |
| CN110661609B (en) * | 2018-06-28 | 2024-02-02 | 杭州海康机器人股份有限公司 | Clock synchronization method and first equipment |
| CN108535772B (en) * | 2018-07-04 | 2024-05-24 | 吉林大学 | Compensation method and device for time synchronization of underground multi-node acquisition system |
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| CN112512111A (en) * | 2019-12-23 | 2021-03-16 | 上海中兴软件有限责任公司 | Time determination method and device, and signal sending method and device |
| CN112003668B (en) * | 2020-08-28 | 2023-04-14 | 石家庄科林电气股份有限公司 | Real-time dynamic tracking time synchronization method |
| CN112350718B (en) * | 2020-09-25 | 2023-06-27 | 苏州华兴源创科技股份有限公司 | Clock source circuit, chassis and multi-chassis cascading system |
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