KR100931387B1 - Clock Synchronization Device and Method - Google Patents

Abstract

The present invention relates to a method of device milling for synchronizing clocks of a networked master and a slave. The clock synchronizing apparatus variably selects a plurality of clocks having different phases to change the phase of the clock, thereby improving the frequency resolution of the clock to be synchronized, thereby increasing the synchronization accuracy. In addition, by filtering the frequency offset between the master and the slave, it is possible to stabilize the synchronized clock signal.

Master, slave, clock, synchronization

Description

Apparatus and method for clock synchronization

The present invention relates to an apparatus and a method for synchronizing a clock, and more particularly, to an apparatus and a method for synchronizing a clock supplied to a networked master and a slave.

The present invention is derived from the research conducted as part of the IT growth engine technology development project of the Ministry of Information and Communication and the Ministry of Information and Communication Research and Development. ].

Network devices, such as ethernet, do not provide clock synchronization by default, but use a lesiochronous method.

In addition, for additional function extension, a method of synchronizing clocks by exchanging a message including a time stamp between clocks of two nodes to be synchronized may be used.

In the conventional first synchronization method, a slave clock calculates a frequency deviation using a time offset obtained through a message exchange with a master clock, and adjusts the slave's time information value and a clock speed to synchronize the clock. It can be done.

The conventional first synchronization method finely corrects a value of a TOD (Time Of Day) generator, which is a kind of counter driven by a conventional oscillator, so that the TOD, which is a time value of the system, is faster or slower. However, since the first synchronization method does not adjust the frequency of the clock signal generated by the real oscillator, a limited field may occur in an application requiring a synchronized clock signal.

The conventional second synchronization scheme uses an analog phase-locked loop on a slave and uses a negative feedback scheme to cancel a calculated clock frequency error. However, the longer the message exchange period, the better the traffic efficiency. In network synchronous systems, the leakage current of the capacitor used in the analog phase locked loop may occur, and thus the message exchange period may not be sufficiently long. have.

In the case of the conventional third synchronization scheme, similar to the second synchronization scheme, a synchronization is achieved with a digital phase-locked loop in the slave. Accordingly, there is no circuit problem such as the second synchronization scheme and digital control is used, which is advantageous in that it is not sensitive to ambient noise. However, there is a limit to the frequency resolution of digitally controlled oscillators (DCOs) that generate clock signals within a digital phase locked loop. If the frequency resolution is limited, an error occurs between the target frequency value of the slave node and the frequency value of the actual digitally controlled oscillator, and the time error accumulates due to this error during the time between message exchanges. That is, the accumulated time error is determined by the product of the frequency error and the message exchange interval.

In a typical network synchronization system, the frequency of a digitally controlled oscillator is within 0.01 ppm, assuming that 100 MHz clocks are synchronized through message exchanges at 1 second intervals, and that time errors within 1 UI (Unit Interval) are allowed to accumulate. Control.

The digitally controlled oscillator presented in the previous paper uses a 16-bit control code with high frequency resolution, but the minimum frequency step is only 50ppm at 100 MHz.

In addition, by using a digital-to-analog converter (DAC) to control the voltage-controlled crystal oscillator (VCXO) can have the same effect as using a digitally controlled oscillator.

However, in consideration of the maximum / minimum frequency offset that the digitally controlled oscillator should include, the third synchronization scheme has a disadvantage of increasing the complexity of the system since a DAC of at least 15 bits should be used.

An object of the present invention is to provide a clock synchronization device and method which can improve the accuracy and stability of synchronization in synchronizing clock signals of a network-connected master and slave.

In accordance with another aspect of the present invention, a clock synchronization device includes: a clock generator configured to generate a plurality of clocks having different phases; A first clock selector configured to select and output any one of the plurality of clocks according to a target frequency offset; A first time information generator configured to generate time information by using the clock selected by the first clock selector; An offset calculator configured to obtain the target frequency offset for minimizing a time offset between the clock of the master and the slave by using the synchronization message transmitted and received between the master and the slave and the time information output from the first time information generator. ;

A filtering unit which performs filtering on the obtained target frequency offset; A second clock selector configured to select and output any one of the plurality of clocks according to the filtered target frequency offset; And a second time information generator generating time information by using the clock selected by the second clock selector.

On the other hand, the clock synchronization method according to the invention, generating a plurality of clocks having different phases; Obtaining a target frequency offset for minimizing a time offset between the clock of the master and the slave by using the synchronization message transmission / reception time information between the master and the slave; Performing filtering on the obtained target frequency offset; Calculating a clock selection period using the target frequency offset on which the filtering is performed; And selecting one of the plurality of clocks at each clock selection period, and sequentially outputting two or more clocks having different phases.

In order to achieve the above object, the present invention provides a computer-readable recording medium recording a program for executing the method on a computer.

According to the clock synchronizing apparatus and method according to the present invention, by selecting a plurality of clocks having different phases by varying the phase of the clock, it is possible to improve the synchronization accuracy by improving the frequency resolution of the clock to be synchronized. In addition, by filtering the frequency offset between the master and the slave, it is possible to stabilize the synchronized clock signal.

Hereinafter, a clock synchronization apparatus and method according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7.

1 is a block diagram illustrating an embodiment of a configuration of a clock synchronization device according to the present invention. The clock synchronization device shown in FIG. 1 includes a clock generator 120, a first clock selector 125, and first time information. Generation unit 130, the first transceiver 135, the offset calculator 140, the filter 150, the second transceiver 155, the second clock selector 165, and the second time information generation It may be configured to include the unit 160.

The clock generator 120 receives a reference clock and outputs a plurality of clocks having different phases, and the first and second clock selectors 125 and 165 select one of the plurality of clocks. Output

The first and second time information generators 130 and 160 generate time-related information at predetermined intervals based on the clocks selected by the first and second clock selectors 125 and 165, respectively.

The offset calculator 140 uses the transmission / reception time information of the synchronization message and the synchronization response message transmitted and received between the master 100 and the slave 110 connected in the network, and the master 100 and the slave 110. A target frequency offset for performing clock synchronization is calculated by minimizing a time offset between the clocks.

As shown in FIG. 1, message transmission / reception time information between the master 100 and the slave 110 may be input from the first transmission / reception unit 135.

The clock of the slave output from the second clock selector 165 has the same average frequency as the clock of the master, but there may be a short term fluctuation even in a state where synchronization is performed. This is because when the transmission / reception time between the master and the slave is quantized in 1 UI, the time offset calculated by Equation 1 is quantized in units of 0.5 UI. Accordingly, the shaking of the clock of the slave output from the clock selecting unit 110 may not be reduced to within 1 UI, and may have shaking of several UIs.

In the case of the clock synchronizing apparatus and method according to the present invention, in order to reduce the unstable time information output from the second time information generator 120 according to the shaking of the clock, the calculated target frequency offset is applied to the calculated target frequency offset. It is desirable to perform filtering.

The filtering unit 150 performs filtering on the target frequency offset calculated by the offset calculating unit 140 and outputs the filtering to the second clock selecting unit 165.

The second clock selector 165 sequentially selects one of a plurality of clocks having different phases and sequentially outputs the filtered target frequency offset. In other words, the second clock selector 165 selects and outputs a plurality of clocks having different phases one by one using the filtered target frequency offset at regular intervals, thereby precisely adjusting the frequency offset of the clock to the calculated target frequency offset. Can be adjusted to increase the frequency resolution of the synchronized clock.

The first and second transmitter / receiver 155 receives information on a message transmitted and received between the master 100 and the slave 110, and receives time information output from the first and second time information generators 130 and 160. By using this, time information related to transmission and reception of the message may be transmitted to the master 100 or the slave 110.

As described above, since the clock output from the second clock selector 165 is phase controlled according to the filtered target frequency offset, the clock is output from the second time information generator 160 and provided to the slave 110. The visual information to be made can be very stable.

Accordingly, the clocks of the master 100 and the slave 110 can be synchronized using stable time information with little shaking.

2 is a flowchart illustrating an embodiment of a clock synchronization method according to the present invention. Referring to FIG. 2, an offset calculator 140 calculates a target frequency offset and clocks the target frequency offset according to the calculated target frequency offset. It will be described in more detail how to select.

The clock generator 120 generates N multi-phase clocks having the same phase interval using the reference clock signal (step 200).

For example, the clock generator 120 may generate the N multi-phase clocks by using a delay locked loop. The phase interval between the generated N multi-phase clocks may be 1 / N unit intervals (UI).

The offset calculator 140 uses the time information of the clock generated by the first time information generator 120 and the transmission / reception time information of the synchronization message transmitted / received between the master 100 and the slave 110. Calculate a target frequency offset to minimize a clock time offset between the slave and the slave 110 (step 210).

The first time information generator 130 is a type of counter that operates by receiving a clock selected by the first clock selector 125. The first time information generator 130 is triggered on the edge of the selected clock to generate a code that is increased by one bit each time an edge occurs in the clock, and the LSB of the output code is the clock frequency. It means the time value corresponding to the inverse. Accordingly, the first time information generation unit 130 may output time information about the time of the slave node.

The second time information generator 160 may generate time information by performing the above method using the clock selected by the second clock selector 165.

3 is a block diagram illustrating an embodiment of the configuration of the offset calculator 140. The offset calculator 140 includes a time offset calculator 141 and a frequency offset calculator 142. Can be.

Referring to FIG. 3, the time offset calculator 141 calculates a time offset between the master 100 and the slave 110.

4 illustrates an embodiment of a method of transmitting and receiving a synchronization message between a master and a slave for calculating the time offset. Referring to FIG. 4, a time offset calculation method of the time offset calculator 141 is described. An embodiment will be described.

The master transmits to the slave node a transmission time T ₁ of the synchronization message and the synchronization message obtained based on the clock of the master at predetermined preset periods.

At the time when the slave receives the synchronization message, the slave receives the transmission time T ₂ of the synchronization message acquired from the master by the second time information generator 160 based on the clock of the slave. Store with (T ₁ ).

The difference between the transmission time T ₁ of the synchronization message and the reception time T ₂ of the synchronization message may include a propagation delay and a network delay.

Accordingly, the slave transmits a delay request message to the master, and stores the transmission time T ₃ of the delay request message acquired by the second time information generator 160 based on the clock of the slave at the time when the delay request message is transmitted. .

The master detects the reception time T ₄ of the delay request message obtained based on the clock of the master at the time when the delay request message is received, and the reception time T ₄ of the delay request message together with the delay response message. Send to the slave.

By the above method, the slave may obtain information about the transmission / reception time (T ₁ , T ₂ ) of the synchronization message and the transmission / reception time (T ₃ , T ₄ ) of the delay request message.

The time offset calculator 141 may calculate the time offset O and the delay D between the master 100 and the slave 110 by calculating as in Equation 1 below.

The frequency offset calculator 142 may calculate a target frequency offset between the master and the slave using the time offset calculated by the time offset calculator 141.

5 and 6 illustrate an embodiment of a method of calculating a target frequency offset. An embodiment of the target frequency offset calculation method of the frequency offset calculator 142 will be described with reference to FIGS. 5 and 6. Will be described.

In Figure 5, the horizontal axis represents the time of the master, which is the reference time of the synchronization system, and the vertical axis represents the time of each of the master and the slave. T denotes the message exchange period between the master and the slave, t _n denotes the time of the slave at the nth message exchange time, and Δn denotes the frequency offset between the clock of the master and the slave immediately after the nth message exchange.

FIG. 6 subtracts the time value of the master clock from the time value of the slave clock shown in FIG. 5 and shows a relative error of the slave clock with respect to the master clock. In FIG. 6, O _n means a time offset calculated by Equation 1 at an nth message exchange time point.

The frequency offset calculator 142 may calculate the frequency offset between the clock of the master 100 and the slave 110 by using the time offsets calculated by the time offset calculator 141 as shown in Equation 2 below. .

Further, using Equation 2, Equation 3 below can be obtained.

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The target frequency offset is a frequency offset between the clock of the master and the slave immediately after the nth message exchange to minimize the time offset (O _{n + 1} ) between the clock of the master and the slave at the time of _{n +} 1th message exchange. Therefore, the target frequency offset Δ _n may be a frequency offset value when O _{n + 1} is 0 in Equation 3 above.

Therefore, the target frequency offset Δ _n may be calculated by calculating the following Equation 4.

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That is, the frequency offset calculator 142 calculates the time offset O _n-1 between the master and the slave calculated by the time offset calculator 141 at the n-1 th message exchange time, and at the n th message exchange time. The target frequency offset is calculated as shown in Equation 4 using the time offset (O _n ), the frequency offset (Δ _n-1 ) between the master and the slave immediately after the n-1th message exchange, and the message transmission / reception period (T). (Δ _n ) can be calculated.

Next, the filtering unit 150 performs filtering on the calculated target frequency offset Δ _n (step 220).

For example, may be a filter unit 150 is a low pass filter (Low Pass Filter) for Is that a high-frequency component at the target frequency offset (Δ _n), and leave only the low-frequency component.

As described above, by filtering and using the target frequency offset Δn, time information generated by the second time information generator 160 based on a clock controlled in phase according to the filtered target frequency offset Δn is obtained. It can have a stable value without shaking.

Accordingly, the time information provided for clock synchronization may be stabilized, thereby enabling more stable and precise clock synchronization.

The second clock selector 165 selects and outputs one of the multi-phase clocks having different phases according to the filtered target frequency offset Δn output from the filter 150. ) Is calculated (step 230).

The second clock selector 165 generates a phase control code according to the calculated clock selection period K, and selects and outputs a clock corresponding to the phase control code among the generated multi-phase clocks (step 240). ).

The second clock selector 165 increases the phase control code by one step for each of the calculated periods K, thereby periodically shifting the phase of the slave clock to generate the target frequency offset Δn. Can be.

FIG. 7 illustrates an embodiment of a clock selection method of the first and second clock selectors 125 and 165. The target frequency offset is determined by the first and second clock selectors 125 and 165 with reference to FIG. 7. An embodiment of a method of sequentially selecting and outputting multi-phase clocks will be described.

Referring to FIG. 7, when M _n phase shifts are performed during one message exchange interval, that is, from nT to (n + 1) T, it may be defined as Equation 5 following the effective frequency Δn. .

In Equation 5, Δ _fr means the free operating frequency offset of the slave clock, it can be calculated as shown in Equation 6 using the result value in the previous message interval. In addition, the f ₀ means the reference frequency of the clock.

In addition, Equation 5 can be summarized as Equation 7 below with respect to M _n .

Assuming that the phase shifts a total of M _n times once every clock selection period K during the period from nT to (n + 1) T, the clock selection period K is calculated as shown in Equation 8 below. Can be.

When the clock selection period K calculated by Equation 8 is not an integer, the clock selection period K may take an integer closest to the value calculated by Equation 8.

As illustrated in FIG. 7, the first and second clock selectors 125 and 165 shift the phases of the slave clock for each clock selection period K calculated by the above method, thereby providing the first and second clocks. The frequency offset of the clock output from the selectors 125 and 165 may have the target frequency offset Δn or the filtered target frequency offset value.

On the other hand, the present invention can also be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1 is a block diagram showing an embodiment of a configuration of a clock synchronization device according to the present invention.

2 is a flowchart illustrating an embodiment of a clock synchronization method according to the present invention.

3 is a block diagram illustrating an embodiment of a configuration of an offset configuration unit of FIG. 1.

4 is a diagram illustrating an embodiment of a method of transmitting and receiving a synchronization message between a master and a slave.

5 to 7 are diagrams for describing an exemplary embodiment of a target frequency offset calculation method.

Claims (10)

In the device for synchronizing the clock of the networked master (master) and slave (slave), A clock generator which generates a plurality of clocks having different phases; A first clock selector configured to select and output any one of the plurality of clocks according to a target frequency offset; A first time information generator configured to generate time information by using the clock selected by the first clock selector; An offset calculator configured to obtain the target frequency offset for minimizing a time offset between the clock of the master and the slave by using the synchronization message transmitted and received between the master and the slave and the time information output from the first time information generator. ; A filtering unit which performs filtering on the obtained target frequency offset; A second clock selector configured to select and output any one of the plurality of clocks according to the filtered target frequency offset; And And a second time information generator configured to generate time information using the clock selected by the second clock selector. The method of claim 1, wherein the filtering unit A clock synchronizer, characterized in that a low pass filter. The method of claim 1, The first and second clock selectors may calculate a clock selection period using the target frequency offset or the filtered target frequency offset, and output one of the plurality of clocks for each of the calculated clock selection periods. Clock Synchronizer. The method of claim 3,

And the clock selection period (K) is calculated using the following equation. In the equation, where N is the number of a plurality of clocks having the different phase, the Δ _n is the target frequency offset, the Δ _fr is a free-running frequency offset of the slave clock. The method of claim 1, wherein the offset calculator A time offset calculator for calculating a time offset between the master and the slave using the synchronization message and time information; And And a frequency offset calculator configured to calculate the target frequency offset using the calculated time offset. The method of claim 5, wherein the time offset calculator A time T1 at which the master transmits a first synchronization message, a time T2 at which the slave receives the first synchronization message, a time T3 at which the slave transmits a second synchronization message, and the master And calculating a time offset between the master and the slave using a time (T4) of receiving a second synchronization message. The method of claim 6, The time offset (O) between the master and the slave is calculated using the following equation.

The method of claim 5, wherein the frequency offset calculator And a target frequency offset Δ _n using the following equation.

In the above equation, Δ _n is the target frequency offset at the time of transmission and reception of the n-th sync message, Δ _n-1 is the frequency offset at the time of transmission and reception of the n-1th sync message, and O _n is the n-th sync. The time offset value output from the time offset calculator at the time of transmission and reception of the message, O _n-1 is the time offset value output from the time offset calculator at the time of transmission and reception of the n-1th sync message, and T is It is a transmission / reception period of the synchronization message. In the method of synchronizing the clock of the networked master and slave (slave), Generating a plurality of clocks having different phases; Obtaining a target frequency offset for minimizing a time offset between the clock of the master and the slave by using the synchronization message transmission / reception time information between the master and the slave; Performing filtering on the obtained target frequency offset; Calculating a clock selection period using the target frequency offset on which the filtering is performed; And Selecting one of the plurality of clocks at each clock selection period, and sequentially outputting two or more clocks having different phases. The method of claim 9, The performing of the filtering step includes performing low pass filtering on the obtained target frequency offset.

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