CN110609462B - High-stability clock synthesis device and method based on atomic clock group - Google Patents
High-stability clock synthesis device and method based on atomic clock group Download PDFInfo
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- CN110609462B CN110609462B CN201910889610.4A CN201910889610A CN110609462B CN 110609462 B CN110609462 B CN 110609462B CN 201910889610 A CN201910889610 A CN 201910889610A CN 110609462 B CN110609462 B CN 110609462B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/02—Details of the space or ground control segments
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
- G04F5/14—Apparatus for producing preselected time intervals for use as timing standards using atomic clocks
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
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Abstract
A high-stability clock synthesis device and method based on atomic clock groups comprises the following steps: the high-stability crystal oscillator, the FPGA module, the analog-to-digital conversion chip ADC, the digital-to-analog conversion chip DAC, the voltage-controlled crystal oscillator and the adder. The plurality of satellite-borne atomic clocks are sequentially connected with the FPGA module, the digital-to-analog conversion chip DAC, the summator and the voltage-controlled crystal oscillator through the corresponding analog-to-digital conversion chips ADC; the voltage-controlled crystal oscillator outputs phase and frequency outwards as a clock signal processed by a next stage of navigation task and outputs the phase and frequency to any analog-to-digital conversion chip ADC; the high-stability crystal oscillator is used for providing sampling frequency for the analog-to-digital conversion chip ADC and the FPGA module, and the sampling clocks of the analog-to-digital conversion chips ADC are in the same frequency and phase. The invention not only solves the problem of satellite clock signal discontinuity caused by switching between different atomic clocks; and a digital general design method based on high-stability clock synthesis in a large dynamic range is provided.
Description
Technical Field
The invention relates to a high-stability clock synthesis device and method based on an atomic clock group, and belongs to the technical field of navigation satellite clock generation.
Background
In the traditional atomic clock group management control, one or more algorithms are used to analyze clock difference data generated by an atomic clock group, calculate the adjustment amount of system parameters of the atomic clock group, and adjust the system parameters through a phase microstepping meter, so that the atomic time scales generated by the atomic clock group have higher accuracy and stability, as shown in fig. 2.
The generation of the satellite clock 10.23MHz signal is used as an important component of the satellite navigation system payload, is the core for maintaining high-precision time frequency, is the satellite time reference for generating navigation signals and distance measurement, and the performance of the satellite clock 10.23MHz signal influences the precision of navigation, positioning and time service.
Currently, Galileo navigation satellites employ a Clock Monitoring and Control Unit (CMCU) as a device for 10.23MHz satellite clock generation, with on-board rubidium atomic clocks and on-board hydrogen atomic clocks as references. The method utilizes a 230KHz signal generated by a DDS and a 230KHz signal obtained by mixing an atomic clock and a voltage controlled crystal oscillator to perform phase discrimination, and controls the 10.23MHz voltage controlled crystal oscillator through a loop filter, thereby realizing the locking of the atomic clock signal. The CMCU comprises four satellite-borne atomic clocks, a redundancy backup configuration mode is adopted, the atomic clock group outputs 10MHz reference frequency to the CMCU through a switch matrix, and the internal part of the CMCU comprises a main frequency signal generation link and a standby frequency signal generation link.
GPS satellite time generation and maintenance technology: the Time reference on the GPS satellite is a Time Keeping System (TKS), and the basic working principle of the TKS is to connect two frequency sources by using a data loop, wherein one frequency source is used as a 10.23MHz System output frequency source, and the other frequency source is used as a 13.4MHz System reference frequency source, and ensure that the output frequency source is locked on the reference frequency source. The TKS of GPS BLOCK IIR uses three satellite-borne rubidium atomic clocks, wherein one is in a working state, the other is in a hot backup state, and the other is in a cold backup state. The three clocks are simultaneously connected to a controllable matrix switch, and the controllable matrix switch selects 1 path as a reference frequency signal of the TKS according to the health condition of each clock.
GONASS satellite time generation and maintenance technology: the main function of the satellite-borne time frequency reference (STFT) in the GLONASS system is to generate a high-precision time frequency signal required by the system by taking a satellite-borne atomic clock as a reference, and ensure the stability and reliability of the time frequency signal. The STFS of the GLONASS satellite adopts a phase-locked loop to connect a system 5MHz reference frequency source and a system 5MHz output frequency source, so that a system output frequency signal is locked on the reference frequency source. The STFS adopts mutual redundancy backup of three satellite-borne cesium atomic clocks, and two paths of outputs are selected through a switch matrix to serve as reference frequency signals of a main time-frequency link and a standby time-frequency link. When the main link fails, the standby signal is switched to be output, so that the reliability of the satellite-borne time frequency reference is ensured.
It can be seen that, in the conventional satellite clock generation method based on the main/standby circuit redundancy backup, the mutual switching between different atomic clocks causes discontinuous phenomena such as frequency hopping, phase hopping and the like in the output signal of the satellite clock, and the high-precision continuity of the 10.23MHz signal output cannot be ensured; meanwhile, in the case of a failure of the main clock, the continuity of the output signal of the satellite clock faces a great challenge.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the device and the method for synthesizing the high-stability clock based on the atomic clock set overcome the defects of the prior art, and not only solve the problem of discontinuous satellite clock signals caused by switching between different atomic clocks; and a digital general design method is provided, the input of analog signals with a large dynamic range can be met by utilizing a digital processing method, and the synthesis of a clock with a large dynamic range and high stability is realized through software configuration.
The technical scheme of the invention is as follows:
a highly stable clock synthesis apparatus based on atomic clock group, comprising: the system comprises a high-stability crystal oscillator, an FPGA module, an analog-to-digital conversion chip ADC, a digital-to-analog conversion chip DAC, a voltage-controlled crystal oscillator and an adder;
the input end of the FPGA module is connected with n analog-to-digital conversion chips ADC, and the external n satellite-borne atomic clocks are respectively connected with the FPGA module through the corresponding analog-to-digital conversion chips ADC; n is a positive integer; the external satellite-borne atomic clock transmits a clock signal of the satellite-borne atomic clock to the corresponding analog-to-digital conversion chip ADC;
the FPGA module, the digital-to-analog conversion chip DAC, the adder and the voltage-controlled crystal oscillator are sequentially connected;
the voltage-controlled crystal oscillator is used for determining a target phase and a target frequency, the target phase and the target frequency are used as the phase and the frequency of a clock signal processed by a next-stage navigation task, meanwhile, the target phase and the target frequency are used as the phase and the frequency of the clock signal of the voltage-controlled crystal oscillator, and the clock signal of the voltage-controlled crystal oscillator is output to any analog-to-digital conversion chip ADC;
the high-stability crystal oscillator is used as a clock source to generate a reference clock signal, the reference clock signal is respectively output to the n analog-to-digital conversion chips ADC, and meanwhile, the reference clock signal is output to the FPGA module;
and the ADC determines a sampling clock according to the reference clock signal output by the high-stability crystal oscillator, the frequencies of the sampling clocks of the n ADC chips are the same, and the phases of the sampling clocks of the n ADC chips are the same.
A high-stability clock synthesis method based on an atomic clock group comprises the following steps:
1) sampling clock signals output by a plurality of external atomic clocks and clock signals output by a voltage-controlled crystal oscillator according to the same sampling frequency to obtain first clock signal sampling data X1 corresponding to each satellite-borne atomic clock and second clock signal sampling data X2 corresponding to the voltage-controlled crystal oscillator;
2) filtering the first clock signal sampling data X1 obtained in the step 1) to obtain a third single-carrier low-frequency signal X3 corresponding to each atomic clock; meanwhile, filtering the second clock signal sampling data X2 to obtain a fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator;
3) determining the phase difference between the atomic clock and the voltage-controlled crystal oscillator as a first phase difference X8 according to the third single-carrier low-frequency signal X3 corresponding to each atomic clock and the fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator in the step 2); determining the phase difference between every two atomic clocks as a second phase difference X9 according to the first phase difference X8;
4) adjusting the phase and frequency of the backup atomic clock according to the second phase difference X9 determined in the step 3) to synchronize the backup atomic clock with the main atomic clock; determining an abnormal detection value according to the second phase difference X9 determined in the step 3), and transmitting the abnormal detection value to an external telemetering and remote control system; determining the paper surface according to the second phase difference X9 and the first phase difference X8 determined in the step 3);
5) carrying out proportional integral differentiation on the paper surface determined in the step 4) to obtain a time control quantity;
6) the time control quantity obtained in the step 5) is transmitted in two paths, and the two paths of time control quantity are respectively subjected to digital-to-analog conversion to obtain analog signals corresponding to the two paths of time control quantity;
7) combining the two paths of analog signals corresponding to the time control quantity in the step 6) to obtain voltage-controlled voltage;
8) according to the voltage-controlled voltage in the step 7), determining a target phase and a target frequency as the phase and the frequency of a clock signal processed by a next-stage navigation task, and simultaneously taking the target phase and the target frequency as the phase and the frequency of the clock signal output by the voltage-controlled crystal oscillator in the step 1).
Compared with the prior art, the invention has the beneficial effects that:
1) the invention uses time scale algorithm to build satellite-borne time scale, to realize the management of satellite-borne atomic clock group, which simplifies the signal distributor of the atomic clock or the selection unit of the atomic clock input signal in the traditional satellite time and frequency generation system, and avoids the problems of frequency hopping, phase jump and discontinuous output signal caused by the mutual switch between the satellite time and the atomic clock in the traditional satellite time and frequency generation system. The method can establish a more stable and reliable time reference, and can improve the frequency stability of the time reference signal to a certain extent.
2) The invention samples the input signal by using the AD converter, and can meet the requirement of large dynamic range analog signal input. The clock signal with a large dynamic range can be flexibly output through software configuration and selection of the OCXO frequency point, so that the design flow is simplified, and the design efficiency is improved.
Drawings
FIG. 1 is a device authentication system connection diagram;
FIG. 2 is a diagram of a conventional atomic clock group management;
FIG. 3 is a block diagram of FPGA module digital mixing;
FIG. 4 is a block diagram of the apparatus of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
The invention relates to a high-stability clock synthesis device based on atomic clock set, as shown in fig. 4, comprising: the system comprises a high-stability crystal oscillator, an FPGA module, an analog-to-digital conversion chip ADC, a digital-to-analog conversion chip DAC, a voltage-controlled crystal oscillator and an adder;
the input end of the FPGA module is connected with n analog-to-digital conversion chips ADC, and the external n satellite-borne atomic clocks are respectively connected with the FPGA module through the corresponding analog-to-digital conversion chips ADC; the input end of the analog-to-digital conversion chip ADC is connected with each corresponding external satellite-borne atomic clock, and the output end of the analog-to-digital conversion chip ADC is connected with the FPGA module; n is a positive integer; the external satellite-borne atomic clock transmits a clock signal of the satellite-borne atomic clock to the corresponding analog-to-digital conversion chip ADC;
the FPGA module, the digital-to-analog conversion chip DAC, the adder and the voltage-controlled crystal oscillator are sequentially connected;
the voltage-controlled crystal oscillator is used for determining a target phase and a target frequency, the target phase and the target frequency are used as the phase and the frequency of a clock signal processed by a next-stage navigation task, meanwhile, the target phase and the target frequency are used as the phase and the frequency of the clock signal of the voltage-controlled crystal oscillator, and the clock signal of the voltage-controlled crystal oscillator is output to any analog-to-digital conversion chip ADC;
the high-stability crystal oscillator is used as a clock source to generate a reference clock signal, the reference clock signal is respectively output to the n analog-to-digital conversion chips ADC, and meanwhile, the reference clock signal is output to the FPGA module;
and the ADC determines a sampling clock according to the reference clock signal output by the high-stability crystal oscillator, the frequencies of the sampling clocks of the n ADC chips are the same, and the phases of the sampling clocks of the n ADC chips are the same.
In the external n atomic clocks, only one atomic clock in a working state is used as a main atomic clock, and the rest atomic clocks are used as backup atomic clocks; each satellite-borne atomic clock outputs a clock signal to the FPGA module through the respective analog-to-digital conversion chip ADC; the sampling clocks of the n analog-to-digital conversion chips ADC are all provided by the same high-stability crystal oscillator, and the sampling clocks of the n analog-to-digital conversion chips ADC are in the same frequency and phase.
Analog-to-digital conversion chip ADC: receiving the reference clock signal output by the high-stability crystal oscillator, taking the frequency of the reference clock signal as a sampling frequency, and receiving a clock signal corresponding to an external satellite-borne atomic clock, or receiving the clock signal corresponding to the external satellite-borne atomic clock and simultaneously receiving the clock signal of the voltage-controlled crystal oscillator; sampling and analog-to-digital converting the clock signal according to the sampling frequency to obtain sampling data corresponding to the clock signal; transmitting the sampling data corresponding to the clock signal to an FPGA module; the sampling data includes: the first clock signal sample data X1 and the second clock signal sample data X2; the first clock signal sampling data X1 corresponds to a clock signal of a satellite-borne atomic clock, and the second clock signal sampling data X2 corresponds to a clock signal of a voltage-controlled crystal oscillator; the first clock signal sample data X1 and the second clock signal sample data X2 are digital signals.
An FPGA module: receiving the reference clock signal output by the high-stability crystal oscillator, taking the reference clock signal as a working clock of the FPGA module, as shown in fig. 3, receiving sampling data corresponding to clock signals transmitted by a plurality of analog-to-digital conversion chips ADC, and performing filtering processing on the sampling data to obtain a single-carrier low-frequency signal; the single-carrier low-frequency signal comprises: a third single-carrier low-frequency signal X3 and a fourth single-carrier low-frequency signal X4; the third single-carrier low-frequency signal X3 corresponds to a satellite-borne atomic clock, and the fourth single-carrier low-frequency signal X4 corresponds to a voltage-controlled crystal oscillator; sequentially filtering the first clock signal sampling data X1 to obtain a third single-carrier low-frequency signal X3 corresponding to each atomic clock; and meanwhile, sequentially filtering the second clock signal sampling data X2 to obtain a fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator. Mixing and filtering the fourth single-carrier low-frequency signal X4 and the third single-carrier low-frequency signal X3 to obtain a fifth single-carrier low-frequency signal X5; generating a sixth single-carrier low-frequency signal X6 by using the DDS according to a reference clock signal generated by a high-stability crystal oscillator; mixing and filtering the fifth single-carrier low-frequency signal X5 and the sixth single-carrier low-frequency signal X6 to obtain a seventh single-carrier low-frequency signal X7; respectively acquiring the phase difference between each atomic clock and the voltage-controlled crystal oscillator as a first phase difference X8 according to a seventh single-carrier low-frequency signal X7; acquiring the phase difference between every two atomic clocks as a second phase difference X9 according to the first phase difference X8; a. adjusting the phase and frequency of the backup atomic clock according to the second phase difference X9 between every two atomic clocks to synchronize the backup atomic clock with the main atomic clock; b. determining an abnormal detection value according to a second phase difference X9 between every two atomic clocks, and transmitting the abnormal detection value to an external telemetering and remote control system; c. determining paper time according to the second phase difference X9 and the first phase difference X8; carrying out proportional integral differentiation on paper surface through a PID module to obtain time control quantity; the PID module transmits the time control quantity to two digital-to-analog conversion chips DAC respectively;
D/A conversion chip DAC: receiving the time control quantity transmitted by the FPGA module, performing digital-to-analog conversion on the time control quantity to obtain an analog signal corresponding to the time control quantity, and transmitting the analog signal to an adder;
an adder: the input end is connected with two digital-to-analog conversion chips DAC, and receives analog signals corresponding to time control quantity transmitted by the two digital-to-analog conversion chips DAC; combining the received time control quantities transmitted by the two DAC chips to obtain voltage-controlled voltage and transmitting the voltage-controlled voltage to a voltage-controlled crystal oscillator;
voltage controlled crystal oscillator: and receiving the voltage-controlled voltage transmitted by the adder, and determining a target phase and a target frequency according to the voltage-controlled voltage.
The FPGA module comprises a digital FIR filter, and the FPGA module performs filtering processing, specifically: filtering out each harmonic and spurious signals in the plurality of first clock signal sampling data X1 by using a digital FIR filter to obtain a third single-carrier low-frequency signal X3 corresponding to each atomic clock; meanwhile, a digital FIR filter is used for filtering out various harmonics and spurious signals in the second clock signal sampling data X2, and a fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator is obtained.
The FPGA module determines to calculate the paper surface according to the first phase difference X8 and the second phase difference X9 between every two atomic clocks, and specifically comprises the following steps:
1) determining the weight W of each atomic clock according to the second phase difference X9 between every two atomic clocksi；
2) Determining from the first phase difference X8 and step 1)Weight W of each atomic clockiAnd determining the paper surface.
The FPGA module determines the weight W of the ith atomic clockiThe method specifically comprises the following steps:
wherein i represents the ith atomic clock, n represents the total number of atomic clocks,
representing the frequency stability of the ith atomic clock; i is an e [1, n ]](ii) a The frequency stability is determined according to a second phase difference X9 between every two atomic clocks.
The FPGA module comprises: the digital FIR filter, the first type phase discrimination module, the second type phase discrimination module, the time scale module and the PID module;
the digital FIR filter is used for filtering;
the first-class phase meter is used for determining the phase difference of a seventh single-carrier low-frequency signal X7 corresponding to each atomic clock and the voltage-controlled crystal oscillator;
the second type of phase meter is used for determining the phase difference between every two atomic clocks;
the time scale module is used for determining the paper surface according to the weight of each atomic clock and the first phase difference X8 corresponding to each atomic clock and transmitting the paper surface to the PID module;
and the PID module is used for receiving the paper surface transmitted by the time scale module, carrying out proportional integral differentiation on the paper surface to obtain time control quantities, and respectively transmitting the time control quantities to two external DACs.
A high-stability clock synthesis method based on an atomic clock group comprises the following steps:
1) sampling clock signals output by a plurality of external atomic clocks and clock signals output by a voltage-controlled crystal oscillator according to the same sampling frequency to obtain first clock signal sampling data X1 corresponding to each satellite-borne atomic clock and second clock signal sampling data X2 corresponding to the voltage-controlled crystal oscillator;
2) filtering the first clock signal sampling data X1 obtained in the step 1) to obtain a third single-carrier low-frequency signal X3 corresponding to each atomic clock; meanwhile, filtering the second clock signal sampling data X2 to obtain a fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator;
3) determining the phase difference between the atomic clock and the voltage-controlled crystal oscillator as a first phase difference X8 according to the third single-carrier low-frequency signal X3 corresponding to each atomic clock and the fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator in the step 2); determining the phase difference between every two atomic clocks as a second phase difference X9 according to the first phase difference X8;
4) adjusting the phase and frequency of the backup atomic clock according to the second phase difference X9 determined in the step 3) to synchronize the backup atomic clock with the main atomic clock; determining an abnormal detection value according to the second phase difference X9 determined in the step 3), and transmitting the abnormal detection value to an external telemetering and remote control system; determining the paper surface according to the second phase difference X9 and the first phase difference X8 determined in the step 3);
5) carrying out proportional integral differentiation on the paper surface determined in the step 4) to obtain a time control quantity;
6) the time control quantity obtained in the step 5) is transmitted in two paths, and the two paths of time control quantity are respectively subjected to digital-to-analog conversion to obtain analog signals corresponding to the two paths of time control quantity;
7) combining the two paths of analog signals corresponding to the time control quantity in the step 6) to obtain voltage-controlled voltage;
8) according to the voltage-controlled voltage in the step 7), determining a target phase and a target frequency as the phase and the frequency of a clock signal processed by a next-stage navigation task, and simultaneously taking the target phase and the target frequency as the phase and the frequency of the clock signal output by the voltage-controlled crystal oscillator in the step 1).
The invention builds a set of digital verification platform, and the specific hardware equipment comprises: 1 clock source, 1 FPGA, a plurality of analog-to-digital conversion chips ADC, 2 digital-to-analog conversion chips DAC, 1 voltage-controlled crystal oscillator, as shown in FIG. 1.
Each atomic clock in the atomic clock group is respectively connected to an ADC sampler, 10MHz of an output signal of the atomic clock is sampled by utilizing an undersampling technology, wherein the sampling clock frequency of the ADC sampler is provided by an external high-precision clock source.
Because each harmonic signal exists after the 10MHz signal output by the atomic clock is subjected to ADC undersampling, a digital FIR filter is arranged inside the FPGA to filter each harmonic signal, so as to obtain pure low-frequency signals, which are respectively signal f1, signal f2, signal f3, and signal f4 in fig. 4.
The phase meter module comprises two parts of digital down-conversion and phase discrimination, a low-frequency signal containing the phases of the atomic clock and the voltage-controlled crystal oscillator or a low-frequency signal containing the phase between the atomic clocks is obtained through the digital down-conversion, and then the phase between the atomic clock and the voltage-controlled crystal oscillator and the phase between the atomic clocks are obtained through the phase discrimination module.
The phase difference measurement includes two aspects: phase difference measurements between atomic clocks and phase difference measurements of atomic clocks from each other. The relative change situation of each atomic clock can be grasped through phase difference measurement between the atomic clocks, namely the phase difference between f1 and f2, f2 and f3, and the phase difference between f3 and f1 are respectively measured, and the stability situation of each atomic clock is evaluated by utilizing a triangular cap algorithm, so that the proportion of each atomic clock in the clock group is determined. The relative change between each atomic clock and the integrated time reference signal can be known by measuring the phase difference between each atomic clock and the voltage controlled crystal oscillator, i.e. measuring the phase difference between f1 and f4, f2 and f4, f3 and f4 respectively. The high-precision phase difference measurement can accurately reflect the state change rule between atomic clocks, and common high-precision phase difference measurement methods comprise FFT, full-phase FFT, cross correlation and the like.
Multiple "master-slave clock sync" patterns are constructed within an atomic clock group. Two atomic clocks (f1, f2) are arbitrarily selected to form a 'master-slave clock synchronization', one atomic clock (f1) is selected as a master clock, the other atomic clock (f2) is selected as a slave clock, and the slave clock (f2) is corrected according to the measured phase difference between the master clock (f1) and the slave clock (f2) so as to keep the frequency synchronization with the master clock (f 1). Then, establishing a second 'master-slave clock synchronization', selecting the slave clock (f2) in the first 'master-slave clock' as a master clock, then selecting other atomic clocks (f3) as slave clocks, and adjusting the 'master clock' (f2) and the 'slave clock' (f3) to keep synchronization according to the phase difference between the two atomic clocks (f2 and f 3). All atomic clocks within an atomic clock group are kept synchronized with the master clock according to "master-slave clock synchronization".
And (3) evaluating the stability characteristic of each atomic clock according to the phase difference (f1-f4, f2-f4 and f3-f4) between each atomic clock and the comprehensive time reference signal and the phase difference (f1-f2, f2-f3 and f3-f1) between the atomic clocks, and generating a paper surface through a time scale algorithm to physicochemically obtain a stable and reliable time reference signal. The method uses a weighting-based time scale algorithm, and adjusts the proportion of each atomic clock in a clock group in time by evaluating the frequency stability of each atomic clock, thereby generating a highly stable and highly reliable time reference signal.
The fault detection module monitors the working states of each atomic clock and the high-stability crystal oscillator respectively, and the working states mainly comprise function interruption, phase jump, frequency jump and the like. The phase jump and the frequency jump of the satellite-borne atomic clock can consider the real-time performance and the accuracy of fault detection. At present, the main methods for detecting the frequency jump of an atomic clock include a block averaging method, a sequence averaging method, a dynamic Allen's variance method, a least square fitting method and a detection method based on a kalman filter. Because the frequency jump detection method based on the kalman filter has real-time performance and high detection capability, the frequency jump detection method based on the kalman filter with real-time performance and high detection capability is used in the scheme.
When a paper surface is established by using a weighted time scale algorithm, the paper surface is processed by PID, then the high-precision DAC is controlled, and finally the ultra-stable crystal oscillator is controlled. The invention uses clean-up digital phase-locking technique, PID is divided into coarse adjustment mode and fine adjustment mode, and uses the advantage of freely adjusting the loop bandwidth and the loop time constant of the phase-locked loop, thereby realizing the rapid locking of the loop and improving the phase noise level of the output signal.
The accuracy of digital-to-analog conversion limits the ability to deliver atomic clock signals with high accuracy. In order to ensure high-precision transmission of the atomic clock signal quality, 2 high-precision DACs are selected, and the integrity of the DAC sampling clock signal is ensured.
Aiming at the problem of the time reference requirements of different frequency points on a satellite, the generation of the time references of the different frequency points can be met by selecting high-stability crystal oscillators with different frequency points and software configuration.
The verification method comprises the following steps:
1) device wiring diagrams. The whole system device mainly comprises a plurality of atomic clocks, a power supply, a frequency meter, a time interval analyzer, a frequency spectrograph, a signal source, a computer and the like; and (3) establishing a verification platform according to the input-output connection relation among the instrument devices shown in the figure 1.
2) Phase jump and frequency jump detection and evaluation method. In order to verify the accuracy of the atomic clock phase jump and frequency jump detection module, a test platform is set up as shown in fig. 1. The phase jump existing in the atomic clock is simulated by adjusting the phase micro-jump meter, and then the real-time performance and the accuracy of the phase jump detection algorithm are evaluated. The output signal of the atomic clock 2 is set as the reference signal of the signal source, when the clock synthesis device based on the atomic clock group works normally, the frequency value of the fine tuning signal source is used for simulating the frequency jump existing in the atomic clock, and then the performance of the frequency jump detection algorithm is evaluated through the telemetering signal obtained by the computer serial port.
3) Atomic clock removal and addition evaluation methods. As shown in fig. 1, when the clock synthesis apparatus works normally, one of the atomic clocks is removed from the clock group, and the data of the frequency meter and the time interval analyzer are respectively observed to determine whether the atomic clock is removed to affect the performance of the output signal. On the contrary, when the output of the clock synthesizer is normal, an atomic clock is added to the clock synthesizer as an input, and then whether the data of the frequency meter and the time interval analyzer are normal or not is observed respectively, so that whether the output signal of the device is affected by the addition of the atomic clock is judged.
4) And measuring and evaluating the stability of the output signal. As shown in fig. 1, when there are N clocks as the input of the clock synthesis apparatus, the frequency stability of the output signal is measured for a long time by using the time interval analyzer, and then the frequency stability of the output signal of the apparatus is compared with the frequency stability of the output of a single atomic clock, thereby verifying the correctness of the time scale algorithm.
5) And (4) outputting signal continuity measurement and evaluation. As shown in fig. 1, when the clock synthesizer is operating normally, the phase jump and the frequency jump existing in the atomic clock are respectively simulated by the phase microstepper and the signal source, and the fault modes of adding and removing the atomic clock are used, the phase difference between the output signal and the reference signal is measured by the time interval analyzer, and then whether the phase jump exists is analyzed according to the phase difference, so as to evaluate the continuity of the output signal.
Those skilled in the art will appreciate that the details of the invention not described in detail in the specification are within the skill of those skilled in the art.
Claims (6)
1. A highly stable clock synthesis apparatus based on atomic clock group, comprising: the system comprises a high-stability crystal oscillator, an FPGA module, an analog-to-digital conversion chip ADC, a digital-to-analog conversion chip DAC, a voltage-controlled crystal oscillator and an adder;
the input end of the FPGA module is connected with n analog-to-digital conversion chips ADC, and the external n satellite-borne atomic clocks are respectively connected with the FPGA module through the corresponding analog-to-digital conversion chips ADC; n is a positive integer; the external satellite-borne atomic clock transmits a clock signal of the satellite-borne atomic clock to the corresponding analog-to-digital conversion chip ADC;
the FPGA module, the digital-to-analog conversion chip DAC, the adder and the voltage-controlled crystal oscillator are sequentially connected;
the voltage-controlled crystal oscillator is used for determining a target phase and a target frequency, the target phase and the target frequency are used as the phase and the frequency of a clock signal processed by a next-stage navigation task, meanwhile, the target phase and the target frequency are used as the phase and the frequency of the clock signal of the voltage-controlled crystal oscillator, and the clock signal of the voltage-controlled crystal oscillator is output to any analog-to-digital conversion chip ADC;
the high-stability crystal oscillator is used as a clock source to generate a reference clock signal, the reference clock signal is respectively output to the n analog-to-digital conversion chips ADC, and meanwhile, the reference clock signal is output to the FPGA module;
the ADC determines a sampling clock according to the reference clock signal output by the high-stability crystal oscillator, the frequencies of the sampling clocks of the n ADC are the same, and the phases of the sampling clocks of the n ADC are the same;
in the external n atomic clocks, only one atomic clock in a working state is used as a main atomic clock, and the rest atomic clocks are used as backup atomic clocks;
analog-to-digital conversion chip ADC: receiving the reference clock signal output by the high-stability crystal oscillator, taking the frequency of the reference clock signal as a sampling frequency, and receiving a clock signal corresponding to an external satellite-borne atomic clock, or receiving the clock signal corresponding to the external satellite-borne atomic clock and simultaneously receiving the clock signal of the voltage-controlled crystal oscillator; sampling and analog-to-digital converting the clock signal according to the sampling frequency to obtain sampling data corresponding to the clock signal; transmitting the sampling data corresponding to the clock signal to an FPGA module; the sampling data includes: the first clock signal sample data X1 and the second clock signal sample data X2; the first clock signal sampling data X1 corresponds to a clock signal of a satellite-borne atomic clock, and the second clock signal sampling data X2 corresponds to a clock signal of a voltage-controlled crystal oscillator;
an FPGA module: receiving the reference clock signal output by the high-stability crystal oscillator, taking the reference clock signal as a working clock, receiving sampling data corresponding to the clock signal transmitted by the plurality of analog-to-digital conversion chips ADC, and performing filtering processing on the sampling data to obtain a single-carrier low-frequency signal; the single-carrier low-frequency signal comprises: a third single-carrier low-frequency signal X3 and a fourth single-carrier low-frequency signal X4; the third single-carrier low-frequency signal X3 corresponds to a satellite-borne atomic clock, and the fourth single-carrier low-frequency signal X4 corresponds to a voltage-controlled crystal oscillator; mixing and filtering the fourth single-carrier low-frequency signal X4 and the third single-carrier low-frequency signal X3 to obtain a fifth single-carrier low-frequency signal X5; generating a sixth single-carrier low-frequency signal X6 by using the DDS according to a reference clock signal generated by a high-stability crystal oscillator; mixing and filtering the fifth single-carrier low-frequency signal X5 and the sixth single-carrier low-frequency signal X6 to obtain a seventh single-carrier low-frequency signal X7; respectively acquiring the phase difference between each atomic clock and the voltage-controlled crystal oscillator as a first phase difference X8 according to a seventh single-carrier low-frequency signal X7; acquiring the phase difference between every two atomic clocks as a second phase difference X9 according to the first phase difference X8; a. adjusting the phase and frequency of the backup atomic clock according to the second phase difference X9 between every two atomic clocks to synchronize the backup atomic clock with the main atomic clock; b. determining an abnormal detection value according to a second phase difference X9 between every two atomic clocks, and transmitting the abnormal detection value to an external telemetering and remote control system; c. determining the paper surface according to the second phase difference X9 and the first phase difference X8; carrying out proportional integral differentiation on paper surface through a PID module to obtain time control quantity; the PID module transmits the time control quantity to two digital-to-analog conversion chips DAC respectively;
D/A conversion chip DAC: receiving the time control quantity transmitted by the FPGA module, performing digital-to-analog conversion on the time control quantity to obtain an analog signal corresponding to the time control quantity, and transmitting the analog signal to an adder;
an adder: the input end is connected with two digital-to-analog conversion chips DAC, and receives analog signals corresponding to time control quantity transmitted by the two digital-to-analog conversion chips DAC; combining the received time control quantities transmitted by the two DAC chips to obtain voltage-controlled voltage and transmitting the voltage-controlled voltage to a voltage-controlled crystal oscillator;
voltage controlled crystal oscillator: and receiving the voltage-controlled voltage transmitted by the adder, and determining a target phase and a target frequency according to the voltage-controlled voltage.
2. The atomic clock group-based high-stability clock synthesis device according to claim 1, wherein the FPGA module includes a digital FIR filter, and the FPGA module performs filtering processing, specifically: filtering out each harmonic and spurious signals in the plurality of first clock signal sampling data X1 by using a digital FIR filter to obtain a third single-carrier low-frequency signal X3 corresponding to each atomic clock; meanwhile, a digital FIR filter is used for filtering out various harmonics and spurious signals in the second clock signal sampling data X2, and a fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator is obtained.
3. The atomic clock group-based highly stable clock synthesis device according to claim 1, wherein the FPGA module determines to calculate the plane according to the first phase difference X8 and the second phase difference X9 between the two atomic clocks, specifically:
1) determining the weight W of each atomic clock according to the second phase difference X9 between every two atomic clocksi；
2) Determining the weight W of each atomic clock according to the first phase difference X8 and the step 1)iAnd determining the paper surface.
4. The atomic clock group-based high-stability clock synthesis device according to claim 3, wherein the FPGA module determines the weight W of the ith atomic clockiThe method specifically comprises the following steps:
wherein i represents the ith atomic clock, n represents the total number of atomic clocks,
representing the frequency stability of the ith atomic clock; i is an e [1, n ]](ii) a The frequency stability is determined according to a second phase difference X9 between every two atomic clocks.
5. The atomic clock group-based high-stability clock synthesis device according to any one of claims 1 to 4, wherein the FPGA module comprises: the digital FIR filter, the first type phase discrimination module, the second type phase discrimination module, the time scale module and the PID module;
the digital FIR filter is used for filtering;
the first-class phase discrimination module is used for determining the phase difference between each atomic clock and a seventh single-carrier low-frequency signal X7 corresponding to the voltage-controlled crystal oscillator;
the second type of phase discrimination module is used for determining the phase difference between every two atomic clocks;
the time scale module is used for determining the paper surface according to the weight of each atomic clock and the first phase difference X8 corresponding to each atomic clock and transmitting the paper surface to the PID module;
and the PID module is used for receiving the paper surface transmitted by the time scale module, carrying out proportional integral differentiation on the paper surface to obtain time control quantities, and respectively transmitting the time control quantities to two external DACs.
6. A high-stability clock synthesis method based on an atomic clock group is characterized by comprising the following steps:
1) sampling clock signals output by a plurality of external atomic clocks and clock signals output by a voltage-controlled crystal oscillator according to the same sampling frequency to obtain first clock signal sampling data X1 corresponding to each satellite-borne atomic clock and second clock signal sampling data X2 corresponding to the voltage-controlled crystal oscillator;
2) filtering the first clock signal sampling data X1 obtained in the step 1) to obtain a third single-carrier low-frequency signal X3 corresponding to each atomic clock; meanwhile, filtering the second clock signal sampling data X2 to obtain a fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator;
3) determining the phase difference between the atomic clock and the voltage-controlled crystal oscillator as a first phase difference X8 according to the third single-carrier low-frequency signal X3 corresponding to each atomic clock and the fourth single-carrier low-frequency signal X4 corresponding to the voltage-controlled crystal oscillator in the step 2); determining the phase difference between every two atomic clocks as a second phase difference X9 according to the first phase difference X8;
4) adjusting the phase and frequency of the backup atomic clock according to the second phase difference X9 determined in the step 3) to synchronize the backup atomic clock with the main atomic clock; determining an abnormal detection value according to the second phase difference X9 determined in the step 3), and transmitting the abnormal detection value to an external telemetering and remote control system; determining the paper surface according to the second phase difference X9 and the first phase difference X8 determined in the step 3);
5) carrying out proportional integral differentiation on the paper surface determined in the step 4) to obtain a time control quantity;
6) the time control quantity obtained in the step 5) is transmitted in two paths, and the two paths of time control quantity are respectively subjected to digital-to-analog conversion to obtain analog signals corresponding to the two paths of time control quantity;
7) combining the two paths of analog signals corresponding to the time control quantity in the step 6) to obtain voltage-controlled voltage;
8) according to the voltage-controlled voltage in the step 7), determining a target phase and a target frequency as the phase and the frequency of a clock signal processed by a next-stage navigation task, and simultaneously taking the target phase and the target frequency as the phase and the frequency of the clock signal output by the voltage-controlled crystal oscillator in the step 1).
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