CN115172379A - Three-dimensional memory and preparation method thereof - Google Patents

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The method for preparing the three-dimensional memory comprises the following steps: preparing an intermediate body including a second substrate, a stacked structure, a channel structure and a gate gap structure; and processing the second substrate from the side of the second substrate far away from the laminated structure, forming an opening at the position of the second substrate corresponding to the gate gap of the gate gap structure, and forming a source contact by filling a semiconductor material in the opening or forming a semiconductor layer on the inner wall of the opening and filling an insulating material in the opening, wherein the source contact and the projection of the gate gap structure in the stacking direction of the laminated structure at least partially overlap.

Description

Three-dimensional memory and preparation method thereof

Divisional application statement

The invention is a divisional application of Chinese patent application with the application number of 202110428154.0, namely a three-dimensional memory and a preparation method thereof, which are submitted on 21/4/2021.

Technical Field

The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory (3D NAND) and a method for fabricating the same.

Background

In a conventional fabrication process of a three-dimensional memory, a stacked structure of a memory array is constructed on a substrate (e.g., a silicon wafer), and dielectric thin film layers (e.g., a silicon oxide layer, a silicon nitride layer, a polysilicon layer, and a tetraethyl orthosilicate (TEOS) layer) included in the three-dimensional memory become more and more complicated as the number of stacked layers increases. When multiple layers are stacked, stress may accumulate in the wafer and cause the above-described dielectric thin film layer to deform.

In addition, the thermal influence of the three-dimensional memory manufacturing process such as etching, filling and heat treatment may further increase the problem of deformation of the dielectric thin film layer, which may result in unstable structure of the memory device, problems such as warpage, etc., further, failure to achieve miniaturization of the peripheral circuit chip, and problems such as degradation of electrical performance. When the deformation of the dielectric thin film layer exceeds a certain limit, the wafer may be bent or the corresponding process cannot be performed in the machine. With the increase of the number of stacked layers, due to the influence of factors such as stress, the upper channel hole and the lower channel hole are difficult to align, and the overlay accuracy (OVL) of the upper channel hole and the lower channel hole may have offset, so that the functional layer at the joint of the upper channel hole and the lower channel hole is damaged when deep hole etching is performed, and the electrical property of the prepared three-dimensional memory is influenced.

Disclosure of Invention

The present application provides a three-dimensional memory and a method of fabricating the same that may solve, at least in part, the above problems or other problems occurring in the prior art.

One aspect of the present application provides a method of fabricating a three-dimensional memory, the method including: preparing an intermediate body including a second substrate, a stacked structure, a channel structure and a gate gap structure; and processing the second substrate from the side of the second substrate far away from the laminated structure, forming an opening at the position of the second substrate corresponding to the gate gap of the gate gap structure, and forming a source contact by filling a semiconductor material in the opening or forming a semiconductor layer on the inner wall of the opening and filling an insulating material in the opening, wherein the source contact at least partially overlaps with the projection of the gate gap structure in the stacking direction of the laminated structure.

In one embodiment of the present application, the method further comprises: after forming the intermediate body, providing a first substrate, and combining a first side of the first substrate with the intermediate body; and forming a peripheral circuit on a second face of the first substrate opposite to the first face.

In one embodiment of the present application, providing a first substrate, and bonding a first side of the first substrate to the intermediate body comprises: providing a silicon-on-insulator including a substrate and a monocrystalline silicon layer; and bonding a surface of the silicon-on-insulator near the substrate to the intermediate.

In one embodiment of the present application, before forming a peripheral circuit on a second face of the first substrate opposite to the first face, the method further includes: after the first surface of the first substrate is bonded to the intermediate body, the bulk of the silicon-on-insulator is removed to obtain a single-crystal silicon layer which is independent, and the peripheral circuit is formed on the surface of the single-crystal silicon layer.

In one embodiment of the present application, preparing an intermediate including the second substrate, the stack structure, the channel structure, and the gate gap structure includes: forming a stacked structure including a plurality of gate layers over a second substrate; forming a channel structure penetrating through the laminated structure; forming a gate gap structure having a spacing from the channel structure; and trimming the edge of the stacked structure to form a stepped structure connected to the channel structure through the gate layer.

In an embodiment of the present application, the second substrate includes a base far away from the stacked-layer structure, and a first doped layer, a sacrificial stacked layer, and a second doped layer sequentially formed on the base, wherein the sacrificial stacked layer includes a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed.

In one embodiment of the present application, the channel structure extends to the first doping layer, and includes a channel hole and a functional layer and a channel layer sequentially formed on an inner wall of the channel hole, characterized in that, after forming a peripheral circuit on a face of the first substrate opposite to a surface close to the base, the method further includes: processing the second substrate from the side of the second substrate far away from the laminated structure to remove the base and form an opening at the position of the first doped layer corresponding to the gate gap; removing the sacrificial stack through the opening to form a substrate cavity; and removing the functional layer exposed in the substrate cavity to expose the channel layer.

In one embodiment of the present application, after removing the functional layer exposed in the substrate cavity to expose the channel layer, the method further comprises: and forming a semiconductor layer on the surface of the doping layer far away from the laminated structure, the inner wall of the opening and the inner wall of the substrate cavity so as to be connected with the exposed channel layer, and filling an insulating material in the substrate cavity and the opening.

In one embodiment of the present application, after removing the functional layer exposed in the substrate cavity to expose the channel layer, the method further comprises: filling a conductive material in the substrate cavity to connect the exposed channel layer; and forming a semiconductor layer on the surface of the doping layer far away from the laminated structure and the inner wall of the opening, and filling an insulating material in the opening.

In one embodiment of the present application, after removing the functional layer exposed in the substrate cavity to expose the channel layer, the method further comprises: filling semiconductive material in the substrate cavity and the opening to connect the exposed channel layer; and forming a semiconductor layer on the surface of the doped layer far away from the laminated structure.

In one embodiment of the present application, filling the opening with an insulating material includes: in the step of filling the insulating material, a filling gap is formed in the opening.

In one embodiment of the present application, filling the opening with a semiconductive material includes: in the step of filling the conductive material, a filling gap is formed in the opening.

Another aspect of the present application provides a three-dimensional memory, including: the memory device comprises a second substrate, a laminated structure arranged on the second substrate, a channel structure penetrating through the laminated structure, and a gate gap structure penetrating through the laminated structure and having a distance with the channel structure, wherein the second substrate comprises a source contact, and the source contact corresponds to the gate gap and is led out from one side departing from the laminated structure; and a peripheral circuit device chip including a first substrate and a peripheral circuit, wherein the source contact is a semiconductor layer, or the source contact includes a semiconductor layer and an insulating layer wrapped by the semiconductor layer; and the source contact at least partially overlaps with a projection of the gate gap structure in a stacking direction of the stacked structure.

In one embodiment of the present application, the first substrate is a single crystal silicon layer formed by removing a bulk of silicon on insulator.

In one embodiment of the present application, the memory device includes: the stacked structure comprises a gate layer and an insulating layer which are stacked alternately; a channel structure penetrating through the stacked structure and extending into the second substrate; and the grid gap structure penetrates through the laminated structure and has a distance with the channel structure, and comprises a grid gap and a filling layer arranged in the grid gap.

In one embodiment of the present application, the second substrate includes: a substrate including a doped region; the conductive layer is formed in the doped region and extends through the side face part of the channel structure, and the source contact is arranged at the position, corresponding to the grid gap, of the doped region and is led out from one side, far away from the laminated structure, of the substrate; wherein the conductive layer comprises a semiconductor layer and an insulating layer surrounded by the semiconductor layer, and the source contact comprises a semiconductor layer and an insulating layer surrounded by the semiconductor layer.

In one embodiment of the present application, the second substrate includes: a substrate including a doped region; the conductive layer is formed in the doped region and extends through the side face part of the channel structure, and the source contact is arranged at the position, corresponding to the grid gap, of the doped region and is led out from one side, far away from the laminated structure, of the substrate; wherein the source contact comprises a semiconductor layer and an insulating layer wrapped by the semiconductor layer.

In one embodiment of the present application, the second substrate includes: a substrate including a doped region; the conductive layer is formed in the doped region and extends through the side face part of the channel structure, and the source contact is arranged at the position, corresponding to the grid gap, of the doped region and is led out from one side, far away from the laminated structure, of the substrate; wherein the source contact and the conductive layer are semiconductor layers.

In one embodiment of the present application, a fill gap is formed in the source contact.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1 is a flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the present application;

fig. 2 to 13 are process schematic diagrams of a manufacturing method according to an embodiment of the present application; and

fig. 14-17 are schematic cross-sectional views of resulting final three-dimensional memory structures formed according to a fabrication method of another embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first side discussed in this application may also be referred to as a second side, and a first window may also be referred to as a second window, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size, and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to examples or illustrations.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, specific steps included in the methods described herein need not be limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 1 is a flowchart of a method 1000 for manufacturing a three-dimensional memory according to a first embodiment of the present application. As shown in fig. 1, the present application provides a method 1000 for manufacturing a three-dimensional memory, including:

s1, preparing an intermediate body comprising a channel structure, a grid gap structure and a step structure.

And S2, providing a first substrate, and combining the first surface of the first substrate with the front surface of the intermediate body, wherein the front surface is provided with the channel structure, the grid gap structure and the step structure.

And S3, forming a peripheral circuit on a second surface, opposite to the first surface, of the first substrate.

The specific processes of the steps of the above-described manufacturing method 1000 will be described in detail below with reference to fig. 2 to 17.

Fig. 2 is a schematic cross-sectional structure of a substrate 100 provided in a manufacturing method according to an embodiment of the present application. Fig. 3 is a schematic cross-sectional view of a structure formed after forming a stack structure 200, a channel structure 300, and a stepped structure 500 on a substrate 100 according to a fabrication method of an embodiment of the present application. Fig. 4 is a schematic cross-sectional view of a structure formed after forming a gate gap 400 and a gate layer 230 in a stacked structure 200 according to a fabrication method of an embodiment of the present application.

As shown in fig. 2 to 4, the step S1 of preparing an intermediate including a channel structure, a gate gap structure, and a stepped structure may include, for example: preparing a composite substrate 100; forming a stack structure 200 including a plurality of sub-stack structures on one side of the composite substrate 100, the stack structure 200 including gate sacrificial layers 220 and insulating layers 210 alternately stacked; and forming a channel hole 300 in the stacked structure 200, the channel hole 300 penetrating the stacked structure 200 in a stacked thickness direction and extending into the substrate 100; forming a gate gap 410 in the stack structure 200 with a spacing from the channel structure 300; removing the gate sacrificial layer 220 through the gate gap 410 to form a gate layer 230; forming a gate gap structure 400 including a gate gap 410 and a filling layer 420 disposed in the gate gap 410; and trimming the edges of the stacked structure 200 to form a stair-step structure 500 connected to the channel structure 300 through the gate layer 230.

In particular, referring to fig. 2, the substrate 100 may be, for example, a composite substrate for supporting device structures thereon. The base 110, the first doped layer 130, the sacrificial stack 140, and the second doped layer 150 may be sequentially disposed by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof to form the substrate 100.

The substrate 110 may be made of any suitable semiconductor material, such as a group III-V compound, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide. In the present embodiment, the substrate 110 may be monocrystalline silicon.

In one embodiment of the present application, a partial region of the substrate 100, such as the first and second doped layers 130 and 150, may be formed by doping N-type or P-type dopants via an ion implantation and diffusion process. In some embodiments, the dopant may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the first doped layer 130 and the second doped layer 150 may be prepared by using the same dopant or different dopants, and further, the doping concentrations of the first doped layer 130 and the second doped layer 150 may be the same or different, which is not limited in this application.

The sacrificial stack 140 may be deposited on a surface of the first doped layer 130 remote from the substrate 110, and the sacrificial stack 140 may comprise a single layer, multiple layers, or a suitable composite layer. For example, the sacrificial stack 140 may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Specifically, in one embodiment of the present application, the sacrificial stack 140 includes a dielectric layer, a sacrificial layer and a dielectric layer, which are sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. The sacrificial stack 140 may comprise any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be single crystalline silicon or polycrystalline silicon, and particularly, in one embodiment of the present application, an exemplary material forming the sacrificial layer is polycrystalline silicon.

Further, a barrier layer 120 may be further disposed between the substrate 110 and the first doping layer 130. The material of which the barrier layer 120 is made may be an oxide.

Referring to fig. 3, after forming the second doped layer 150 (as shown in fig. 2), the stacked structure 200 may be formed on one side of the substrate 100 by one or more thin film deposition processes, which may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, which is not limited in this application. The stack structure 200 may include a plurality of pairs of insulating layers 210 and gate sacrificial layers 220 alternately stacked on each other. For example, the stack structure 200 may include 64 pairs, 128 pairs, or more than 128 pairs of the insulating layer 210 and the gate sacrificial layer 220. In some embodiments, the insulating layer 210 and the gate sacrificial layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the insulating layer 210 and the gate sacrificial layer 220 include silicon oxide and silicon nitride, respectively. A silicon oxide layer may be used as the isolation stack layer and a silicon nitride layer may be used as the sacrificial stack layer. The sacrificial stack may then be etched away and replaced with a conductor layer comprising a conductive material.

The method of making the single laminate structure 200 is described above. In fact, as the storage requirement of the three-dimensional memory is increased, the storage stack is gradually increased. In order to break through the limitation of the traditional process limit, a double-stack technology or a multi-stack technology can be adopted, and a stack structure is formed by sequentially stacking N (N is more than or equal to 2) sub-stack structures in the thickness direction of the stack structure, wherein each sub-stack structure can comprise a plurality of insulating layers and gate sacrificial layers which are alternately stacked. The number of layers of each sub-stack may be the same or different. However, it will be understood by those skilled in the art that the subsequent fabrication process may be performed on the basis of a multi-stack structure or a single-stack structure.

The stair-step structure 500 may be formed by performing a plurality of "trim-etch" cycles on edge portions of the stacked structure 200 such that the stacked structure 200 has one or more sloped edges and a top (away from the substrate 100) dielectric layer pair that is shorter than a bottom (closer to the substrate 100) dielectric layer pair (the insulating layer 210 and the gate sacrificial layer 220). Any suitable etching process (including any one or combination of dry and wet etching processes) may be used in the step formation process. Further, a dielectric layer 510 may also be formed to cover the step.

The trench structure 300 includes a trench hole 310 filled with a semiconductor layer and a composite dielectric layer. The channel hole 310 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole 310 may have a cylindrical or column shape penetrating the stack structure 200 and extending to the first doping layer 130 of the substrate 100.

Further, after the multi-stack technology is adopted to form the stack structure, the stack structure may include N sub-stack structures, and correspondingly, the channel hole may also include N sub-channel holes, where the N sub-stack structures correspond to the N sub-channel holes one to one, and N is greater than or equal to 2. Forming the channel hole in the stacked structure using the multi-stack technique may include: forming a first sub-laminated structure on one side of the substrate and forming a first sub-channel hole penetrating through the first sub-laminated structure and extending into the substrate; continuing to form subsequent sub-laminated structures and sub-channel holes until an Nth sub-laminated structure and an Nth sub-channel hole are formed, wherein N-1 hole-filling sacrificial layers are correspondingly filled in N-1 sub-channel holes except the Nth sub-channel hole; and removing the N-1 hole filling sacrificial layers based on the Nth sub-channel hole, so that the sub-channel holes which are adjacent up and down in the N sub-channel holes are at least partially aligned with each other, and obtaining the channel hole.

After the channel hole 310 is formed, the functional layer 320 and the channel layer 330 may be sequentially formed on the inner wall (inner sidewall and bottom near the substrate 100) of the channel hole 310 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof.

The functional layer 320 may include a blocking layer (not shown) formed on an inner wall of the trench hole 310 to block outflow of charges, a charge trap layer (not shown) on a surface of the blocking layer to store charges during operation of the three-dimensional memory, and a tunnel insulating layer (not shown) on a surface of the charge trap layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like. The charge trapping layer may comprise one or more layers, which may comprise one or more materials. Materials for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide band gap material, and the like. The tunnel insulation layer may include one or more layers, which may include one or more materials. Materials for the tunnel insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like.

In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure other than the ONO configuration. For example, the functional layer 320 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

The channel layer 330 can be used to transport desired charges (electrons or holes). In some embodiments, channel layer 330 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. According to an exemplary embodiment of the present application, the material of the channel layer 330 includes, but is not limited to, P-type doped polysilicon. Similar to the channel hole 310, the channel layer 330 also extends through the stacked-layer structure 200 and into the first doped layer 130 of the substrate 100.

The method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application further includes: a channel plug 340 is formed at the top of the channel hole 310 away from the substrate 100.

In particular, the channel hole 310 may be filled with a filling dielectric layer 350. The fill dielectric layer 350 may include an oxide dielectric layer, such as silicon oxide. Further, during the filling process, a plurality of insulation gaps may be formed in the filling dielectric layer 350 by controlling the trench filling process to relieve the structural stress. A trench plug 340 is then formed in the portion of the filling dielectric layer 350 that is located at the top of the channel hole 310. The channel plug 340 may be made of the same material as the channel layer 330, such as P-type doped polysilicon.

In some embodiments of the present application, the trench hole 310 may be etched after the step structure 500 is formed. In some other embodiments, the channel hole 310 may also be formed before the step structure 500 is formed.

Referring to fig. 4, a method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application further includes: a gate gap structure 400 is formed having a spacing with the channel structure 300. The gate gap structure 400 includes a gate gap 410 penetrating the stack structure 200 and a filling layer 420 disposed in the gate gap 410. The stack structure 200 is divided into a plurality of memory blocks by the gate gap structure 400. In some implementations, three-dimensional memory cells belonging to a memory block can be reset together in a block erase operation. Further, a pair of gate gap structures 400 may define a memory block therebetween. One or more additional gate gap structures 400 may be formed between a pair of gate gap structures 400.

The gate gap 410 may be formed by, for example, a dry etch process or a combination of dry and wet etch processes. The gate gap 410 may extend through the stack structure 200 and reach the second doped layer 150 in a direction approximately perpendicular to the substrate 100.

According to an example, the method 1000 for fabricating a three-dimensional memory of the present application further includes a step of disposing the gate layer 230 in the stacked structure 200. The step of disposing the gate layer 230 may, for example, include: removing the gate sacrificial layer 220 (as shown in fig. 3) based on the gate gap 410 to form a sacrificial gap; forming a gate layer 230 within the sacrificial gap; and a filling layer 420 is disposed in the gate gap 410.

Specifically, the gate gap 410 may be used as a path for providing an etchant and a chemical precursor, and all of the gate sacrificial layer 220 in the stacked-layer structure 200 may be removed by a process such as wet etching to form a sacrificial gap. Gate layer 230 may be formed in the sacrificial gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The gate layer 230 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

A dielectric material, such as an oxide, may be selected to fill the gate gap 410 to form a fill layer 420. Alternatively, the same material as the insulating layer 210 may be selected for filling, such as silicon oxide.

The gate layer 230 may extend laterally (perpendicular to the thickness direction of the stacked structure 200) as a word line, terminating at one or more of the stair-step structures 500 of the stacked structure 200.

Referring to fig. 5, after filling the gate line slits 410, openings for the peripheral contacts 171 and the word line contacts 172 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The openings for the peripheral contacts 171 and wordline contacts 172 are then filled with a conductive material by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material forming peripheral contacts 171 and wordline contacts 172 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some implementations, when preparing the peripheral contacts 171 and the word line contacts 172, a layer of conductive material (e.g., titanium nitride TiN) can be deposited as a contact layer before depositing another conductive material.

Further, a CVD or PVD process may be performed to deposit a dielectric material (e.g., silicon oxide or silicon nitride) on the three-dimensional memory. The opening for the via may then be formed by a dry etching process or a combination of dry and wet etching processes. Some vias are configured for peripheral contact 171 and wordline contact 172. Some other vias are configured for each bit line contact that electrically contacts the upper end of the corresponding memory cell and individually addresses the corresponding memory cell. The openings are then filled with a conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials, and a process of CVD, PVD, ALD, electroplating, electroless plating, or combinations thereof is employed to form vias 173, 174, and 175. Vias 173, 174, and 175 are electrically connected to peripheral contact 171, word line contact 172, and bit line contact, respectively. In some embodiments, a layer of conductive material (e.g., titanium nitride TiN) may be deposited first before filling the openings to form vias 173-175.

Further, a dielectric material (e.g., silicon oxide or silicon nitride) may be deposited to bury vias 173-175, forming dielectric layer 170. And in a similar process to the formation of vias 173-175, openings are made and then filled to form contacts 176, 177 and 178 that serve as interconnects to peripheral devices. The contacts 176 to 178 are electrically connected to the vias 173 to 175, respectively. The contacts 176-178 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or a combination of two or more of these materials. In some embodiments, a conductive material (e.g., titanium nitride) may be deposited first before filling the openings to form the contacts 176-178.

Referring to fig. 6, after forming the interconnection contacts 176 to 178, the method 1000 of fabricating a three-dimensional memory provided herein completes the front process of the intermediate body 2000 overall. The method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application further includes: providing a first substrate, and combining a first surface of the first substrate with the front surface of the intermediate body, wherein a channel structure, a grid gap structure and a step structure are formed; and forming a peripheral circuit on a second face of the first substrate opposite to the first face.

The three-dimensional memory may include a memory device and a peripheral circuit chip. The array structure of the three-dimensional memory is different from the structure of the peripheral circuit chip and must be manufactured separately. As the number of stacked layers increases, the dielectric thin film layers (e.g., silicon oxide layers, silicon nitride layers, polysilicon layers, and Tetraethylorthosilicate (TEOS) layers) included in the memory device become more complex. When a plurality of layers are stacked, stress may be accumulated in the wafer and cause deformation of the dielectric thin film layer, which may cause structural instability of the memory device, cause problems such as warpage, and further affect electrical properties of the peripheral circuit chip. In addition, since a heat treatment and a thermal processing process are required to form the memory structure of the three-dimensional memory, the electrical properties of the peripheral circuit are affected by the heat of the above process, and may be accordingly degraded. Further, since the peripheral circuit chip is more severely affected by the heat as it is more miniaturized, the heat influence of the above process also causes the peripheral circuit chip to be unable to be miniaturized.

After an intermediate body of a storage device (the intermediate body with a channel structure, a grid gap structure and a step structure) is formed, the back surface (the surface without the peripheral circuit) of a substrate required by the formation of the peripheral circuit is combined with the front surface (the surface with the channel structure, the grid gap structure and the step structure) of the intermediate body, and then the peripheral circuit is formed on the front surface of the substrate, so that the electrical performance of the peripheral circuit can be effectively prevented from being reduced due to the thermal influence of the front surface forming process of the storage device, the combined storage device and a peripheral circuit chip can jointly resist the stress generated by each film layer in the three-dimensional storage device, and the problems of warping and the like of a wafer can be effectively prevented.

In some implementations, the peripheral circuitry 800 may include one or more of page buffers, decoders (e.g., row and column decoders), drivers, charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) required in the circuitry. In some embodiments, the peripheral circuitry 800 may be formed by CMOS technology, but is not limited thereto.

Specifically, the first side of the substrate 700 of the peripheral circuit chip 3000 may be placed over the top surface 170 of the intermediate body 2000 on which the contacts 176-178 are disposed. Then, after an alignment step (e.g., alignment may be performed with the interconnect contacts of both wafers separately), the first side of substrate 700 is bonded to front side 170 of intermediate body 2000. Alternatively, a bonding process may be selected to bond the first side of substrate 700 to front side 170 of intermediate body 2000.

Further, in one embodiment of the present application, the material for preparing the substrate 700 may be selected from, for example, a silicon-on-insulator SOI. Silicon-on-insulator SOI comprises a base and a single crystal silicon layer, wherein the base may comprise a relatively thick bulk substrate layer (e.g., a silicon substrate layer) and a relatively thin intermediate layer of insulating silicon dioxide. The substrate is primarily used to provide mechanical support. The thickness of the single crystal silicon layer is very thin relative to the substrate, and the single crystal silicon layer is arranged above the substrate, so that an etching circuit can be formed on the single crystal silicon layer. After the first side of substrate 700 is bonded to front side 170 of intermediate body 2000, the bulk portion of the silicon-on-insulator SOI may be removed using any suitable etching process, including any one or combination of a dry etching process and a wet etching process, to obtain a fully free-standing single crystal silicon layer, and peripheral circuitry may be formed on the single crystal silicon layer.

As shown in fig. 7, in some embodiments, the step of bonding the first side of the substrate 700 to the front side 170 of the intermediate body 2000 is preceded by forming an oxide layer 600 on the front side 170 by a thin film deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. The corresponding contacts of the peripheral circuit chip 3000 may be disposed on the oxide layer 600 and the substrate 700.

The substrate 700 includes opposite first and second sides, the first side of the substrate 700 may be combined with a front side of an intermediate body (a surface on which a channel structure, a gate gap structure, and a step structure are formed), and the second side of the substrate 700 may have the peripheral circuit 800 formed thereon. The peripheral circuit chip 3000 and the bonding process (e.g., bonding process) of the two devices may be prepared by conventional processes according to actual needs, and are not described herein.

Further, contacts and via portions corresponding to the peripheral contacts, word line contacts, bit line contacts, vias, and interconnect contacts of the intermediate body 2000 described above may also be formed in the peripheral circuit chip 3000. Since the contact and via formation process in the peripheral circuit chip 3000 may adopt a preparation process of the intermediate of the memory device or an existing conventional process, details are not described herein. In some embodiments, solder or a conductive adhesive may be used to bond each interconnect contact 176-178 with a corresponding contact of the peripheral circuit chip 3000 and to electrically connect the interconnect contacts 176-178, respectively, to corresponding contacts of the peripheral circuit chip 3000, such that the intermediate body 2000 and the peripheral circuit chip 3000 are in electrical communication.

Fig. 8 is a schematic cross-sectional view of a structure formed after thinning the substrate 100 to expose the barrier layer 120 on the side of the substrate 100 (the back side of the substrate 100) where the stacked-layer structure 200 is not disposed, according to a manufacturing method of an embodiment of the present application. Fig. 9 is a schematic cross-sectional view of a structure formed after forming a substrate cavity 21 on the back side of a thinned substrate 100 according to a fabrication method of an embodiment of the present application. Fig. 10 is a schematic cross-sectional view of a structure formed after forming a substrate cavity 21 on the back side of the thinned substrate 100 according to a fabrication method of an embodiment of the present application.

As shown in fig. 8 to 10, the three-dimensional memory and the method 1000 for manufacturing the same provided by the present application further include: processing the substrate 100 from a side of the substrate 100 away from the stacked structure 200 to remove the base 110 and form an opening 20 at a position of the first doping layer 130 corresponding to the gate gap 400; removing the sacrificial stack 140 through the opening 20 to form a substrate cavity 21; and removing the functional layer 320 exposed in the substrate cavity 21 at the sidewall of the channel hole 300 to expose the channel layer 330.

Specifically, fig. 8 is a schematic structural diagram of the structure of fig. 7 that is turned over by 180 ° and then thinned. Referring to fig. 8, the base 110 of the substrate 100 (shown in fig. 2) may be removed from the side of the substrate 100 (the back side of the substrate 100) where the stacked structure 200 is not disposed by using any suitable etching process (including any one or a combination of a dry etching process and a wet etching process) to expose the barrier layer 120.

Further, as shown in fig. 9, for example, a dry etching process or a combination of dry and wet etching processes may be used, or other manufacturing processes may be performed to remove the barrier layer 120 (as shown in fig. 8) and remove the sacrificial substrate stack 140 (as shown in fig. 8) through the opening 20 to form the substrate cavity 21, where the side portion of the barrier layer of the functional layer 320 may be exposed in the substrate cavity 21. Next, a plurality of selective etching processes (e.g., a plurality of selective wet etching processes) may be performed to sequentially remove the blocking layer of the functional layer 320, the charge trap layer, and the exposed portion of the tunnel insulation layer until the bottom side portion of the channel layer 330 is exposed.

Fig. 10 is a schematic cross-sectional view of a structure formed after forming a semiconductive layer 900 on the back side of a thinned substrate 100 according to a manufacturing method of an embodiment of the present application.

Specifically, as shown in fig. 10, a semiconductor layer 900 may be formed of a semiconductor material (e.g., polysilicon) on a surface of the first doping layer 130 away from the stacked-layer structure 200, an inner wall of the opening 20 (shown in fig. 9), and an inner wall of the substrate cavity 21 (shown in fig. 9) by a deposition process such as CVD or PVD to connect the exposed channel layer 330, and an insulating material (e.g., silicon oxide) may be filled in the substrate cavity 21 and the opening 20 by a deposition process such as CVD or PVD.

In this embodiment, the insulating material is filled in the substrate cavity 21 and the opening 20 to reduce the resistance of the semiconductor layer 900, and the semiconductor material may be selected to be a relatively low-doped material.

The source contact 910 of the three-dimensional memory may be formed by forming a semiconductor layer on the inner wall of the opening 20 and filling an insulating material inside the opening 20.

The common source line is led out from the back of the channel hole, the function that the grid gap is used as a leading-out channel electrically connected with the common source line is cancelled, the effective memory cell array area can be effectively increased, the deformation of the memory region is at least partially reduced, good support is provided for the memory region, and meanwhile the alignment problem of the common source line and the grid gap layer can be avoided to a certain extent.

Fig. 11 is a schematic cross-sectional view of a structure formed after forming an opening for forming a via 191 on the back surface of the substrate according to a fabrication method of an embodiment of the present application. Fig. 12 is a schematic cross-sectional view of a structure formed after a source contact 910 is pulled out from the back side of a substrate according to a fabrication method of an embodiment of the present application. Fig. 13 is a schematic cross-sectional view of a structure formed after forming a dielectric layer 116 on the surface of a metal layer 193 according to a method of manufacturing an embodiment of the present application.

As shown in fig. 11 to 13, the opening 113 may be formed at a position of the thinned substrate 100 corresponding to the peripheral contact 171 by a dry etching process or a combination of a dry etching and a wet etching process. The opening 113 may expose the peripheral contact 171, and then be filled with a conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), CVD, PVD, ALD, electroplating, electroless plating, or combinations thereof, to form the via 191 by performing a deposition process, such as CVD or PVD, to form a dielectric layer (e.g., silicon dioxide or silicon nitride) on the sidewalls and bottom of the opening 113. Vias 191 may be used as contact structures, and vias 191 may also be referred to as through-silicon contacts (TSCs). Vias 191 may be electrically connected to peripheral contact 171 and first doped region 130 by metal layer 193. The metal layer 193 may be implemented by performing CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. The dielectric layer 116 may be used for a passivation layer and may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

Fig. 14 is a cross-sectional schematic view of a three-dimensional memory structure formed according to a fabrication method of another embodiment of the present application. Fig. 15 is a cross-sectional schematic view of a three-dimensional memory structure formed according to a fabrication method of another embodiment of the present application. Fig. 16 is a cross-sectional schematic view of a three-dimensional memory structure formed according to a fabrication method of another embodiment of the present application. Fig. 17 is a cross-sectional schematic view of a three-dimensional memory structure formed according to a fabrication method of another embodiment of the present application.

In particular, there are a number of possible processes for forming the semiconducting layer 900 and the source contact 910 in the three-dimensional memory structure as shown in fig. 13-17.

In fig. 13, a semiconductor layer 900 may be formed of a semiconductor material (e.g., polysilicon) on the surface of the first doping layer 130, the inner wall of the opening 20 (shown in fig. 9), and the inner wall of the substrate cavity 21 (shown in fig. 9) by a deposition process such as CVD or PVD to connect the exposed channel layer 330, and an insulating material (e.g., silicon oxide) may be filled in the substrate cavity 21 and the opening 20 by a deposition process such as CVD or PVD.

In this embodiment, the filling of the insulating material in the substrate cavity 21 and the opening 20 can reduce the resistance of the semiconductor layer 900, while the semiconductor material can be selected to be a relatively low doped material.

The source contact 910 of the three-dimensional memory may be formed by forming a semiconductor layer on the inner wall of the opening 20 and filling an insulating material inside the opening 20.

The steps of forming the semiconductor layer 900 and the source contact 910 in the process of fabricating the three-dimensional memory in fig. 14 are substantially identical to the fabrication method shown in fig. 13, wherein, when an insulating material (e.g., silicon oxide) is filled in the opening 20 (as shown in fig. 9) by a deposition process such as CVD or PVD, a filling gap 911 may be formed in the opening 20 to relieve stress of the relevant films.

In fig. 15, a semiconductive material may be filled in the substrate cavity 21 (shown in fig. 9) by a deposition process such as CVD or PVD from a semiconductor material (e.g., polysilicon) to connect the exposed channel layer 330, and a semiconductor layer may be formed on the surface of the first doped layer 130 and the inner walls of the opening 20 (shown in fig. 9) and filled with an insulating material in the opening 20 by a deposition process such as CVD or PVD.

The source contact 910 of the three-dimensional memory may be formed by forming a semiconductor layer on the inner wall of the opening 20 and filling an insulating material inside the opening 20.

In this embodiment, the insulating material is filled in the opening 20 to reduce the resistance of the semiconductor layer 900, and the semiconductor material can be selected to have a relatively low doping concentration.

In fig. 16, a source contact 910 of a three-dimensional memory may be formed by filling a semiconductor material (e.g., polysilicon) in the substrate cavity 21 (shown in fig. 9) and the opening 20 (shown in fig. 9) with a conductive material through a deposition process such as CVD or PVD to connect the exposed channel layer 330, and forming a semiconductor layer on the surface and inner wall of the first doping layer 130, and filling the opening 20 with the semiconductor material.

The steps of forming the semiconductor layer 900 and the source contact 910 in the process of fabricating the three-dimensional memory in fig. 17 are substantially identical to the fabrication method shown in fig. 16, wherein, when the semiconductor material is filled in the opening 20 (shown in fig. 9) by a deposition process such as CVD or PVD, a filling gap 911 may be formed in the opening 20 to relieve stress of the relevant film.

Another aspect of the present application also provides a three-dimensional memory. The three-dimensional memory can be manufactured by any one of the manufacturing methods described in the above embodiments. Referring again to fig. 17, the three-dimensional memory may include: a memory device (including the intermediate body 2000) and a peripheral circuit chip 3000. The memory device includes opposing front 170 and back surfaces, with a channel structure 300 disposed on the front surface. A peripheral circuit die 3000 is disposed over the front side 170, the peripheral circuit die including a first substrate 700, the first substrate 700 including opposing first and second sides, and a peripheral circuit 800 disposed on the second side of the first substrate 700, wherein the front side of the memory device is bonded to the first side of the first substrate 700. In one embodiment of the present application, a selective bonding process may bond the front side of the memory device to the first side of the first substrate 700.

In one embodiment of the present application, the first substrate 700 may be a single crystal silicon layer formed by removing a bulk of silicon on insulator.

In addition, in one embodiment of the present application, the front surface 170 of the memory device is further provided with a gate gap structure 400 and a stepped structure 500.

Specifically, the memory device includes: substrate 100 (second substrate), stack structure 200, channel structure 300, gate gap structure 400. The stacked structure 200 is disposed on the substrate 100, and the stacked structure 200 includes gate layers 230 and insulating layers 210 that are alternately stacked. The channel structure 300 extends through the stack 200 and to the substrate 100. The gate gap structure 400 penetrates the stack structure 200 and has a distance from the channel structure 300. The gate gap structure 400 includes a gate gap 410 and a filling layer 420 disposed in the gate gap. In addition, the edge of the stacked structure 200 may be trimmed to be stepped to form the stepped structure 500.

In one embodiment of the present application, a substrate 100 includes: substrate 110, conductive layer 900, and source contact 910. The substrate 110 includes a doped region 130. The conductive layer 900 is formed in the doped region 130 and extends through a side portion of the channel structure 300. The source contact 910 is disposed in the doped region 130 corresponding to the gate gap 410 and is led out from the side of the substrate 110 far away from the stacked structure 200. The conductive layer 900 includes a semiconductor layer and an insulating layer wrapped by the semiconductor layer. The source contact 910 includes a semiconductor layer and an insulating layer surrounded by the semiconductor layer. In this embodiment mode, the insulating layer can reduce the resistance of the conductor layer and the source contact, and further, the semiconductor layer can be formed using a semiconductor material having a relatively low doping concentration.

In one embodiment of the present application, a substrate 100 includes: substrate 110, conductive layer 900, and source contact 910. The substrate 110 includes a doped region 130. The conductive layer 900 is formed in the doped region 130 and extends through a side portion of the channel structure 300. The source contact 910 is disposed in the doped region 130 corresponding to the gate gap 410 and is led out from the side of the substrate 110 away from the stacked structure 200. The source contact 910 includes a semiconductor layer and an insulating layer surrounded by the semiconductor layer. In this embodiment mode, the insulating layer can reduce the resistance of the source contact, and further, a semiconductor material having a relatively low doping concentration can be selected to form the semiconductor layer.

In one embodiment of the present application, a substrate 100 includes: substrate 110, conductive layer 900, and source contact 910. The substrate 110 includes a doped region 130. The conductive layer 900 is formed in the doped region 130 and extends through a side portion of the channel structure 300. The source contact 910 is disposed in the doped region 130 corresponding to the gate gap 410 and is led out from the side of the substrate 110 away from the stacked structure 200. The source contact 910 and the conductive layer 900 are semiconductor layers.

In one embodiment of the present application, a fill gap 911 is formed in the source contact 910.

Alternatively, in one embodiment of the present application, the peripheral circuit chip 3000 includes: a first substrate 700 and peripheral circuitry 800. The first substrate 700 may be a single crystal silicon layer formed by removing a bulk of silicon on insulator, wherein the first substrate 700 includes opposing first and second sides, wherein the first side may be bonded to the front side 170 of the memory device. Peripheral circuitry 800 is disposed on a second side of substrate 700.

Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described in detail.

The three-dimensional memory device can effectively avoid the electrical property of a peripheral circuit from being reduced due to the thermal influence of the front face forming process, so that the combined memory device and a peripheral circuit chip can jointly resist the stress generated by each film layer in the three-dimensional memory, meanwhile, in the process of forming the three-dimensional memory device, the preparation process is simplified, the preparation period is shortened, and under the condition of increasing the stacking layer number of the three-dimensional memory, a machine table is not replaced, and the corresponding preparation process can be realized.

The above description is only an embodiment of the present application and an illustration of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of protection covered by this application is not limited to the embodiments with a specific combination of features described above, but also covers other embodiments with any combination of features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (19)

1. A method of fabricating a three-dimensional memory, the method comprising:

preparing an intermediate body including a second substrate, a stacked structure, a channel structure and a gate gap structure; and

processing the second substrate from a side of the second substrate far away from the stacked structure, forming an opening in the second substrate at a position corresponding to a gate gap of the gate gap structure, forming a source contact by filling a semiconductor material in the opening or forming a semiconductor layer on an inner wall of the opening and filling an insulating material in the opening,

wherein the source contact at least partially overlaps with a projection of the gate gap structure in a stacking direction of the stacked structure.

2. The method of claim 1, further comprising:

after forming the intermediate body, providing a first substrate, and combining a first side of the first substrate with the intermediate body; and

peripheral circuitry is formed on a second side of the first substrate opposite the first side.

3. The method of claim 2, wherein providing a first substrate, and bonding a first side of the first substrate to the intermediate body comprises:

providing a silicon-on-insulator comprising a substrate and a monocrystalline silicon layer; and

bonding a surface of the silicon-on-insulator proximate the substrate to the intermediate.

4. The method of claim 3, wherein prior to forming peripheral circuitry on a second side of the first substrate opposite the first side, the method further comprises:

after the first surface of the first substrate is bonded to the intermediate body, the bulk of the silicon-on-insulator is removed to obtain a single-crystal silicon layer which is independent, and the peripheral circuit is formed on the surface of the single-crystal silicon layer.

5. The method of claim 2, wherein preparing an intermediate comprising the second substrate, the stack structure, the channel structure, and the gate gap structure comprises:

forming a stacked structure including a plurality of gate layers over a second substrate;

forming a channel structure penetrating through the laminated structure;

forming a gate gap structure having a spacing from the channel structure; and

trimming the edge of the stacked structure to form a stepped structure connected to the channel structure through the gate layer.

6. The method of claim 5, wherein the second substrate comprises a base far away from the stacked structure, and a first doped layer, a sacrificial stacked layer and a second doped layer sequentially formed on the base, wherein the sacrificial stacked layer comprises a dielectric layer, a sacrificial layer and a dielectric layer sequentially arranged.

7. The method of claim 6, the channel structure extending to the first doping layer and including a channel hole and a functional layer and a channel layer sequentially formed on an inner wall of the channel hole, wherein after forming a peripheral circuit on a second face of the first substrate opposite to the first face, the method further comprises:

processing the second substrate from the side of the second substrate far away from the laminated structure to remove the base and form an opening at the position of the first doping layer corresponding to the gate gap;

removing the sacrificial stack through the opening to form a substrate cavity; and

removing the functional layer exposed in the substrate cavity to expose the channel layer.

8. The method of claim 7, wherein after removing the functional layer exposed in the substrate cavity to expose the channel layer, the method further comprises:

and forming a semiconductor layer on the surface of the doping layer far away from the laminated structure, the inner wall of the opening and the inner wall of the substrate cavity so as to be connected with the exposed channel layer, and filling an insulating material in the substrate cavity and the opening.

9. The method of claim 7, wherein after removing the functional layer exposed in the substrate cavity to expose the channel layer, the method further comprises:

filling a semiconductive material in the substrate cavity to connect the exposed channel layer; and

and forming a semiconductor layer on the surface of the doped layer far away from the laminated structure and the inner wall of the opening, and filling an insulating material in the opening.

10. The method of claim 7, wherein after removing the functional layer exposed in the substrate cavity to expose the channel layer, the method further comprises:

filling semiconductive material in the substrate cavity and the opening to connect the exposed channel layer; and

and forming a semiconductor layer on the surface of the doped layer far away from the laminated structure.

11. The method of claim 8, wherein filling the opening with an insulating material comprises:

in the step of filling the insulating material, a filling gap is formed in the opening.

12. The method of claim 10, wherein filling the opening with a conductive material comprises:

in the step of filling the semiconductive material, a fill gap is formed in the opening.

13. A three-dimensional memory, comprising:

the memory device comprises a second substrate, a laminated structure arranged on the second substrate, a channel structure penetrating through the laminated structure, and a grid gap structure penetrating through the laminated structure and having a distance with the channel structure, wherein the second substrate comprises a source contact, and the source contact corresponds to the grid gap and is led out from one side departing from the laminated structure; and

a peripheral circuit device chip including a first substrate and a peripheral circuit,

the source contact is a semiconductor layer, or the source contact comprises a semiconductor layer and an insulating layer wrapped by the semiconductor layer; and

the source contact at least partially overlaps with a projection of the gate gap structure in a stacking direction of the stacked structure.

14. The memory of claim 13, wherein the first substrate is a single crystal silicon layer formed by removing a bulk of silicon on insulator.

15. The memory of claim 13, wherein the storage device comprises:

a second substrate, which is a substrate,

a stacked structure disposed on the second substrate, the stacked structure including gate layers and insulating layers alternately stacked;

a channel structure passing through the stacked structure and extending into the second substrate.

16. The memory of claim 15, wherein the second substrate comprises:

a substrate including a doped region;

a conductive layer formed in the doped region and extending through a side portion of the channel structure; and

the source contact is arranged at the position of the doped region corresponding to the grid gap;

wherein the conductive layer comprises a semiconductor layer and an insulating layer wrapped by the semiconductor layer, an

The source contact includes a semiconductor layer and an insulating layer surrounded by the semiconductor layer.

17. The memory of claim 15, wherein the second substrate comprises:

a substrate including a doped region;

a conductive layer formed in the doped region and extending through a side portion of the channel structure; and

the source contact is arranged at the position of the doped region corresponding to the grid gap;

wherein the source contact comprises a semiconductor layer and an insulating layer wrapped by the semiconductor layer.

18. The memory of claim 15, wherein the second substrate comprises:

a substrate including a doped region;

a conductive layer formed in the doped region and extending through a side portion of the channel structure; and

the source contact is arranged at the position of the doped region corresponding to the grid gap;

wherein the source contact and the conductive layer are semiconductor layers.

19. The memory according to claim 16 or 18,

a fill gap is formed in the source contact.

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