CN115167611A - PCIE equipment clock holding device and method and readable storage medium - Google Patents

PCIE equipment clock holding device and method and readable storage medium Download PDF

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Publication number
CN115167611A
CN115167611A CN202210730551.8A CN202210730551A CN115167611A CN 115167611 A CN115167611 A CN 115167611A CN 202210730551 A CN202210730551 A CN 202210730551A CN 115167611 A CN115167611 A CN 115167611A
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CN
China
Prior art keywords
clock
data
circuit
local board
pcie
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Pending
Application number
CN202210730551.8A
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Chinese (zh)
Inventor
李妍
郝沁汾
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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Priority to CN202210730551.8A priority Critical patent/CN115167611A/en
Publication of CN115167611A publication Critical patent/CN115167611A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a PCI E device clock holding device, a PCI E device clock holding method and a readable storage medium, wherein the device comprises: the PCI E switching chip is used for acquiring the clock data of the local board in real time; the delay circuit is used for reserving the transmission data of the PC IE switching chip within a preset time; a clock extraction circuit to recover clock data from the transmit data to complete clock extraction; a clock lock circuit to lock the clock data; the clock selection circuit is used for selecting the clock data as an available clock of the local board; and the clock driving circuit is used for providing a local board service clock based on the local board available clock. The invention can provide the function of keeping the clock of the system in a short time when the clock of the local board system has a fault, and avoids the occurrence of system faults caused by the interruption of all service channels due to the loss of the system clock.

Description

PCIE equipment clock holding device and method and readable storage medium
Technical Field
The present invention relates to the field of circuit control technologies, and in particular, to a clock holding apparatus and method for a PCIE device, and a readable storage medium.
Background
The PCI-Express (peripheral component interconnect Express) is a high-speed serial computer expansion bus standard, belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, and connected devices distribute independent channel bandwidth and do not share bus bandwidth, and mainly support functions of active power management, error report, end-to-end reliability transmission, hot plug, quality of service (QOS) and the like.
Since the PCIE device is a device that carries high-speed services and the system clock is an indispensable component unit for normal operation of the entire operating device, when the system clock is lost due to a fault, the entire system will fall into a state of stopping all services at once, so that if the system can obtain the clock through internal processing, the loss caused by the system completely stopping services is greatly reduced.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a clock holding apparatus, method and readable storage medium for PCIE device, which can provide a clock holding function of a system in a short time when a local board system clock fails, and avoid occurrence of system failure due to interruption of all service channels caused by loss of the system clock.
A first aspect of the present invention provides a device for maintaining a clock of PCIE device, where the device includes:
the PCIE switching chip is used for acquiring local board clock data in real time;
the delay circuit is used for reserving the transmitting data of the PCIE switching chip within a preset time, wherein the transmitting data is sent out from a transmitting end of the PCIE switching chip;
a clock extraction circuit to recover clock data from the transmit data to complete clock extraction;
a clock locking circuit for locking the clock data;
the clock selection circuit is used for selecting the clock data as an available clock of the local board;
the clock driving circuit is used for providing a local board service clock based on the local board available clock;
the input end of the delay circuit is electrically connected with the transmitting end of the PCIE switching chip, and the output end of the delay circuit is electrically connected with the receiving end of the PCIE switching chip; the input end of the clock extraction circuit is electrically connected with the output end of the delay circuit, and the output end of the clock extraction circuit is electrically connected with the input end of the clock locking circuit; the output end of the clock locking circuit is electrically connected with the input end of the clock selection circuit; the output end of the clock selection circuit is electrically connected with the input end of the clock driving circuit; the output end of the clock driving circuit is electrically connected with the input end of the PCIE switching chip.
In this scheme, the device further comprises a clock generator, wherein the clock generator is used for providing the available clock of the board, and the output end of the clock generator is electrically connected with the input end of the clock selection circuit.
In this scheme, the device further comprises an external clock input unit electrically connected to the input terminal of the clock selection circuit and used for acquiring external clock input data.
In this scheme, the delay circuit sends the transmission data back to the receiving end of the PCIE switch chip, and the transmitting end and the receiving end of the PCIE switch chip perform return processing.
The second aspect of the present invention further provides a method for maintaining a clock of a PCIE device, where the method includes the following steps:
the state of the local board system clock is monitored, wherein,
when the local board system clock is monitored to have a fault, the following method steps are executed:
acquiring local board clock data and transmitting the local board clock data from a transmitting terminal of the PCIE switching chip;
reserving the transmission data of the PCIE switching chip within a preset time;
recovering clock data from the transmit data to complete clock extraction;
locking the clock data;
selecting the clock data as an available clock of the board;
providing a board service clock based on the board available clock
In the scheme, when the local board system clock is not monitored to have a fault, the selection data of the clock selection circuit is acquired so as to switch different local board service clocks.
In the scheme, when the clock of the local board system is not monitored to have a fault, the method further comprises the step of obtaining local board available clock data provided by the clock generator or obtaining external clock input data.
In this scheme, the method further includes extracting the local board clock data from one of the downlink traffic channels of the PCIE switch chip.
In this scheme, the method further comprises extracting the current system clock as the local board service clock after the local board system clock is failed and repaired.
A third aspect of the present invention provides a computer-readable storage medium, where the computer-readable storage medium includes a PCIE device clock holding method program of a machine, and when the PCIE device clock holding method program is executed by a processor, the step of implementing the PCIE device clock holding method according to any one of the above items is implemented.
The invention discloses a clock holding device, a clock holding method and a readable storage medium of PCIE equipment, which can provide the clock holding function of a system in a short time when a local board system clock has a fault, and avoid the occurrence of system faults caused by the interruption of all service channels due to the loss of the system clock.
Drawings
Fig. 1 shows a schematic structural diagram of an embodiment of a PCIE device clock holding apparatus according to the present invention;
fig. 2 is a schematic structural diagram of a PCIE device clock holding apparatus in another embodiment of the present invention;
fig. 3 is a flowchart illustrating a method for clock keeping of PCIE devices according to an embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced otherwise than as specifically described herein and, therefore, the scope of the present invention is not limited by the specific embodiments disclosed below.
Fig. 1 shows a schematic structural diagram of a clock holding apparatus of a PCIE device according to the present application.
As shown in fig. 1, the present application discloses a PCIE device clock holding apparatus, where the apparatus includes:
the PCIE switching chip is used for acquiring local board clock data in real time;
the delay circuit is used for reserving the transmitting data of the PCIE switching chip within a preset time, wherein the transmitting data is sent out from a transmitting end of the PCIE switching chip;
a clock extraction circuit to recover clock data from the transmit data to complete clock extraction;
a clock locking circuit for locking the clock data;
the clock selection circuit is used for selecting the clock data as a local available clock;
the clock driving circuit is used for providing a local board service clock based on the local board available clock;
the input end of the delay circuit is electrically connected with the transmitting end of the PCIE switching chip, and the output end of the delay circuit is electrically connected with the receiving end of the PCIE switching chip; the input end of the clock extraction circuit is electrically connected with the output end of the delay circuit, and the output end of the clock extraction circuit is electrically connected with the input end of the clock locking circuit; the output end of the clock locking circuit is electrically connected with the input end of the clock selection circuit; the output end of the clock selection circuit is electrically connected with the input end of the clock driving circuit; the output end of the clock driving circuit is electrically connected with the input end of the PCIE switching chip.
It should be noted that, as shown in fig. 1, when a system clock fails, both the clock generator 7 and the external clock 8 cannot normally input the system clock, and at this time, the board clock data acquired by the PCIE switch chip 1 is used as the board service clock to provide a stable clock, where, as can be seen from fig. 1, the transmitting end TX of the PCIE switch chip 1 is electrically connected to the input end of the delay circuit 2, the output end of the delay circuit 2 is electrically connected to the receiving end RX of the PCIE switch chip 1, and is also electrically connected to the input end of the clock extraction circuit 3, the delay circuit 2 is configured to retain the transmitting data of the PCIE switch chip within a preset time, where the preset time is generally "2" minutes, and may be adjusted as required during actual application, and then the clock extraction circuit 3 may recover the clock data from the transmitting data to complete clock extraction, correspondingly, the output end of the clock extraction circuit 3 is electrically connected to the input end of the clock locking circuit 4, so that the clock locking circuit 4 can lock the corresponding clock data after acquiring the clock data, wherein the locking duration can be 24 hours, the locking duration can be adjusted as required in practical application, the output end of the clock locking circuit 4 is electrically connected to the input end of the clock selection circuit 5, thereby ensuring that the clock selection circuit 5 can select the clock data as a local available clock and output the clock data, and since the output end of the clock selection circuit 5 is electrically connected to the input end of the clock driving circuit 6, the clock driving circuit 6 can acquire the local available clock and provide the local service clock based on the local available clock, the short-time clock supply of the board system is completed, and the problem of service channel interruption caused by system clock loss is avoided.
According to the embodiment of the invention, the device further comprises a clock generator, wherein the clock generator is used for providing the available clock of the local board, and the output end of the clock generator is electrically connected with the input end of the clock selection circuit.
As shown in fig. 2, when the board system clock is normal, that is, the output data of the clock lock circuit 4 does not need to be accessed, that is, the circuit in the dashed line box is not used, the input clock of the clock generator 7 is used, and the clock selection circuit 5 selects the clock input by the clock generator 7 based on the clock input by the clock generator 7 and outputs the clock input by the clock generator 7 as the board available clock.
According to the embodiment of the invention, the input end of the clock selection circuit is also electrically connected with an external clock input unit for acquiring external clock input data.
As shown in fig. 2, when the board system clock is normal, that is, when the circuit in the dashed line box, which is the output data of the clock lock circuit 4, is not used, the clock input by the external clock 8 is used, and similarly, the clock selection circuit 5 selects the clock input by the external clock 8 as the board clock and outputs the clock.
According to the embodiment of the present invention, the delay circuit sends the transmission data back to the receiving end of the PCIE switch chip, and the transmitting end and the receiving end of the PCIE switch chip perform return processing.
It should be noted that, while the delay circuit 2 sends the transmission data back to the receiving end RX of the PCIE switch chip 1, the transmitting end TX and the receiving end RX inside the PCIE switch chip 1 perform processing back to form a closed loop, so that the continuity of the data sent to the delay circuit 2 can be more effectively maintained.
Fig. 3 is a schematic diagram illustrating steps of a PCIE device clock keeping method according to the present application.
As shown in fig. 3, the present application discloses a PCIE device clock keeping method, which includes the following steps:
step S302, monitoring the state of a local board system clock, wherein when the local board system clock is monitored to have a fault, the following method steps are executed:
step S304, acquiring local board clock data and sending the local board clock data from a transmitting end of the PCIE switching chip;
step S306, reserving the transmission data of the PCIE switching chip within a preset time;
step S308, recovering clock data from the transmitted data to finish clock extraction;
step S310, locking the clock data;
s312, selecting the clock data as an available clock of the board;
and step S314, providing a local board service clock based on the local board available clock.
It should be noted that, first, the state of the system clock of the board is monitored, when a system clock fault occurs, that is, when it is indicated that an input source of the current system clock cannot provide a normal system clock, the board clock data currently running on the board is acquired and sent from a transmitting end of the PCIE switch chip, the transmission data of the PCIE switch chip is retained within the preset time by using a delay circuit, where the transmission data includes the board clock data transmitted by the transmitting end of the PCIE switch chip, and the preset time may be set to "2" minutes, and may be adjusted as needed in specific actual application, and then a clock extraction circuit may be used to recover the clock data based on the retained transmission data to complete corresponding clock extraction, and further a clock locking circuit is used to lock the extracted clock data, so that the locked clock data is output to a clock selection circuit as the board available clock, and then a clock driving circuit may provide the board service clock for system running on the board based on the board available clock, so as to avoid the problem that a system service is stopped due to the loss of the system clock, the problem that the clock extraction is difficult to be manually maintained for a long time, and the system clock is difficult to be maintained for reminding of a long-time loss, and therefore, the system clock loss is difficult to remind the system clock loss.
It should be noted that the system clock represents a clock signal currently running on the local board, the service clock represents a clock signal currently available on the local board, and the clock signal becomes the system clock after the service clock is used as the clock signal running on the local board.
According to the embodiment of the invention, when the local board system clock is not in fault, the selection data of the clock selection circuit is obtained so as to switch different local board service clocks.
It should be noted that, when it is monitored that the local board system clock does not fail, the system clock is required when the PCIE device operates normally, and the selected data of the clock selection circuit is obtained to output, so that different local board service clocks can be switched based on different clock data, where a source of the system clock of the selected data includes a clock generator or an external clock input.
According to the embodiment of the invention, when the system clock of the local board is not in fault, the method further comprises the step of obtaining the available clock data of the local board provided by the clock generator.
It should be noted that, when the board system clock is running normally, the data input by the clock generator may be used as the board available clock data.
According to the embodiment of the invention, when the local board system clock is not in fault, the method further comprises the step of acquiring external clock input data.
It should be noted that, when the system clock of the board runs normally, the data input by the external clock may be used as the available clock data of the board.
According to the embodiment of the present invention, the method further includes extracting the local board clock data from one of the downlink service channels of the PCIE switch chip.
It should be noted that, in the above embodiment, the extraction of the local board service clock is completed by using the PCIE switch chip, the delay circuit, the clock extraction circuit, and the clock locking circuit, but in this embodiment, it is described that one of the downlink service channels of the PCIE switch chip may be set as a channel specially used for clock extraction to extract the local board clock data from the channel.
According to the embodiment of the invention, the method further comprises the step of extracting the current system clock as the local board service clock after the local board system clock is failed and repaired.
It should be noted that, in the above embodiment, it is described that the PCIE switch chip and the set peripheral circuit are used to complete the clock delay and the clock extraction recovery function after the local board system clock fails, but this content only can provide a short system clock holding function, and an alarm prompt is also sent after the system clock fails, so that after the local board system clock fails and is repaired, the clock recovery is not required to be performed again through the PCIE switch chip and the peripheral circuit, and the current recovered normal system clock may be directly used as the local board service clock, where the local board service clock includes input data of the clock generator or input data of the external clock.
A third aspect of the present invention provides a computer-readable storage medium, where the computer-readable storage medium includes a PCIE device clock keeping method program of a machine, and when the PCIE device clock keeping method program is executed by a processor, the steps of the PCIE device clock keeping method described in any one of the above are implemented.
The invention discloses a clock holding device, a clock holding method and a readable storage medium of PCIE equipment, which can provide the clock holding function of a system in a short time when a local board system clock has a fault, and avoid the occurrence of system faults caused by the interruption of all service channels due to the loss of the system clock.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or in other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps of implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer-readable storage medium, and when executed, executes the steps including the method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and various media capable of storing program codes.
Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

Claims (10)

1. A clock holding device for PCIE equipment is characterized by comprising:
the PCIE switching chip is used for acquiring local board clock data in real time;
the delay circuit is used for retaining the transmitting data of the PCIE switching chip within a preset time, wherein the transmitting data is transmitted from a transmitting end of the PCIE switching chip;
a clock extraction circuit to recover clock data from the transmit data to complete clock extraction;
a clock lock circuit to lock the clock data;
the clock selection circuit is used for selecting the clock data as a local available clock;
the clock driving circuit is used for providing a local board service clock based on the local board available clock;
the input end of the delay circuit is electrically connected with the transmitting end of the PCIE switching chip, and the output end of the delay circuit is electrically connected with the receiving end of the PCIE switching chip; the input end of the clock extraction circuit is electrically connected with the output end of the delay circuit, and the output end of the clock extraction circuit is electrically connected with the input end of the clock locking circuit; the output end of the clock locking circuit is electrically connected with the input end of the clock selection circuit; the output end of the clock selection circuit is electrically connected with the input end of the clock driving circuit; the output end of the clock driving circuit is electrically connected with the input end of the PCIE switching chip.
2. The apparatus of claim 1, further comprising a clock generator configured to provide the local board available clock, wherein an output of the clock generator is electrically connected to an input of the clock selection circuit.
3. The device according to claim 1, wherein the input terminal of the clock selection circuit is further electrically connected to an external clock input unit, configured to obtain external clock input data.
4. The clock holding apparatus of claim 1, wherein the delay circuit sends the transmission data back to a receiving end of the PCIE switch chip, and the transmitting end and the receiving end of the PCIE switch chip perform return processing.
5. A PCIE equipment clock keeping method is characterized in that the method comprises the following steps:
monitoring the state of the system clock of the board, wherein,
when the local board system clock is monitored to have a fault, the following method steps are executed:
acquiring local board clock data and transmitting the local board clock data from a transmitting end of the PCIE switching chip;
reserving the transmission data of the PCIE switching chip within a preset time;
recovering clock data from the transmit data to complete clock extraction;
locking the clock data;
selecting the clock data as an available clock of the board;
and providing a local board service clock based on the local board available clock.
6. The method according to claim 5, wherein when it is monitored that the local board system clock is not faulty, selection data of a clock selection circuit is obtained to switch different local board service clocks.
7. The clock holding method for a PCIE device according to claim 5, wherein when it is monitored that the local board system clock does not have a fault, the method further includes obtaining local board available clock data provided by a clock generator or obtaining external clock input data.
8. The method according to claim 5, wherein the method further includes extracting the local board clock data from one of the downlink traffic channels of the PCIE switching chip.
9. The method of claim 5, wherein the method further comprises extracting a current system clock as the local board service clock after the local board system clock fails and is repaired.
10. A computer-readable storage medium, wherein the computer-readable storage medium includes a PCIE device clock keeping method program, and when the PCIE device clock keeping method program is executed by a processor, the steps of a PCIE device clock keeping method according to any one of claims 5 to 9 are implemented.
CN202210730551.8A 2022-06-24 2022-06-24 PCIE equipment clock holding device and method and readable storage medium Pending CN115167611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210730551.8A CN115167611A (en) 2022-06-24 2022-06-24 PCIE equipment clock holding device and method and readable storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210730551.8A CN115167611A (en) 2022-06-24 2022-06-24 PCIE equipment clock holding device and method and readable storage medium

Publications (1)

Publication Number Publication Date
CN115167611A true CN115167611A (en) 2022-10-11

Family

ID=83487265

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210730551.8A Pending CN115167611A (en) 2022-06-24 2022-06-24 PCIE equipment clock holding device and method and readable storage medium

Country Status (1)

Country Link
CN (1) CN115167611A (en)

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