CN112527570B - I2C communication recovery method, device, equipment and computer readable storage medium - Google Patents
I2C communication recovery method, device, equipment and computer readable storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
- G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
Abstract
The invention discloses an I2C communication recovery method, which is applied to a CPLD logic chip and comprises the following steps: acquiring link state information corresponding to each I2C link in current operation; judging whether a fault link state exists in each link state information; if yes, determining the I2C link corresponding to the state of the fault link as the fault link, and switching the fault link to a preset standby I2C link. By applying the I2C communication recovery method provided by the invention, the automatic recovery of the I2C communication is realized, and the accurate acquisition of the running state of the server is ensured, thereby realizing the effective control of the server. The invention also discloses an I2C communication recovery device, equipment and a storage medium, and has corresponding technical effects.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a computer-readable storage medium for I2C communication recovery.
Background
The I2C bus is a bus widely used by a server, and is mainly used for monitoring the operation of hardware, and currently, in the normal operation of the server, the power supply, the memory, the hard disk, the temperature, the voltage and the like are all monitored through the I2C bus, so that the normal operation of the I2C bus is very important.
Hardware monitoring chips provide dozens of paths of I2C links, but these are not enough to monitor all devices, and extension chips such as I2C 9548 and I2C 9555 are widely used in practical use to extend I2C links. Because of the limitation of I2C communication, when one I2C link of the hardware monitoring chip is expanded into multiple I2C links through the expansion chip, if any one of the I2C links is hung, the whole I2C channel including the sub outgoing I2C link and the sub expansion I2C link is hung. In addition, after physical failure occurs to the sub-direct I2C link led out from the hardware monitoring chip, each subsequent sub-extended I2C link cannot operate normally, and after the link fails, hardware of the server cannot be monitored, the operating state of the server cannot be accurately obtained, so that the server is in an out-of-control state.
In summary, how to effectively solve the problems that the hardware of the server cannot be monitored due to the I2C link failure, and the server is in an out-of-control state, and the like, is a problem that needs to be solved urgently by those skilled in the art at present.
Disclosure of Invention
The invention aims to provide an I2C communication recovery method, which realizes automatic recovery of I2C communication and ensures accurate acquisition of the running state of a server, thereby realizing effective control of the server; another object of the present invention is to provide an I2C communication recovery apparatus, device and computer-readable storage medium.
In order to solve the technical problems, the invention provides the following technical scheme:
an I2C communication recovery method is applied to a CPLD logic chip and comprises the following steps:
acquiring link state information corresponding to each I2C link in current operation;
judging whether a fault link state exists in each link state information;
if yes, determining the I2C link corresponding to the state of the fault link as the fault link, and switching the fault link to a preset standby I2C link.
In a specific embodiment of the present invention, determining whether a failed link status exists in each of the link status information includes:
judging whether link state information with a fault enabling bit exceeding a preset time length exists in each link state information or not;
determining the I2C link corresponding to the fault link state as a fault link, including:
and determining the I2C link corresponding to the link state information with the fault enabling bit exceeding the preset duration as the fault link.
In a specific embodiment of the present invention, switching the failed link to a preset standby I2C link includes:
resetting the sub-extension I2C link contained in the fault link;
judging whether the fault link is recovered to be normal or not;
if not, switching the sub-direct-out I2C link in the fault link to a standby sub-direct-out I2C link in the standby I2C link to obtain a first switching link;
judging whether the first switching link operates normally or not;
if not, switching the sub-expansion I2C link in the fault link to a standby sub-expansion I2C link in the standby I2C link to obtain a second switching link.
In an embodiment of the present invention, the method further comprises:
when the first switching link is determined to operate normally, synchronizing the first switching link into a baseboard management controller so that the baseboard management controller dynamically initializes the driving of the first switching link;
and when the first switching link is determined to be not normally operated and the second switching link is determined to be normally operated, synchronizing the second switching link into the baseboard management controller so that the baseboard management controller dynamically initializes the driving of the second switching link.
An I2C communication recovery device is applied to a CPLD logic chip and comprises:
the state information acquisition module is used for acquiring the link state information corresponding to each currently running I2C link;
the judging module is used for judging whether a fault link state exists in each link state information;
and the link switching module is used for determining an I2C link corresponding to the fault link state as a fault link and switching the fault link to a preset standby I2C link when the fault link state exists in the link state information.
In a specific embodiment of the present invention, the determining module is specifically a module that determines whether there is link state information in which a fault enable bit exceeds a preset time length in each link state information;
the link switching module comprises a fault link determining submodule, and the fault link determining submodule is specifically a module for determining an I2C link corresponding to link state information of which the fault enabling bit exceeds the preset time length as the fault link.
In a specific embodiment of the present invention, the link switching module includes:
the link resetting submodule is used for resetting the sub-extended I2C link contained in the fault link;
the first judgment sub-module is used for judging whether the fault link is recovered to be normal or not;
the first link switching submodule is used for switching the sub straight-out I2C link in the fault link to the standby sub straight-out I2C link in the standby I2C link to obtain a first switching link when the fault link is determined not to be recovered to be normal;
the second judgment submodule is used for judging whether the first switching link operates normally or not;
and the second link switching submodule is used for switching the sub-extension I2C link in the fault link to the standby sub-extension I2C link in the standby I2C link to obtain a second switching link when the first switching link does not normally run.
In one embodiment of the present invention, the method further comprises:
the first link driving module is used for synchronizing the first switching link into a baseboard management controller when the first switching link is determined to operate normally, so that the baseboard management controller dynamically initializes the driving of the first switching link;
and the second link driving module is used for synchronizing the second switching link into the baseboard management controller when the first switching link is determined not to normally operate and the second switching link operates normally, so that the baseboard management controller dynamically initializes the driving of the second switching link.
An I2C communication recovery apparatus comprising:
a memory for storing a computer program;
a processor for implementing the steps of the I2C communication restoration method as described above when executing the computer program.
A computer-readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the I2C communication restoration method as set forth above.
The I2C communication recovery method provided by the invention is applied to a CPLD logic chip and used for acquiring the link state information corresponding to each currently operated I2C link; judging whether a fault link state exists in each link state information; if yes, determining the I2C link corresponding to the fault link state as a fault link, and switching the fault link to a preset standby I2C link. The method comprises the steps of deploying a CPLD logic chip for monitoring link state sub-information of each I2C link, presetting a standby I2C link, and switching a fault link to the preset standby I2C link when the fault link is monitored. Therefore, the automatic recovery of the I2C communication is realized, the accurate acquisition of the running state of the server is ensured, and the effective control of the server is realized.
Correspondingly, the invention also provides an I2C communication recovery device, equipment and a computer readable storage medium corresponding to the I2C communication recovery method, which have the technical effects described above and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of an implementation of an I2C communication recovery method according to an embodiment of the present invention;
FIG. 2 is a flowchart of another implementation of a method for recovering I2C communication according to an embodiment of the present invention;
fig. 3 is a block diagram of an I2C communication recovery apparatus according to an embodiment of the present invention;
fig. 4 is a block diagram of an I2C communication recovery device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, fig. 1 is a flowchart of an implementation of an I2C communication recovery method in an embodiment of the present invention, which is applied to a CPLD logic chip, and the method may include the following steps:
s101: and acquiring link state information corresponding to each I2C link in current operation.
In the operation process of the server, link state information corresponding to each I2C link which is currently operated is obtained, namely the link state information of each I2C link which is currently used for signal transmission between the hardware monitoring chip and the hardware is obtained.
S102: and judging whether the link state information has a fault link state or not, if not, not processing, and if so, executing the step S103.
After the link state information corresponding to each I2C link in current operation is acquired, whether a faulty link state exists in each link state information is determined, if not, it indicates that each I2C link in current operation is normal, and no processing is required, if yes, it indicates that an I2C link incapable of performing normal transmission on a signal between a hardware monitoring chip and hardware exists, and step S103 is executed.
S103: and determining the I2C link corresponding to the state of the fault link as the fault link, and switching the fault link to a preset standby I2C link.
And when the state information of each link is determined to have the state of the failed link, determining the I2C link corresponding to the state of the failed link as the failed link, and switching the failed link to the preset standby I2C link. The method comprises the steps of deploying a CPLD logic chip for monitoring link state sub-information of each I2C link, presetting a standby I2C link, and switching a fault link to the preset standby I2C link when the fault link is monitored. Therefore, automatic recovery of I2C communication is realized, accurate acquisition of the running state of the server is guaranteed, effective control over the server is realized, and the running life of the server is prolonged.
The I2C communication recovery method provided by the invention is applied to a CPLD logic chip and used for acquiring the link state information corresponding to each currently operated I2C link; judging whether a fault link state exists in each link state information; if yes, determining the I2C link corresponding to the state of the fault link as the fault link, and switching the fault link to a preset standby I2C link. The method comprises the steps of deploying a CPLD logic chip for monitoring link state sub-information of each I2C link, presetting a standby I2C link, and switching a fault link to the preset standby I2C link when the fault link is monitored. Therefore, automatic recovery of I2C communication is realized, accurate acquisition of the running state of the server is ensured, and effective control over the server is realized.
It should be noted that, based on the first embodiment, the embodiment of the present invention further provides a corresponding improvement scheme. In the following embodiments, steps that are the same as or correspond to those in the first embodiment may be referred to each other, and corresponding advantageous effects may also be referred to each other, which are not described in detail in the following modified embodiments.
The second embodiment:
referring to fig. 2, fig. 2 is a flowchart of another implementation of an I2C communication recovery method in the embodiment of the present invention, which is applied to a CPLD logic chip, and the method may include the following steps:
s201: and acquiring link state information corresponding to each currently operated I2C link.
S202: and judging whether the link state information with the fault enabling bit exceeding the preset duration exists in each link state information, if not, not processing, and if so, executing the step S203.
Presetting the time length of a fault enabling bit of link state information allowed when the I2C link normally operates, judging whether the link state information with the fault enabling bit exceeding the preset time length exists in each link state information after the link state information corresponding to each I2C link currently operates is obtained, if not, indicating that each I2C link currently operates is normal without any processing, if yes, indicating that an I2C link incapable of normally transmitting signals between a hardware monitoring chip and hardware exists, and executing the step S203.
For example, under the condition that the CPLD logic chip is under 400MHZ according to the I2C clock signal CLK and the SMBUS protocol, 256 bytes of continuous I2C links are pulled down continuously, link failure is calculated, and whether link state information with failure enable bits exceeding preset duration exists in each link state information or not is judged.
It should be noted that the preset time period may be set and adjusted according to actual situations, which is not limited in the embodiment of the present invention.
S203: and determining the I2C link corresponding to the link state information with the fault enabling bit exceeding the preset time length as a fault link.
And when determining that the link state information with the fault enabling bit exceeding the preset time length exists in the link state information, determining the I2C link corresponding to the link state information with the fault enabling bit exceeding the preset time length as a fault link.
S204: and carrying out reset operation on the sub-extended I2C link contained in the failed link.
When a sub-direct-out I2C link in an I2C link is expanded in advance, a reset mechanism of the expanded sub-expanded I2C link is set. And after the I2C link corresponding to the link state information with the fault enabling bit exceeding the preset duration is determined as the fault link, resetting the sub-extended I2C link contained in the fault link. And attempting to automatically repair the failed link by performing reset operation on the sub-extended I2C link contained in the failed link.
S205: and judging whether the fault link is recovered to be normal, if so, executing step S206, and if not, executing step S207.
After the sub-extension I2C link included in the failed link is reset, it is determined whether the failed link is recovered to be normal, if so, it indicates that the sub-extension I2C link included in the failed link is temporarily abnormal, step S206 is performed, otherwise, it indicates that the failed link cannot be automatically repaired by resetting the sub-extension I2C link included in the failed link, and step S207 is performed.
S206: and outputting the prompt information of abnormal connection of the sub-extension I2C link.
After the sub-extension I2C link contained in the fault link is reset and the fault link is determined to be recovered to be normal, outputting abnormal connection prompt information of the sub-extension I2C link, and prompting a user that the current link fault is the temporary abnormality of the sub-extension I2C link contained in the fault link.
S207: and switching the sub-outgoing I2C link in the fault link to a standby sub-outgoing I2C link in the standby I2C link to obtain a first switching link.
And the standby I2C link comprises a standby sub-outgoing I2C link, and after the condition that the failed link is not recovered to be normal is determined by carrying out reset operation on the sub-extended I2C link contained in the failed link, the sub-outgoing I2C link in the failed link is switched to the standby sub-outgoing I2C link in the standby I2C link to obtain a first switched link.
S208: and judging whether the first switching link normally operates, if so, executing step S209, otherwise, executing step S210.
After the sub-direct-out I2C link in the failed link is switched to the standby sub-direct-out I2C link in the standby I2C link, and the first switched link is obtained, it is determined whether the first switched link operates normally, if yes, it is determined that the current link failure is the sub-direct-out I2C link failure included in the failed link, step S209 is performed, if no, it is determined that the current link failure is not the sub-direct-out I2C link failure included in the failed link, and step S210 is performed.
S209: and synchronizing the first switching link into the baseboard management controller so that the baseboard management controller dynamically initializes the driving of the first switching link.
When the sub-straight-out I2C link in the fault link is determined to be switched to the standby sub-straight-out I2C link in the standby I2C link, and the obtained first switching link operates normally, the link fault is the sub-straight-out I2C link fault contained in the fault link, the first switching link is synchronized into the baseboard management controller, and the baseboard management controller dynamically initializes the drive of the first switching link, so that the newly established drive of the first switching link is started to monitor corresponding hardware. Besides, the sub-direct-out I2C link failure prompt information can be output.
S210: and switching the sub-expansion I2C link in the fault link to a standby sub-expansion I2C link in a standby I2C link to obtain a second switching link.
When the sub-direct-out I2C link in the fault link is determined to be switched to the standby sub-direct-out I2C link in the standby I2C link, and the obtained first switching link still cannot normally operate, the link fault is indicated to be not the sub-direct-out I2C link fault included in the fault link, the sub-extended I2C link in the fault link is switched to the standby sub-extended I2C link in the standby I2C link, and a second switching link is obtained.
S211: and when the second switching link is determined to operate normally, synchronizing the second switching link into the baseboard management controller so that the baseboard management controller dynamically initializes the driving of the second switching link.
When the second switching link is determined to operate normally, the link failure is described to be a sub-extension I2C link failure included in the failed link, the second switching link is synchronized into the baseboard management controller, and the baseboard management controller dynamically initializes the drive of the second switching link, so that the newly established drive of the second switching link is started to monitor corresponding hardware. Besides, the fault prompt information of the sub-extension I2C link can be output.
The present embodiment is different from the first embodiment corresponding to the technical solution claimed in independent claim 1, and the technical solutions claimed in the dependent claims 2 to 4 are added, and certainly, according to different practical situations and requirements, the technical solutions claimed in the dependent claims can be flexibly combined on the basis of not affecting the integrity of the solutions, so as to better meet the requirements of different use scenarios.
Corresponding to the above method embodiment, the present invention further provides an I2C communication recovery apparatus, and the I2C communication recovery apparatus described below and the I2C communication recovery method described above may be referred to correspondingly.
Referring to fig. 3, fig. 3 is a block diagram of an I2C communication recovery apparatus in an embodiment of the present invention, which is applied to a CPLD logic chip, and the apparatus may include:
a status information obtaining module 31, configured to obtain link status information corresponding to each I2C link that is currently running;
a judging module 32, configured to judge whether a faulty link state exists in each link state information;
and a link switching module 33, configured to determine, when it is determined that a faulty link state exists in each link state information, an I2C link corresponding to the faulty link state as a faulty link, and switch the faulty link to a preset standby I2C link.
The I2C communication recovery device provided by the invention is applied to a CPLD logic chip and used for acquiring the link state information corresponding to each currently operated I2C link; judging whether a fault link state exists in each link state information; if yes, determining the I2C link corresponding to the state of the fault link as the fault link, and switching the fault link to a preset standby I2C link. The method comprises the steps of deploying a CPLD logic chip for monitoring link state sub-information of each I2C link, presetting a standby I2C link, and switching a fault link to the preset standby I2C link when the fault link is monitored. Therefore, automatic recovery of I2C communication is realized, accurate acquisition of the running state of the server is ensured, and effective control over the server is realized.
In a specific embodiment of the present invention, the determining module 32 is a module that determines whether there is link state information in which the fault enable bit exceeds a preset time length in each link state information;
the link switching module 33 includes a faulty link determining submodule, which is specifically a module that determines an I2C link corresponding to link state information in which a fault enable bit exceeds a preset time length as a faulty link.
In a specific embodiment of the present invention, the link switching module 33 includes:
the link resetting submodule is used for resetting the sub-extended I2C link contained in the fault link;
the first judgment sub-module is used for judging whether the fault link is recovered to be normal or not;
the first link switching submodule is used for switching the sub-direct-out I2C link in the fault link to the standby sub-direct-out I2C link in the standby I2C link to obtain a first switching link when the fault link is determined not to be recovered to normal;
the second judgment submodule is used for judging whether the first switching link operates normally;
and the second link switching submodule is used for switching the sub-extension I2C link in the fault link to the standby sub-extension I2C link in the standby I2C link to obtain a second switching link when the first switching link of the eggplant does not normally operate.
In one embodiment of the present invention, the apparatus may further include:
the first link driving module is used for synchronizing the first switching link into the baseboard management controller when the first switching link is determined to operate normally, so that the baseboard management controller dynamically initializes the driving of the first switching link;
and the second link driving module is used for synchronizing the second switching link into the baseboard management controller when the first switching link is determined to be not normally operated and the second switching link is determined to be normally operated, so that the baseboard management controller dynamically initializes the driving of the second switching link.
Corresponding to the above method embodiment, referring to fig. 4, fig. 4 is a schematic diagram of an I2C communication recovery apparatus provided in the present invention, where the apparatus may include:
a memory 41 for storing a computer program;
the processor 42, when executing the computer program stored in the memory 41, may implement the following steps:
acquiring link state information corresponding to each I2C link in current operation; judging whether a fault link state exists in each link state information; if yes, determining the I2C link corresponding to the fault link state as a fault link, and switching the fault link to a preset standby I2C link.
For the introduction of the device provided by the present invention, please refer to the above method embodiment, which is not described herein again.
Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the steps of:
acquiring link state information corresponding to each I2C link in current operation; judging whether a fault link state exists in each link state information; if yes, determining the I2C link corresponding to the state of the fault link as the fault link, and switching the fault link to a preset standby I2C link.
The computer-readable storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
For the introduction of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not described herein again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The apparatuses, devices and computer-readable storage media disclosed in the embodiments correspond to the methods disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (8)
1. An I2C communication recovery method is applied to a CPLD logic chip and comprises the following steps:
acquiring link state information corresponding to each I2C link in current operation;
judging whether a fault link state exists in each link state information;
if so, determining the I2C link corresponding to the state of the fault link as the fault link, and switching the fault link to a preset standby I2C link;
switching the failed link to a preset standby I2C link, including:
resetting the sub-extension I2C link contained in the fault link;
judging whether the fault link is recovered to be normal or not;
if not, switching the sub-direct-out I2C link in the fault link to a standby sub-direct-out I2C link in the standby I2C link to obtain a first switching link;
judging whether the first switching link operates normally or not;
if not, switching the sub-expansion I2C link in the fault link to a standby sub-expansion I2C link in the standby I2C link to obtain a second switching link.
2. The I2C communication recovery method according to claim 1, wherein determining whether there is a failed link state in each of the link state information includes:
judging whether link state information with a fault enabling bit exceeding a preset time length exists in each link state information or not;
determining the I2C link corresponding to the fault link state as a fault link, including:
and determining the I2C link corresponding to the link state information with the fault enabling bit exceeding the preset duration as the fault link.
3. The I2C communication recovery method of claim 1, further comprising:
when the first switching link is determined to operate normally, synchronizing the first switching link into a baseboard management controller so that the baseboard management controller dynamically initializes the driving of the first switching link;
and when the first switching link is determined to be not normally operated and the second switching link is determined to be normally operated, synchronizing the second switching link into the baseboard management controller so that the baseboard management controller dynamically initializes the driving of the second switching link.
4. An I2C communication recovery device, which is applied to a CPLD logic chip, comprises:
the state information acquisition module is used for acquiring the link state information corresponding to each currently running I2C link;
the judging module is used for judging whether a fault link state exists in each link state information;
the link switching module is used for determining an I2C link corresponding to the fault link state as a fault link and switching the fault link to a preset standby I2C link when the fault link state exists in the link state information;
the link switching module includes:
the link resetting submodule is used for resetting the sub-extended I2C link contained in the fault link;
the first judgment sub-module is used for judging whether the fault link is recovered to be normal or not;
the first link switching submodule is used for switching the sub-straight-out I2C link in the fault link to a standby sub-straight-out I2C link in the standby I2C link to obtain a first switching link when the fault link is determined not to be recovered to be normal;
the second judgment submodule is used for judging whether the first switching link operates normally;
and the second link switching submodule is used for switching the sub-extension I2C link in the fault link to the standby sub-extension I2C link in the standby I2C link to obtain a second switching link when the first switching link does not normally run.
5. The I2C communication recovery device according to claim 4, wherein the determining module is specifically a module that determines whether there is link state information in which a fault enable bit exceeds a preset duration in each of the link state information;
the link switching module comprises a fault link determining submodule, and the fault link determining submodule is specifically a module for determining an I2C link corresponding to the link state information of which the fault enabling bit exceeds the preset duration as the fault link.
6. The I2C communication recovery apparatus according to claim 4, further comprising:
the first link driving module is used for synchronizing the first switching link into a baseboard management controller when the first switching link is determined to operate normally, so that the baseboard management controller dynamically initializes the driving of the first switching link;
and the second link driving module is used for synchronizing the second switching link into the baseboard management controller when the first switching link is determined not to normally operate and the second switching link operates normally, so that the baseboard management controller dynamically initializes the driving of the second switching link.
7. An I2C communication recovery device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the I2C communication restoration method according to any one of claims 1 to 3 when executing the computer program.
8. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the I2C communication restoration method according to any one of claims 1 to 3.
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| CN101123542A (en) * | 2007-07-30 | 2008-02-13 | 华为技术有限公司 | Method and system for link failure detection and device for link failure detection |
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