CN112422388B - Communication device, method, system and electronic equipment - Google Patents
Communication device, method, system and electronic equipment Download PDFInfo
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- CN112422388B CN112422388B CN202011305648.1A CN202011305648A CN112422388B CN 112422388 B CN112422388 B CN 112422388B CN 202011305648 A CN202011305648 A CN 202011305648A CN 112422388 B CN112422388 B CN 112422388B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
- H04L12/4035—Bus networks with centralised control, e.g. polling in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit
Abstract
The application discloses a communication device, a method, a system and an electronic device, comprising a first programmable logic device and a second programmable logic device; the first programmable logic device and the second programmable logic device are both provided with a first bus clock communication port, and the first programmable logic device transmits a first bus clock to the second programmable logic device through the first bus clock communication port; the first programmable logic device and the second programmable logic device are both provided with a first bus frame head communication port, and the first programmable logic device transmits a first bus frame head to the second programmable logic device through the first bus frame head communication port; the first programmable logic device is provided with a first communication slot position, the second programmable logic device is provided with a second communication slot position, and the first communication slot position is connected with the second communication slot position through a data bus. The first bus clock and the first bus frame header are generated by the programmable logic device, and are independent of software, so that the CPU occupancy rate is reduced.
Description
Technical Field
The present application relates to the field of information processing technologies, and in particular, to a communication apparatus, a method, a system, and an electronic device.
Background
At present, a device such as a switch and the like is provided with a plurality of service boards, so in the application process of the device, information transmission may be performed between the service boards, one method is to perform inter-board out-of-band information communication, and the other method is to implement inter-board communication through a communication bus, such as I2C, a serial port and the like.
However, in the process of implementing inter-board communication through the communication bus, software operation is required, and the occupancy rate of a Central Processing Unit (CPU) is increased.
In summary, how to reduce the CPU occupancy rate during inter-board communication is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The purpose of the present application is to provide a communication device which can solve the technical problem of how to reduce the CPU occupancy rate during the inter-board communication to a certain extent. The application also provides a communication method, a communication system and electronic equipment.
In a first aspect, the present application provides a communication apparatus comprising: the first programmable logic device and the second programmable logic device;
the first programmable logic device is provided with a first bus clock sending port, the second programmable logic device is provided with a first bus clock receiving port, and the first programmable logic device transmits a first bus clock generated by the first programmable logic device to the second programmable logic device through the first bus clock sending port and the first bus clock receiving port;
the first programmable logic device is provided with a first bus frame header sending port, the second programmable logic device is provided with a first bus frame header receiving port, and the first programmable logic device transmits a first bus frame header generated by the first programmable logic device to the second programmable logic device through the first bus frame header sending port and the first bus frame header receiving port;
the first programmable logic device is provided with a first communication slot position, the second programmable logic device is provided with a second communication slot position, the first communication slot position and the second communication slot position are connected through a data bus, and the first communication slot position and the second communication slot position carry out time division multiplexing communication based on a target bus clock and a target bus frame header; the target bus clock comprises a bus clock determined based on the first bus clock, and the target bus frame header comprises a bus frame header determined based on the first bus frame header.
Preferably, the device further comprises a third programmable logic device;
the third programmable logic device is provided with a second bus clock sending port, the second programmable logic device is provided with a second bus clock receiving port, and the third programmable logic device transmits a second bus clock generated by the third programmable logic device to the second programmable logic device through the second bus clock sending port and the second bus clock receiving port;
the third programmable logic device is provided with a second bus frame header sending port, the second programmable logic device is provided with a second bus frame header receiving port, and the third programmable logic device transmits a second bus frame header generated by the third programmable logic device to the second programmable logic device through the second bus frame header sending port and the second bus frame header receiving port;
the third programmable logic device is provided with a third communication slot position, the third communication slot position is connected with the first communication slot position through the data bus, the third communication slot position is connected with the second communication slot position through the data bus, and the third communication slot position and the second communication slot position carry out time division multiplexing communication based on the target bus clock and the target bus frame header;
a bus clock arbitration port and a bus frame header arbitration port are arranged between the first programmable logic device and the third programmable logic device, the first programmable logic device and the third programmable logic device select the target bus clock from the first bus clock and the second bus clock through the bus clock arbitration port, and the first programmable logic device and the third programmable logic device select the target bus frame header from the first bus frame header and the second bus frame header through the bus frame header arbitration port.
Preferably, the first communication slot is connected with the data bus through a first anti-interference chip, and the second communication slot is connected with the data bus through a second anti-interference chip.
Preferably, the first anti-interference chip and the second anti-interference chip are of a type including 485 communication chips.
In a second aspect, the present application provides a communication method applied to a target programmable logic device, including:
determining a target bus clock and a target bus frame header, wherein the target bus clock and the target bus frame header are generated by a programmable logic device;
determining a communication time slot of each target communication slot position in the target programmable logic device based on the target bus frame header;
based on the communication trigger edge of the target bus clock, bit counting is carried out according to the communication time slot, and slot counting and multiframe counting are carried out simultaneously; wherein the slot position count is increased after the bit count is full, and the multiframe count is increased after the slot position count is full;
and controlling the target communication slot matched with the slot position count to transmit the target information in a multi-frame mode with another communication slot position of another programmable logic device through a data bus.
Preferably, the determining the target bus clock and the target bus frame header includes:
and if the target programmable logic device does not have the generating function of generating the bus clock and the bus frame header, determining the received bus clock as the target bus clock, and determining the received bus frame header as the target bus frame header.
Preferably, the determining the target bus clock and the target bus frame header includes:
generating a first bus clock and a first bus frame header;
judging whether the first bus clock and the first bus frame head fail or not; the failure comprises no overturn within a preset period;
if the first bus clock and the first bus frame head are not invalid, determining the first bus clock as the target bus clock, and determining the first bus frame head as the target bus frame head;
and if the first bus clock and/or the first bus frame head fail, receiving a second bus clock and a second bus frame head which are sent by a main programmable logic device and a standby programmable logic device formed by the target programmable logic device, determining the second bus clock as the target bus clock, and determining the second bus frame head as the target bus frame head.
Preferably, the target information includes single board basic information of a single board where the target programmable logic device is located and single board user usage information;
the single board basic information comprises at least one of a single board mandatory state, a single board active/standby state, a single board preparation state and a single board in-place state; the veneer forced state is used for representing whether a veneer has a main/standby state, and the main/standby state is used for representing whether the veneer is a main veneer or a standby veneer; the single board preparation state is used for representing whether the single board is prepared or not; the single board in-place state is used for representing whether the single board is in place or not.
Preferably, the target information includes a frame flag;
and the frame flag is used for representing whether the data bus is overturned.
In a third aspect, the present application provides a communication system applied to a target programmable logic device, including:
the bus determining module is used for determining a target bus clock and a target bus frame header, and the target bus clock and the target bus frame header are generated by a programmable logic device;
a communication time slot determining module, configured to determine a communication time slot of each target communication slot in the target programmable logic device based on the target bus frame header;
the counting module is used for carrying out bit counting according to the communication time slot based on the communication triggering edge of the target bus clock and simultaneously carrying out slot position counting and multiframe counting; wherein the slot position count is increased after the bit count is full, and the multiframe count is increased after the slot position count is full;
and the control module is used for controlling the target communication slot matched with the slot position count to transmit the target information in a multi-frame mode with another communication slot position of another programmable logic device through a data bus.
In a fourth aspect, the present application provides an electronic device applied to a target programmable logic device, including:
a storage component for a programmable logic program;
processing means for implementing the steps of the communication method as described in any one of the above when said programmable logic program is executed.
The communication device comprises a first programmable logic device and a second programmable logic device; the first programmable logic device is provided with a first bus clock sending port, the second programmable logic device is provided with a first bus clock receiving port, and the first programmable logic device transmits a first bus clock to the second programmable logic device through the first bus clock sending port and the first bus clock receiving port; the first programmable logic device is provided with a first bus frame header sending port, the second programmable logic device is provided with a first bus frame header receiving port, and the first programmable logic device transmits a first bus frame header to the second programmable logic device through the first bus frame header sending port and the first bus frame header receiving port; the first programmable logic device is provided with a first communication slot position, the second programmable logic device is provided with a second communication slot position, the first communication slot position and the second communication slot position are connected through a data bus, and the first communication slot position and the second communication slot position carry out time division multiplexing communication based on a target bus clock and a target bus frame header; the target bus clock includes a bus clock determined based on the first bus clock, and the target bus frame header includes a bus frame header determined based on the first bus frame header. In the application, a first bus clock and a first bus frame head are transmitted between a first programmable logic device and a second programmable logic device, and time division multiplexing communication is carried out by means of a target bus clock determined based on the first bus clock, the target bus frame head determined based on the first bus frame head and a data bus. The communication method, the communication system and the electronic equipment solve the corresponding technical problems.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a communication device according to an embodiment of the present application;
fig. 2 is another schematic structural diagram of a communication device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a communication device provided in the present application in practical application;
fig. 4 is a flowchart of a communication method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a communication system according to an embodiment of the present application;
fig. 6 is a schematic diagram of a hardware component structure of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a communication device according to an embodiment of the present disclosure.
The communication device provided by the embodiment of the application can comprise: a first programmable logic device 11, a second programmable logic device 12;
the first programmable logic device 11 is provided with a first bus clock sending port 111, the second programmable logic device 12 is provided with a first bus clock receiving port 121, and the first programmable logic device 11 transmits a first bus clock generated by the first programmable logic device 11 to the second programmable logic device 11 through the first bus clock sending port 111 and the first bus clock receiving port 121;
the first CPLD11 is provided with a first bus frame header sending port 112, the second CPLD12 is provided with a first bus frame header receiving port 122, and the first CPLD11 transmits a first bus frame header generated by itself to the second CPLD12 through the first bus frame header sending port 112 and the first bus frame header receiving port 122;
the first CPLD11 is provided with a first communication slot position 113, the second CPLD12 is provided with a second communication slot position 123, the first communication slot position 113 and the second communication slot position 123 are connected through a data bus 13, and the first communication slot position 113 and the second communication slot position 123 perform time division multiplexing communication based on a target bus clock and a target bus frame header; the target bus clock includes a bus clock determined based on the first bus clock, and the target bus frame header includes a bus frame header determined based on the first bus frame header.
The type of the Programmable Logic device involved in the communication apparatus provided in the present application can be determined according to actual needs, for example, the Programmable Logic device can be a CPLD (Complex Programmable Logic device), an FPGA (Field Programmable Gate Array), etc., since the CPLD, the FPGA, etc. are devices developed from a PAL (Programmable Array Logic) device and a GAL (Generic Array Logic) device, the CPLD, the FPGA, etc. are relatively large in scale, Complex in structure, and belong to a large-scale integrated circuit range, and are digital integrated circuits in which a user constructs Logic functions according to their own needs, and the basic design method is to generate corresponding target files by means of an integrated development software platform and using methods such as schematic diagrams, hardware description languages, etc., and transmit codes to a target chip through a download cable ("in system" Programming), the designed digital system is realized, so that the CPLD, the FPGA and the like can execute logic functions; in addition, in the application, the first programmable logic device may transmit the first bus clock to the second programmable logic device through the first bus clock transmitting port and the first bus clock receiving port, and may transmit the first bus frame header to the second programmable logic device through the first bus frame header transmitting port and the first bus frame header receiving port, and the first communication slot of the first programmable logic device and the second communication slot of the second programmable logic device perform time division multiplexing communication based on the first bus clock and the first bus frame header, so that the first programmable logic device may manage and control the first bus clock and the first bus frame header that communicate with the second programmable logic device, and further, manage and control the communication between the first programmable logic device and the second programmable logic device.
It should be noted that the communication slot may perform information transmission on a rising edge or a falling edge of the bus clock, such as transmitting data on the falling edge of the bus clock, receiving data on the rising edge of the bus clock, and the like; the number of the communication slot positions in the first programmable logic device and the second programmable logic device can be determined according to actual needs, for example, the number of the slot positions in the first communication slot position and the second communication slot position can be 16, and the functions of the communication slot positions can be determined according to actual needs. In addition, because the first communication slot position is connected with the second communication slot position through the data bus, the number of data lines between the first communication slot position and the second communication slot position is small, and the communication device is convenient to deploy, maintain and the like. In addition, Time Division Multiplexing (TDM) uses Time as a parameter for signal Division, so that signals of different paths do not overlap each other on a Time axis, where Time Division Multiplexing is to divide the Time provided for the whole channel to transmit information into a plurality of Time slices (for short, Time slots) and allocate the Time slots to each signal source for use, and a bus frame header in the present application may be used to manage and control the Time slots of the communication slots, for example, a bus frame header defines a frame as 256 Time slots, the number of the communication slots is 16, and each communication slot may use 16 Time slots to transmit data.
The communication device comprises a first programmable logic device and a second programmable logic device; the first programmable logic device is provided with a first bus clock sending port, the second programmable logic device is provided with a first bus clock receiving port, and the first programmable logic device transmits a first bus clock to the second programmable logic device through the first bus clock sending port and the first bus clock receiving port; the first programmable logic device is provided with a first bus frame header sending port, the second programmable logic device is provided with a first bus frame header receiving port, and the first programmable logic device transmits a first bus frame header to the second programmable logic device through the first bus frame header sending port and the first bus frame header receiving port; the first programmable logic device is provided with a first communication slot position, the second programmable logic device is provided with a second communication slot position, the first communication slot position and the second communication slot position are connected through a data bus, and the first communication slot position and the second communication slot position carry out time division multiplexing communication based on a target bus clock and a target bus frame header; the target bus clock includes a bus clock determined based on the first bus clock, and the target bus frame header includes a bus frame header determined based on the first bus frame header. In the application, a first bus clock and a first bus frame head are transmitted between a first programmable logic device and a second programmable logic device, and time division multiplexing communication is performed by means of a target bus clock determined based on the first bus clock, the target bus frame head determined based on the first bus frame head and a data bus.
Referring to fig. 2, fig. 2 is a second structural diagram of a communication device according to an embodiment of the present disclosure.
The communication device provided by the embodiment of the present application may further include a third programmable logic device 14;
the third programmable logic device 14 is provided with a second bus clock transmission port 141, the second programmable logic device 12 is provided with a second bus clock reception port 124, and the third programmable logic device 14 transmits a second bus clock to the second programmable logic device 12 through the second bus clock transmission port 141 and the second bus clock reception port 124;
the third programmable logic device 14 is provided with a second bus frame header sending port 142, the second programmable logic device 12 is provided with a second bus frame header receiving port 125, and the third programmable logic device 14 transmits the second bus frame header to the second programmable logic device 12 through the second bus frame header sending port 142 and the second bus frame header receiving port 125;
the third programmable logic device 14 is provided with a third communication slot 143, the third communication slot 143 is connected with the first communication slot 113 through a data bus, the third communication slot 143 is connected with the second communication slot 123 through a data bus 13, and the third communication slot 143 and the second communication slot 123 perform time division multiplexing communication based on the target bus clock and the target bus frame header;
a bus clock arbitration port 114 and a bus frame header arbitration port 144 are arranged between the first programmable logic device 11 and the third programmable logic device 14, the first programmable logic device 11 and the third programmable logic device 14 select a target bus clock from the first bus clock or the second bus clock through the bus clock arbitration port 114, and the first programmable logic device 11 and the third programmable logic device 14 select a target bus frame header from the first bus frame header or the second bus frame header synchronously through the bus frame header arbitration port 144.
In practical application, because the first programmable logic device transmits the first bus clock and the first bus frame header to the second programmable logic device, the stability of the bus frame header and the bus clock for managing and controlling communication between the first programmable logic device and the second programmable logic device can only be maintained by the first programmable logic device, if the first programmable logic device fails, the first programmable logic device and the second programmable logic device do not have a target bus clock and a target bus frame header for managing and controlling communication, which can cause that the first programmable logic device and the second programmable logic device cannot communicate with each other The second bus clock selects the target bus clock, the first programmable logic device and the third programmable logic device can select the target bus frame head from the first bus frame head and the second bus frame head through the bus frame head arbitration port, thus, the first programmable logic device and the third programmable logic device can form a main-standby relation, under the condition that the clock of the first programmable logic device fails, the third programmable logic device can transmit the second bus clock and the second bus frame head to the first programmable logic device, so that the first programmable logic device can communicate by means of the second bus clock and the second bus frame head, correspondingly, under the condition that the clock of the third programmable logic device fails, the first programmable logic device can transmit the first bus clock and the first bus frame head to the third programmable logic device, so that the third programmable logic device can communicate by means of the first bus clock and the first bus frame head, and the like.
In the communication device provided by the embodiment of the application, the first communication slot position can also be connected with the data bus through the first anti-interference chip, and the second communication slot position can also be connected with the data bus through the second anti-interference chip. Therefore, the information transmitted by the first communication slot position and the second communication slot position can be prevented from being interfered by the outside by the anti-interference chip, and the accuracy of the communication information is ensured.
It should be noted that, in practical applications, each communication slot may be connected to a communication bus through an anti-interference chip, and the like.
In a specific application scenario, the types of the first anti-interference chip and the second anti-interference chip may include a 485 communication chip and the like. At this time, the data input/output state may be switched by the DE pin of the 485 communication chip, for example, the DE pin is set to be a high level for data output, and the DE pin is set to be a low level for data input.
In order to facilitate understanding of the communication device provided by the present application, it is assumed that the communication device provided by the present application is applied to inter-board communication in a switch, and is used for communication between a management board and a function board, and the programmable logic device is a CPLD, where the management board is used for providing management and control functions of a device and a protocol processing function of a data plane, is responsible for processing various communication protocols, serves as a proxy for user operation, manages a system and monitors performance according to an operation instruction of a user, feeds back a device operation condition to the user, and monitors and maintains an interface board, a switch module, a fan, a power supply, and the like; the structure of the communication apparatus provided in the present application may be as shown in fig. 3, and the meaning of each signal in the communication apparatus may be as shown in table 1, and the like.
Table 1 table of meaning of each signal in communication apparatus
Note that the GX _ FP0, GX _ CLK0 signals transmitted by the management board a constitute clock information GX0, and the GX _ FP1, GX _ CLK1 signals transmitted by the management board B constitute clock information GX 1; the GX0 and GX1 form master and standby clock information between the management board a, the management board B and the function board, the principle that each board selects the GX0 and the GX1 can be determined according to actual needs, for example, when the GX0 is valid and the GX1 fails, the clock information of the GX0 bus can be selected, when the GX0 fails and the GX1 is valid, the clock information of the GX1 bus can be selected, when both GX buses fail, the clock information of the GX0 bus is selected by default, and when both GX buses are valid, the clock information of the GX0 bus can be selected. The condition for determining the failure of the GX bus may be determined according to actual needs, for example, it may be set that the failure is defined as no inversion within a preset period, and the failure of the clock line is considered as the failure assuming that the clock line has no inversion within 4 GX _ FP periods, taking the clock line as an example.
Referring to fig. 4, fig. 4 is a flowchart of a communication method according to an embodiment of the present disclosure.
The communication method provided by the embodiment of the application is applied to a target programmable logic device and can comprise the following steps:
step S101: and determining a target bus clock and a target bus frame header, wherein the target bus clock and the target bus frame header are generated by a programmable logic device.
In practical applications, a target programmable logic device is also a programmable logic device that needs to perform information transmission, and according to the communication apparatus shown in fig. 1 of the present application, the target programmable logic device may be a first programmable logic device or a second programmable logic device, that is, when the first programmable logic device or the second programmable logic device needs to perform information transmission, the target programmable logic device becomes a target programmable logic device in the present application. Because the programmable logic devices need to rely on the bus clock and the bus frame header when information is transmitted, the target programmable logic device needs to determine the target bus clock and the target bus frame header firstly, and the target bus clock and the target bus frame header are generated by the programmable logic device, and particularly which programmable logic device generates can be determined according to actual needs.
Step S102: and determining the communication time slot of each target communication slot position in the target programmable logic device based on the target bus frame header.
In practical application, after the target programmable logic device determines the target bus clock and the target bus frame header, the communication time slot of each target communication slot in the target programmable logic device can be determined based on the target bus frame header, so that the target communication slot is controlled to perform data transmission by means of the data bus according to the corresponding communication time slot, and bus collision is avoided.
Step S103: based on the communication trigger edge of the target bus clock, bit counting is carried out according to the communication time slot, and slot position counting and multiframe counting are carried out simultaneously; wherein, a slot position count is added after the bit count is recorded, and a multiframe count is added after the slot position count is recorded.
In practical application, after determining the communication time slot of each target communication slot in the target programmable logic device based on the target bus frame header, the target programmable logic device may perform bit counting according to the communication time slot based on the communication trigger edge of the target bus clock, perform slot counting and multiframe counting simultaneously, increase a slot counting after the bit counting is full, increase a multiframe counting after the slot counting is full, assuming that the number of the target communication slots is 16, each target communication slot occupies 16 slots for information transmission, 16 frames constitute a multiframe, in the counting process, when the bit counting is equal to 16, the slot counting is increased by 1, when the slot counting is equal to 16, the multiframe counting is increased by 1, and at this time, the relationship between each counting and the clock may be as shown in fig. 5; the relationship between bus transfer rates may be as follows: assuming that the bus clock is 50 MHz/32-1.5625 MHz, the frame rate is 50 MHz/32/256-6.13K frames/s, the complex frame rate is 50 MHz/32/256/16-381 complex frames/s, and the user information effective bandwidth is 50 MHz/32/256/16-8-16-48.768 Kbit/s.
Step S104: and controlling the target communication slot matched with the slot position count to transmit target information in a multi-frame mode with another communication slot position of another programmable logic device through a data bus.
In practical application, in a counting process of a target programmable logic device, the information sending timing of a target communication slot may be controlled through slot counting, for example, the target communication slot matched with the slot counting is controlled to transmit target information in a multi-frame form with another communication slot of another programmable logic device through a data bus, for example, if a current slot counting value is 1, the target communication slot matched with 1 and the another communication slot may be controlled to transmit the target information in the multi-frame form, and in the process, the other target communication slots cannot transmit information. And when a single target communication slot transmits target information, the target information may be transmitted to one or more other communication slots at a time, which is not specifically limited herein.
In a specific application scenario, the definition of the communication channel information in the data bus may be as follows:
com _ slot [3:0 ]: 4bit, Com _ channel [127:124 ]; indicating the slot position number of the sent veneer, for example, 1 indicates slot position 1, etc.;
reserve: 3bit, Com _ channel [123:121], reserved and used when transmitting non-definition information;
com _ valid: 1bit, Com _ channel [120], which indicates whether the frame is valid, and can use 1 to indicate that the frame is valid, and 0 to indicate an invalid frame, etc.;
com _ frame [119:0 ]: 120 bits, Com _ channel [119:0], represent transmitted data frames.
In the communication method provided by the application, a target programmable logic device determines a target bus clock and a target bus frame header, and the target bus clock and the target bus frame header are generated by the programmable logic device; determining a communication time slot of each target communication slot position in the target programmable logic device based on the target bus frame header; bit counting is carried out according to a communication time slot based on a communication trigger edge of a target bus clock, and slot counting and multiframe counting are carried out simultaneously; wherein, after the bit count is recorded, a slot position count is added, and after the slot position count is recorded, a multiframe count is added; and controlling the target communication slot matched with the slot position count to transmit target information in a multi-frame mode with another communication slot position of another programmable logic device through a data bus. In the application, the target programmable logic device transmits the target information in a time division multiplexing mode by means of the target bus clock and the target bus frame header, and the target bus clock and the target bus frame header are generated by the programmable logic device, so that software control is not needed in the information transmission process, the participation of a CPU is not needed, and the CPU occupancy rate can be reduced.
In the communication method provided by the embodiment of the application, in the process of determining the target bus clock and the target bus frame header, if the target programmable logic device has the function of generating the bus clock and the bus frame header, a third bus clock and a third bus frame header can be generated, and whether the third bus clock and the third bus frame header fail or not is judged; the failure comprises no overturn within a preset period;
if the third bus clock and the third bus frame header are not invalid, determining the third bus clock as a target bus clock, and determining the third bus frame header as a target bus frame header;
if the third bus clock and/or the third bus frame header fail, receiving a fourth bus clock and a fourth bus frame header sent by a master programmable logic device and a slave programmable logic device which are formed with the target programmable logic device, determining the fourth bus clock as the target bus clock, and determining the fourth bus frame header as the target bus frame header;
if the target programmable logic device does not have the generating function, the received bus clock can be determined as the target bus clock, and the received bus frame header can be determined as the target bus frame header.
For convenience of understanding, it is assumed that the target programmable logic device in the present application is a CPLD on the management board a in the apparatus shown in fig. 3, and at this time, the target programmable logic device has a generating function, so the target programmable logic device may generate a third bus clock and a third bus frame header, that is, a first bus clock and a first bus frame header, and determine whether the first bus clock and the first bus frame header fail, if the first bus clock and the first bus frame header do not fail, determine the first bus clock as the target bus clock, determine the first bus frame header as the target bus frame header, if the first bus clock and/or the first bus frame header fail, receive the primary and secondary programmable logic devices formed with the target programmable logic device, that is, the CPLD on the management board B, and send a fourth bus clock and a fourth bus frame header, that is, the second bus clock and the second bus frame header, and determining the second bus clock as a target bus clock, and determining the second bus frame header as a target bus frame header. Therefore, the target bus clock and the target bus frame header can be determined quickly and effectively through the embodiment.
In the communication method provided in the embodiment of the present application, the target information may include single board basic information and single board user usage information of a single board where the target programmable logic device is located, or the target information includes a frame flag;
the veneer basic information may include a veneer mandatory state, a veneer active/standby state, a veneer preparation state, and a veneer in-place state; the veneer forced state is used for representing whether the veneer has a main/standby state, and the main/standby state of the veneer is used for representing whether the veneer is a main veneer or a standby veneer; the single board preparation state is used for representing whether the single board is ready or not; the veneer in-place state is used for representing whether the veneer is in place or not;
the frame flag is used for representing whether the data bus is overturned.
For ease of understanding, assuming that a single target communication slot occupies 16 slots, the target information may be constructed as follows:
time slot 0: sending the mandatory state of the single board basic information;
time slot 1: sending the main and standby states of the single board basic information;
time slot 2: sending the preparation state of the single board basic information;
time slot 3: sending the in-place state of the single board basic information;
time slots 4-7: sending the multiframe number of the single board user use information;
time slots 8-15: sending single board user using information content user _ info [127:0], using multiframe mode to transmit; user _ info [127] can be sent first and received first;
the definition of the board basic information may be as shown in table 2, and the definition of the user _ info [127] may be as shown in table 3, etc.
Table 2 definition of single board basic information
TABLE 3 definition of user _ info [127]
It should be noted that the single board user usage information may be used to transmit information such as a single board alarm state and a port state, and the single board user information may be transmitted to an internal register of the programmable logic device by the CPU, and then transmitted to a corresponding communication slot by the internal register, and the like, and the process may include the following steps:
CPU sends single board user information to internal register of programmable logic device, the single board user information can include target slot position number and corresponding data;
the programmable logic device judges whether a data latch triggering edge arrives, if so, the single-board user information is latched to an internal register of the programmable logic device, and if not, the programmable logic device returns to the step of judging whether the data latch triggering edge arrives;
the programmable logic device judges whether bus data comprising single board user information and single board basic information is sent to the slot position, if the bus data is sent to the slot position, whether the currently sent bus data is sent completely is judged, if the currently sent bus data is not sent completely, the currently sent bus data is continued, and if the currently sent bus data is sent completely, new bus data is obtained to be sent; and if the bus data is not sent to the slot position, returning to execute the step of judging whether the bus data is sent to the slot position or not, and the like.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a communication system according to an embodiment of the present disclosure.
The communication system provided in the embodiment of the present application, applied to a target programmable logic device, may include:
a bus determining module 101, configured to determine a target bus clock and a target bus frame header, where the target bus clock and the target bus frame header are generated by a programmable logic device;
a communication time slot determining module 102, configured to determine a communication time slot of each target communication slot in the target programmable logic device based on a target bus frame header;
the counting module 103 is used for carrying out bit counting according to a communication time slot based on a communication trigger edge of a target bus clock, and simultaneously carrying out slot position counting and multiframe counting; wherein, after the bit count is recorded, a slot position count is added, and after the slot position count is recorded, a multiframe count is added;
and the control module 104 is used for controlling the target communication slot matched with the slot position count to transmit target information in a multi-frame mode with another communication slot position of another programmable logic device through a data bus.
The communication system provided in the embodiment of the present application is applied to a target programmable logic device, and the bus determining module may include:
the judging unit is used for generating a first bus clock and a first bus frame header if the target programmable logic device has the generating function of generating the bus clock and the bus frame header, and judging whether the first bus clock and the first bus frame header fail or not; failure comprises no turnover within a preset period; if the first bus clock and the first bus frame head are not invalid, determining the first bus clock as a target bus clock, and determining the first bus frame head as a target bus frame head; if the first bus clock and/or the first bus frame head fail, receiving a second bus clock and a second bus frame head which are sent by a programmable logic device which forms a main programmable logic device with a target programmable logic device, determining the second bus clock as the target bus clock, and determining the second bus frame head as the target bus frame head; and if the target programmable logic device does not have the generating function, determining the received bus clock as the target bus clock, and determining the received bus frame header as the target bus frame header.
The communication system provided by the embodiment of the application is applied to a target programmable logic device, and the target information may include single-board basic information and single-board user use information of a single board where the target programmable logic device is located, or the target information includes a frame flag;
the single board basic information comprises a single board mandatory state, a single board active/standby state, a single board preparation state and a single board in-place state; the veneer forced state is used for representing whether the veneer has a main/standby state, and the main/standby state of the veneer is used for representing whether the veneer is a main veneer or a standby veneer; the single board preparation state is used for representing whether the single board is ready or not; the veneer in-place state is used for representing whether the veneer is in place or not;
the frame flag is used for representing whether the data bus is overturned.
Based on the hardware implementation of the program module, and in order to implement the method according to the embodiment of the present invention, an embodiment of the present invention further provides an electronic device, fig. 6 is a schematic diagram of a hardware composition structure of the electronic device according to the embodiment of the present invention, and as shown in fig. 6, the electronic device includes:
a communication interface 1 capable of performing information interaction with other devices such as network devices and the like;
and the processing part 2 is connected with the communication interface 1 to realize information interaction with other equipment, and is used for executing the communication method provided by one or more technical schemes when running a computer program. And the computer program is stored on the storage means 3.
In practice, of course, the various components in the electronic device are coupled together by the bus system 4. It will be appreciated that the bus system 4 is used to enable connection communication between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. For the sake of clarity, however, the various buses are labeled as bus system 4 in fig. 6.
The storage section 3 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic apparatus. Examples of such data include: any programmable logic program for operation on an electronic device.
It will be appreciated that the storage component 3 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The storage component 3 described in the embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The method disclosed in the above-described embodiment of the present invention may be applied to the processing component 2 or implemented by the processing component 2. The processing component 2 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processing unit 2. The processing element 2 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed by the embodiment of the invention can be directly implemented by a hardware decoding processor, or can be implemented by combining hardware and software modules in the decoding processor. The processing unit 2 reads the program in the storage unit 3 and, in conjunction with its hardware, performs the steps of the method described above.
When the processing unit 2 executes the program, it implements the corresponding processes in the methods of the embodiments of the present invention, and for brevity, details are not described here again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus, terminal and method may be implemented in other manners. The above-described device embodiments are only illustrative, for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or in other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.
Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media capable of storing program code.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A communications apparatus, comprising: the first programmable logic device and the second programmable logic device;
the first programmable logic device is provided with a first bus clock sending port, the second programmable logic device is provided with a first bus clock receiving port, and the first programmable logic device transmits a first bus clock generated by the first programmable logic device to the second programmable logic device through the first bus clock sending port and the first bus clock receiving port;
the first programmable logic device is provided with a first bus frame header sending port, the second programmable logic device is provided with a first bus frame header receiving port, and the first programmable logic device transmits a first bus frame header generated by the first programmable logic device to the second programmable logic device through the first bus frame header sending port and the first bus frame header receiving port;
the first programmable logic device is provided with a first communication slot position, the second programmable logic device is provided with a second communication slot position, the first communication slot position and the second communication slot position are connected through a data bus, and the first communication slot position and the second communication slot position carry out time division multiplexing communication based on a target bus clock and a target bus frame header; the target bus clock comprises a bus clock determined based on the first bus clock, and the target bus frame header comprises a bus frame header determined based on the first bus frame header;
the system also comprises a third programmable logic device;
the third programmable logic device is provided with a second bus clock sending port, the second programmable logic device is provided with a second bus clock receiving port, and the third programmable logic device transmits a second bus clock generated by the third programmable logic device to the second programmable logic device through the second bus clock sending port and the second bus clock receiving port;
the third programmable logic device is provided with a second bus frame header sending port, the second programmable logic device is provided with a second bus frame header receiving port, and the third programmable logic device transmits a second bus frame header generated by the third programmable logic device to the second programmable logic device through the second bus frame header sending port and the second bus frame header receiving port;
the third programmable logic device is provided with a third communication slot position, the third communication slot position is connected with the first communication slot position through the data bus, the third communication slot position is connected with the second communication slot position through the data bus, and the third communication slot position and the second communication slot position carry out time division multiplexing communication based on the target bus clock and the target bus frame header;
a bus clock arbitration port and a bus frame header arbitration port are arranged between the first programmable logic device and the third programmable logic device, the first programmable logic device and the third programmable logic device select the target bus clock from the first bus clock and the second bus clock through the bus clock arbitration port, and the first programmable logic device and the third programmable logic device select the target bus frame header from the first bus frame header and the second bus frame header through the bus frame header arbitration port.
2. The communication device of claim 1, wherein the first communication slot is coupled to the data bus via a first anti-jamming chip and the second communication slot is coupled to the data bus via a second anti-jamming chip.
3. The communications device of claim 2, wherein the first anti-jamming chip and the second anti-jamming chip are of the type comprising a 485 communication chip.
4. A communication method is applied to a target programmable logic device and comprises the following steps:
determining a target bus clock and a target bus frame header, wherein the target bus clock and the target bus frame header are generated by a programmable logic device;
determining a communication time slot of each target communication slot position in the target programmable logic device based on the target bus frame header;
based on the communication trigger edge of the target bus clock, bit counting is carried out according to the communication time slot, and slot counting and multiframe counting are carried out simultaneously; wherein the slot position count is increased after the bit count is full, and the multiframe count is increased after the slot position count is full;
controlling the target communication slot matched with the slot count to transmit the target information in a multi-frame mode with another communication slot of another programmable logic device through a data bus;
wherein, the determining the target bus clock and the target bus frame header comprises: generating a first bus clock and a first bus frame header; judging whether the first bus clock and the first bus frame head fail or not; the failure comprises no overturn within a preset period; if the first bus clock and the first bus frame head are not invalid, determining the first bus clock as the target bus clock, and determining the first bus frame head as the target bus frame head; and if the first bus clock and/or the first bus frame head fail, receiving a second bus clock and a second bus frame head which are sent by a main programmable logic device and a standby programmable logic device formed by the target programmable logic device, determining the second bus clock as the target bus clock, and determining the second bus frame head as the target bus frame head.
5. The method of claim 4, wherein determining the target bus clock and the target bus frame header comprises:
and if the target programmable logic device does not have the generating function of generating the bus clock and the bus frame header, determining the received bus clock as the target bus clock, and determining the received bus frame header as the target bus frame header.
6. The method according to claim 4, wherein the target information includes single board basic information and single board user usage information of a single board on which the target programmable logic device is located;
the single board basic information comprises at least one of a single board mandatory state, a single board active/standby state, a single board preparation state and a single board in-place state; the veneer forced state is used for representing whether a veneer has a main/standby state, and the main/standby state is used for representing whether the veneer is a main veneer or a standby veneer; the single board preparation state is used for representing whether the single board is prepared or not; the single board in-place state is used for representing whether the single board is in place or not.
7. The method of claim 4, wherein the target information comprises a frame flag;
and the frame flag is used for representing whether the data bus is overturned.
8. A communication system, applied to a target programmable logic device, comprising:
the bus determining module is used for determining a target bus clock and a target bus frame header, and the target bus clock and the target bus frame header are generated by a programmable logic device;
a communication time slot determining module, configured to determine a communication time slot of each target communication slot in the target programmable logic device based on the target bus frame header;
the counting module is used for carrying out bit counting according to the communication time slot based on the communication triggering edge of the target bus clock and simultaneously carrying out slot position counting and multiframe counting; wherein the slot position count is increased after the bit count is full, and the multiframe count is increased after the slot position count is full;
the control module is used for controlling the target communication slot matched with the slot counting to transmit the target information in a multiframe mode with another communication slot of another programmable logic device through a data bus;
wherein the bus determination module comprises:
the judging unit is used for generating a first bus clock and a first bus frame header; judging whether the first bus clock and the first bus frame head fail or not; the failure comprises no overturn within a preset period; if the first bus clock and the first bus frame head are not invalid, determining the first bus clock as the target bus clock, and determining the first bus frame head as the target bus frame head; and if the first bus clock and/or the first bus frame head fail, receiving a second bus clock and a second bus frame head which are sent by a main programmable logic device and a standby programmable logic device formed by the target programmable logic device, determining the second bus clock as the target bus clock, and determining the second bus frame head as the target bus frame head.
9. An electronic device, applied to a target programmable logic device, comprising:
a storage unit for storing a programmable logic program;
processing means for implementing the steps of the communication method according to any one of claims 4 to 7 when executing the programmable logic program.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791278A (en) * | 2004-12-14 | 2006-06-21 | 华为技术有限公司 | Synchronous optical network and optical transmission network uniform dispatching system and its method |
| CN1909493A (en) * | 2006-08-09 | 2007-02-07 | 华为技术有限公司 | Communication system and method between serial boards |
| CN101005348A (en) * | 2006-01-20 | 2007-07-25 | 中兴通讯股份有限公司 | Method for long line transmission frame head and its realizing device |
| CN101136711A (en) * | 2007-09-29 | 2008-03-05 | 中兴通讯股份有限公司 | Optical terminal service, clock, cross service high integration veneer service smooth switch system of SDH system |
| CN101404609A (en) * | 2008-11-12 | 2009-04-08 | 华为技术有限公司 | Data exchange method, apparatus and system |
| CN101615968A (en) * | 2009-07-27 | 2009-12-30 | 北京华环电子股份有限公司 | A kind of transmission method of time division multiplexing data services and device |
| CN102510355A (en) * | 2011-11-10 | 2012-06-20 | 烽火通信科技股份有限公司 | Method for realizing flexible expenditure data increase and decrease in PTN system |
| CN106789162A (en) * | 2016-11-25 | 2017-05-31 | 瑞斯康达科技发展股份有限公司 | A kind of distributed electrical cross system and its alarm transmission method |
| CN109787703A (en) * | 2019-02-28 | 2019-05-21 | 烽火通信科技股份有限公司 | A kind of modification method of timestamp, clock synchronizing method and system |
| CN110635980A (en) * | 2018-06-21 | 2019-12-31 | 深圳市中航比特通讯技术有限公司 | Controlled shared bus and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6085317A (en) * | 1997-08-15 | 2000-07-04 | Altera Corporation | Reconfigurable computer architecture using programmable logic devices |
| US7007121B1 (en) * | 2002-02-27 | 2006-02-28 | Xilinx, Inc. | Method and apparatus for synchronized buses |
| US8724665B2 (en) * | 2009-07-20 | 2014-05-13 | Synopsys, Inc. | Pseudo-synchronous time division multiplexing |
-
2020
- 2020-11-19 CN CN202011305648.1A patent/CN112422388B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791278A (en) * | 2004-12-14 | 2006-06-21 | 华为技术有限公司 | Synchronous optical network and optical transmission network uniform dispatching system and its method |
| CN101005348A (en) * | 2006-01-20 | 2007-07-25 | 中兴通讯股份有限公司 | Method for long line transmission frame head and its realizing device |
| CN1909493A (en) * | 2006-08-09 | 2007-02-07 | 华为技术有限公司 | Communication system and method between serial boards |
| CN101136711A (en) * | 2007-09-29 | 2008-03-05 | 中兴通讯股份有限公司 | Optical terminal service, clock, cross service high integration veneer service smooth switch system of SDH system |
| CN101404609A (en) * | 2008-11-12 | 2009-04-08 | 华为技术有限公司 | Data exchange method, apparatus and system |
| CN101615968A (en) * | 2009-07-27 | 2009-12-30 | 北京华环电子股份有限公司 | A kind of transmission method of time division multiplexing data services and device |
| CN102510355A (en) * | 2011-11-10 | 2012-06-20 | 烽火通信科技股份有限公司 | Method for realizing flexible expenditure data increase and decrease in PTN system |
| CN106789162A (en) * | 2016-11-25 | 2017-05-31 | 瑞斯康达科技发展股份有限公司 | A kind of distributed electrical cross system and its alarm transmission method |
| CN110635980A (en) * | 2018-06-21 | 2019-12-31 | 深圳市中航比特通讯技术有限公司 | Controlled shared bus and method |
| CN109787703A (en) * | 2019-02-28 | 2019-05-21 | 烽火通信科技股份有限公司 | A kind of modification method of timestamp, clock synchronizing method and system |
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|---|---|
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