CN115148701A - Power semiconductor module packaging structure - Google Patents
Power semiconductor module packaging structure Download PDFInfo
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- CN115148701A CN115148701A CN202210771211.XA CN202210771211A CN115148701A CN 115148701 A CN115148701 A CN 115148701A CN 202210771211 A CN202210771211 A CN 202210771211A CN 115148701 A CN115148701 A CN 115148701A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The invention discloses a power semiconductor module packaging structure. The structure includes: the first heat dissipation plate, the first chip module and the second chip module are arranged on the first heat dissipation plate; the first chip module and the second chip module are symmetrically arranged on two sides of the first heat dissipation plate; the first chip module comprises a first substrate, a first power chip, a second power chip, a first positive power input terminal, a first negative power input terminal and a first phase power output terminal; the second chip module comprises a second substrate, a third power chip, a fourth power chip, a second positive power input terminal, a second negative power input terminal and a second phase power output terminal; the first substrate, the first power chip, the second power chip, the first positive power input terminal, the first negative power output terminal and the first phase power output terminal are respectively and symmetrically arranged with the second substrate, the fourth power chip, the third power chip, the second negative power input terminal, the second positive power output terminal and the second phase power output terminal, so that the commutation paths are completely overlapped.
Description
Technical Field
The embodiment of the invention relates to a semiconductor packaging technology, in particular to a power semiconductor module packaging structure.
Background
Semiconductor power module packaging technology is mainly developed towards small volume and high power. At present, the conventional power module packaging adopts a mode of arranging a plurality of chips in a plane, so that the packaging causes the area of a current conversion loop of a chip circuit to be larger, the stray inductance parameter to be larger, larger voltage and current overshoot is easily caused in the switching process, the device safety is poor, the loss is large, the EMC performance is poor, particularly, the SiC device has hard switching characteristic, more serious voltage overshoot and serious electromagnetic interference problem.
Disclosure of Invention
The invention provides a power semiconductor module packaging structure, which enables commutation paths to be completely overlapped, thereby reducing stray inductance parameters of the power semiconductor module and improving the switching safety of the module.
An embodiment of the present invention provides a power semiconductor module package structure, including:
a first heat dissipation plate; the first heat dissipation plate comprises a first surface and a second surface which are oppositely arranged;
a first chip module; the first chip module is arranged on one side of the first surface of the first heat dissipation plate; the first chip module comprises a first substrate, a first power chip, a second power chip, a first positive power input terminal, a first negative power output terminal and a first phase power output terminal; the first substrate comprises a first electrode part, a second electrode part and a third electrode part; one end of the first electrode part is welded with the first positive power input terminal; one end of the second electrode part is welded with the first negative power input terminal; one end of the third electrode part is welded with the first-phase power output terminal; the first power chip is welded on the first electrode part; the second power chip is welded on the third electrode part; the first power chip is electrically connected with the third electrode part through a binding line; the second power chip is electrically connected with the second electrode block through a binding line;
a second chip module; the second chip module is arranged on one side of the second surface of the first heat dissipation plate; the second chip module comprises a second substrate, a third power chip, a fourth power chip, a second positive power input terminal, a second negative power input terminal and a second phase power output terminal; the second substrate comprises a fourth electrode part, a fifth electrode part and a sixth electrode part; one end of the fourth electrode part is welded with the second positive power input terminal; one end of the fifth electrode part is welded with the second negative power input terminal; one end of the sixth electrode part is welded the second phase power output terminal; the third power chip is welded on the sixth electrode part; the fourth power chip is welded on the fifth electrode part; the third power chip is electrically connected with the fourth electrode part through a binding line; the fourth power chip is electrically connected with the sixth electrode part through a binding line;
wherein the first phase power output terminal is electrically connected to the first phase power output terminal through a load; the third power chip and the second power chip are symmetrically arranged; the fourth power chip and the first power chip are symmetrically arranged.
Optionally, the first positive power input terminal and the second negative power input terminal have different extension lengths;
the second positive power input terminal and the first negative power input terminal have different extension lengths;
the first phase output terminal and the second phase output terminal have different extension lengths.
Optionally, the method further includes: a third substrate, a second heat dissipation plate, a fourth substrate and a third heat dissipation plate;
the third substrate is arranged on one side, away from the first heat dissipation plate, of the first chip module; the second heat dissipation plate is arranged on one side, far away from the first chip module, of the third substrate, and the projection part of the second heat dissipation plate on the first heat radiator covers the first heat dissipation plate;
the fourth substrate is arranged on one side, away from the first heat dissipation plate, of the second chip module; the third heat dissipation plate is arranged on one side, far away from the second chip module, of the fourth substrate; the fourth heat dissipation plate covers the first heat dissipation plate at a projection portion of the first heat sink.
Optionally, the second heat dissipation plate includes a first water-cooled substrate and first heat dissipation pins; the first water-cooling substrate is arranged between the first heat dissipation pin needle and the third substrate;
the third heat dissipation plate comprises a second water-cooling substrate and second heat dissipation pin needles; the second water-cooling base plate is arranged between the second heat dissipation pin needle and the fourth base plate.
Optionally, the method further includes: a packaging layer;
the packaging layer, the second heat dissipation plate and the third heat dissipation plate form a sealed cavity, and sealing materials are filled in the sealed cavity.
Optionally, the first heat dissipation plate includes a first water-cooling plane plate, a heat dissipation cavity, and a second water-cooling plane plate; the heat dissipation cavity is arranged between the first water-cooling plane plate and the second water-cooling plane plate.
Optionally, the first heat dissipation plate includes a heat dissipation metal plate.
Optionally, the first power chip, the second power chip, the third power chip, and the fourth power chip all include a plurality of semiconductor chips connected in parallel.
Optionally, the first substrate further includes a first control signal terminal pad; the first control signal terminal welding spot is electrically connected with the first power chip and the second power chip through binding lines;
the second substrate further comprises a second control signal terminal welding spot; and the second control signal terminal welding spot is electrically connected with the third power chip and the fourth power chip through binding wires.
Optionally, the first substrate and the second substrate are both double-sided copper-clad ceramic substrates; the third substrate and the fourth substrate are both double-sided copper-clad ceramic substrates
In the embodiment of the invention, one end of a first electrode part in a first substrate is welded with a first positive power input terminal, and one end of a second electrode part is welded with a first negative power input terminal; one end of the third electrode part is welded with a first-phase power output terminal; the first power chip is welded on the first electrode part; the second power chip is welded on the third electrode part; the first power chip is electrically connected with the third electrode part through the binding line; the second power chip is electrically connected with the second electrode block through a binding line; a second positive power input terminal is welded at one end of a fourth electrode part in the second substrate; one end of the fifth electrode part is welded with a second negative power input terminal; one end of the sixth electrode part is welded with a second-phase power output terminal; the third power chip is welded on the sixth electrode part; the fourth power chip is welded on the fifth electrode part; the third power chip is electrically connected with the fourth electrode part through the binding line; the fourth power chip is electrically connected with the sixth electrode part through a binding line; simultaneously electrically connecting the first phase power output terminal with the first phase power output terminal through a load; the third power chip and the second power chip are symmetrically arranged; the fourth power chip and the first power chip are symmetrically arranged, so that the packaging structure adopts a completely symmetrical layout wiring structure, switch commutation paths are completely overlapped, stray inductance parameters of the power semiconductor module are reduced, and the switch safety of the module is improved.
Drawings
Fig. 1 is a front plan view and a back plan view of a power semiconductor module package structure according to an embodiment of the invention;
FIG. 2 is a cross-sectional view of a power semiconductor module package along section line AB of FIG. 1;
fig. 3 is a schematic diagram of electrical connections of a power semiconductor module according to an embodiment of the present invention;
FIG. 4 is a top view of a front side and a top view of a package structure of another power semiconductor module according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of the power semiconductor module package along the section line AB of FIG. 4;
fig. 6 is a schematic overall structure diagram of a power semiconductor module package structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a front top view and a back top view of a power semiconductor module package structure according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of a power semiconductor module package along section line AB of FIG. 1; as shown in fig. 1 and 2, the power semiconductor module package structure includes: a first heat dissipation plate 10; the first heat dissipation plate 10 includes a first surface 11 and a second surface 12 that are oppositely disposed; a first chip module 20; the first chip module 20 is disposed on the first surface 11 side of the first heat dissipation plate 10; the first chip module 20 includes a first substrate 21, a first power chip 22, a second power chip 23, a first positive power input terminal 24, a first negative power input terminal 25, and a first phase power output terminal 26; the first substrate 21 includes a first electrode portion 211, a second electrode portion 212, and a third electrode portion 213; one end of the first electrode portion 211 is welded to the first positive power input terminal 24; one end of the second electrode portion 212 is welded to the first negative power input terminal 25; one end of the third electrode part 213 is welded with the first-phase power output terminal 26; the first power chip 22 is soldered on the first electrode portion 211; the second power chip 23 is soldered to the third electrode portion 213; the first power chip 22 is electrically connected to the third electrode portion 213 through the binding line; the second power chip 23 is electrically connected with the second electrode portion 212 through the binding line; optionally, the first substrate 21 is a ceramic substrate with copper coated on both sides; the first substrate 21 further includes a first intermediate ceramic insulating layer 215 and a first copper layer 216; the first intermediate ceramic insulating layer 215 serves to insulate the electrode portions of the first electrode portion 211, the second electrode portion 212, and the third electrode portion 213 from the first heat sink 10, and the first copper skin layer 216 serves to solder the first substrate 21 to the first heat sink 10.
A second chip module 30; the second chip module 30 is disposed on the second surface 12 side of the first heat sink 10; the second chip module 30 includes a second substrate 31, a third power chip 32, a fourth power chip 33, a second positive power input terminal 34, a second negative power input terminal 35, and a second phase power output terminal 36; the second substrate 31 includes a fourth electrode portion 311, a fifth electrode portion 312, and a sixth electrode portion 313; one end of the fourth electrode portion 311 is welded to the second positive power input terminal 34; one end of the fifth electrode part 312 is welded with the second negative power input terminal 35; one end of the sixth electrode portion 313 is welded with the second-phase power output terminal 36; the third power chip 32 is soldered to the sixth electrode portion 313; the fourth power chip 33 is soldered to the fifth electrode portion 312; the third power chip 32 is electrically connected to the fourth electrode portion 311 through a bonding wire; the fourth power chip 33 is electrically connected to the sixth electrode portion 313 through a bonding wire; wherein the first phase power output terminal 26 is electrically connected to the first phase power output terminal 36 through a load; third power chip 32 and second Power chip 23 symmetrically arranging; the fourth power chip 33 and the first power chip 22 are symmetrically arranged, and optionally, the second substrate 31 is a double-sided copper-clad ceramic substrate; the second substrate 31 further comprises a second intermediate ceramic insulating layer 315 and a second copper layer 316; the second intermediate ceramic insulating layer 315 serves to insulate the electrode portions of the third electrode portion 311, the fourth electrode portion 312, and the fifth electrode portion 313 from the first heat sink 10, and the second copper layer 316 serves to solder the second substrate 31 to the first heat sink 10. .
Fig. 3 is an electrical connection schematic diagram of a power semiconductor module according to an embodiment of the present invention, as shown in fig. 3, the power semiconductor module includes four power switching devices Q1, Q2, Q3, and Q4, where the power switching devices Q1, Q2, Q3, and Q4 may be IGBTs or MOSFETs, and when the power semiconductor module outputs power, Q1 and Q2 cannot be turned on simultaneously, and Q3 and Q4 cannot be turned on simultaneously; when Q1 and Q4 are conducted and Q2 and Q3 are closed, the load flows forward current to form a current conversion loop; when Q1 and Q4 are closed and Q2 and Q3 are conducted, the load flows negative current to form another commutation loop, and therefore the four power switching devices Q1-Q4 work alternately to convert direct current into alternating current. As shown in fig. 1 and fig. 2, the physical diagram of the power semiconductor module and the electrical connection diagram of the power semiconductor module are arranged in a one-to-one correspondence, when the first positive power input terminal 24 receives an input direct current positive input current signal, because one end of the first electrode portion 211 is welded with the first positive power input terminal 24, the first power chip 22 is welded on the first electrode portion 211, the first power chip 22 is electrically connected with the third electrode portion 213 through a binding line, one end of the third electrode portion 213 is welded with the first phase power output terminal 26, and the first phase power output terminal 26 is electrically connected with the first phase power output terminal 36 through a load, which means that the direct current positive input current signal is transmitted to the load through the first power chip 22, and the positive input current signal flowing out from the load is transmitted to the second phase power output terminal 36; meanwhile, one end of the sixth electrode part 313 is welded with the second phase power output terminal 36, and the fourth power chip 33 is electrically connected with the sixth electrode part 313 through a binding line; the fourth power chip 33 is soldered on the fifth electrode portion 312; one end of the fifth electrode part 312 is welded with the second negative power input terminal 35; the positive input current signal from the load is transmitted to the second phase power output terminal 36, then to the fourth power chip 33, and finally flows back to the second negative power input terminal 35, so as to form a forward commutation loop.
Similarly, when the second positive power input terminal 34 receives the input dc positive input current signal, one end of the fourth electrode portion 311 is welded to the second positive power input terminal 34; the third power chip 32 is electrically connected to the fourth electrode portion 311 through a bonding wire; the third power chip 32 is soldered to the sixth electrode portion 313; one end of the sixth electrode portion 313 is welded with the second phase power output terminal 36, the second phase power output terminal 36 is electrically connected with the first phase power output terminal 26 through the load, so that a direct-current positive input current signal is transmitted to the load through the third power chip 32, and a positive input current signal flowing out of the load is transmitted to the first phase power output terminal 26; meanwhile, one end of the third electrode part 213 is welded with the first-phase power output terminal 26; the second power chip 23 is soldered to the third electrode portion 213; the second power chip 23 is electrically connected to the second electrode portion 212 through the bonding wire; one end of the second electrode part 212 is welded with the first negative power input terminal 25; thus, a positive input current signal flowing out of the load is transmitted to the first-phase power output terminal 26, then transmitted to the second power chip 23, and finally flows back to the first negative power input terminal 25, so that a negative commutation loop is formed; thus, the third power chip 32 and the second power chip 23 are symmetrically arranged; the fourth power chip 33 and the first power chip 22 are symmetrically arranged, the upper layer and the lower layer adopt a completely symmetrical layout wiring structure, and a path of a positive commutation loop formed by the fourth power chip 33 and the first power chip 22 and a path of another negative commutation loop formed by the third power chip 32 and the second power chip 23 are completely overlapped, so that stray inductance parameters of the power semiconductor module are reduced, and the switching safety of the module is improved.
Optionally, fig. 4 is a front top view and a back top view of another power semiconductor module package structure provided in the embodiment of the present invention; FIG. 5 is a cross-sectional view of the power semiconductor module package along the section line AB of FIG. 4; as shown in fig. 4 and 5, the semiconductor module package structure further includes: a third substrate 40, a second heat dissipation plate 50, a fourth substrate 60, and a third heat dissipation plate 70; the third substrate 40 is disposed on a side of the first chip module 20 away from the first heat dissipation plate 10; the second heat dissipation plate 50 is disposed on a side of the third substrate 40 away from the first chip module 20; the second heat dissipation plate 50 covers the first heat dissipation plate 10 at the projection part of the first heat dissipation plate 10; the fourth substrate 60 is disposed on a side of the second chip module 30 away from the first heat dissipation plate 10; the third heat sink plate 70 is disposed on the fourth substrate 60 at a side away from the second chip module 30. The third heat sink 70 is disposed on the first heat sink 10 the projected portion of (a) covers the first heat dissipation plate 10; wherein, third base plate 40 is two-sided copper clad ceramic substrate, include two-layer copper cortex and the insulating layer between two-layer copper cortex in the third base plate 40, the first surface of third base plate 40 sets up a copper cortex for first power chip 22 of welded fastening and second power chip 23, the second surface of third base plate 40 sets up another copper cortex and is used for can being used for welded fastening second heating panel 50, insulating layer in the third base plate 40 has played the effect of insulating first power chip 22 and second power chip 23 and second heating panel 50 well. The fourth substrate 60 is a double-sided copper-clad ceramic substrate, similarly, the fourth substrate 60 includes two copper layers in the third substrate 40 and an insulating layer between the two copper layers, a copper layer is disposed on the first surface of the fourth substrate 60 for welding and fixing the third power chip 32 and the fourth power chip 33, another copper layer is disposed on the second surface of the fourth substrate 60 for fixedly welding the third heat dissipation plate 70, and the insulating layer in the fourth substrate 60 plays a good role in insulating the third chip 32, the fourth power chip 33 and the third heat dissipation plate 70; in addition, the second heat dissipation plate 50 and the third heat dissipation plate 70 are used for heat dissipation in an upper layer and a lower layer, so that the upper surface and the lower surface of the module can be effectively cooled simultaneously, the heat dissipation effect is good, and the size of the module can be effectively reduced.
Optionally, with continued reference to fig. 5, the structure further includes an encapsulation layer 80; the encapsulating layer 80, the second heat dissipation plate 50 and the third heat dissipation plate 70 form a sealed cavity, and the sealed cavity is filled with a sealant, for example, an encapsulating epoxy resin is filled in the sealed cavity, so as to form a complete power semiconductor module.
Optionally, referring to fig. 4 and 5, the second heat dissipation plate 50 includes a first water-cooled substrate and first heat dissipation pins; the first water-cooling substrate is arranged between the first heat dissipation pin needle and the third substrate 40; the third heat dissipation plate 70 includes a second water-cooled substrate and second heat dissipation pins; the second water-cooled substrate is disposed between the second heat dissipation pin and the fourth substrate 60. The first water-cooling substrate can be used for welding and fixing the third substrate 40; the second water-cooled substrate can be used for welding and fixing the fourth substrate 60, and the first heat dissipation pin and the second heat dissipation pin can increase the contact area with external cooling liquid, so that the heat dissipation efficiency of the whole module can be effectively improved; it is to be understood that the second heat dissipation plate 50 and the third heat dissipation plate 70 may have other structures, and any heat sink having a weldable surface may satisfy the present design, and the structures of the second heat dissipation plate 50 and the third heat dissipation plate 70 are not limited herein.
Alternatively, as shown in fig. 4 and 5, the first heat dissipation plate 10 includes a first water-cooled flat plate, a heat dissipation cavity, and a second water-cooled flat plate; the heat dissipation cavity is arranged between the first water-cooling plane plate and the second water-cooling plane plate. The first water-cooling plane plate and the second water-cooling plane plate are respectively used for fixedly welding the first substrate 21 and the second substrate 31; the heat dissipation cavity is used for increasing the contact area with the cooling liquid and improving the heat dissipation efficiency; it will be appreciated that the first heat spreader plate may be configured in other ways, and any heat sink having a solderable plane will suffice for this design, and the configuration of the first heat spreader plate is not limited herein.
Optionally, as shown in fig. 4, the first heat dissipation plate 10 includes a heat dissipation metal plate, the heat dissipation metal plate may be directly welded on the first substrate 21 and the second substrate 31, and the heat dissipation metal plate may play a role of heat dissipation, and in addition, may also effectively reduce the volume of the module.
Alternatively, fig. 6 is a schematic diagram of an overall structure of a power semiconductor module package structure according to an embodiment of the present invention, and referring to fig. 2 and fig. 6, the first positive power input terminal 24 and the second negative power input terminal 35 have different extending lengths; the second positive power input terminal 25 and the first negative power input terminal 34 have different extension lengths; the first phase output terminal 26 and the second phase output terminal 36 extend differently. Wherein, the first positive power input terminal 24 and the second negative power input terminal 35 are stacked, and the extension length of the second negative power input terminal 35 is greater than that of the first positive power input terminal 24; the second positive power input terminal 25 and the first negative power input terminal 34 are stacked, and the extension length of the first negative power input terminal 34 is longer than that of the second positive power input terminal 25; the first phase output terminal 26 and the second phase output terminal 36 are arranged in a laminated mode, and the extension length of the second phase output terminal 36 is larger than that of the first phase output terminal 26, so that the lower layer second negative power input terminal 35, the first negative power input terminal 34, the second phase output terminal 36, the upper layer first positive power input terminal 24, the second positive power input terminal 25 and the first phase output terminal 26 can be welded with an external copper bar at the same time, and the welding efficiency of the module and the external copper bar is improved.
In addition, the first positive power input terminal 24 and the second negative power input terminal 35 are vertically arranged in the longitudinal direction; the second positive power input terminal 25 and the first negative power input terminal 34 are vertically arranged, and the first phase output terminal 26 and the second phase output terminal 36 are vertically arranged, so that positive and negative currents are completely overlapped, and stray inductance parameters of connection with an external motor and a capacitor are minimized as much as possible.
Optionally, as shown in fig. 1, the first power chip 22, the second power chip 23, the third power chip 32, and the fourth power chip 33 each include a plurality of semiconductor chips connected in parallel. The number of the parallel semiconductor chips of each power chip can be set according to actual power requirements, the multiple semiconductor chips are arranged in parallel, the expandability of power can be improved, and in addition, the semiconductor chips are uniformly arranged to be beneficial to improving the consistency of the switching characteristics of the whole module.
Optionally, as shown in fig. 1, 3 and 4, the first substrate 21 further includes a first control signal terminal pad 27 thereon; the first control signal terminal pad 27 is electrically connected to the first power chip 22 and the second power chip 23 through a bonding wire; second substrate 31 further includes a second control signal terminal pad 37 thereon; the second control signal terminal pad 37 is electrically connected to the third power chip 32 and the fourth power chip 33 through bonding wires.
The first control signal terminal welding spot 27 and the second control signal terminal welding spot 37 can both receive control signals, so that the power device is in an open-close state; in the actual layout, the first control signal terminal pad 27 and the second control signal terminal pad 37 are led out in a row, concentrated on one side, which facilitates the drawing of the control lines.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A power semiconductor module package structure, comprising:
a first heat dissipation plate; the first heat dissipation plate comprises a first surface and a second surface which are oppositely arranged;
a first chip module; the first chip module is arranged on one side of the first surface of the first heat dissipation plate; the first chip module comprises a first substrate, a first power chip, a second power chip, a first positive power input terminal, a first negative power output terminal and a first phase power output terminal; the first substrate comprises a first electrode part, a second electrode part and a third electrode part; one end of the first electrode part is welded with the first positive power input terminal; one end of the second electrode part is welded with the first negative power input terminal; one end of the third electrode part is welded with the first-phase power output terminal; the first power chip is welded on the first electrode part; the second power chip is welded on the third electrode part; the first power chip is electrically connected with the third electrode part through a binding line; the second power chip is electrically connected with the second electrode block through a binding line;
a second chip module; the second chip module is arranged on one side of the second surface of the first heat dissipation plate; the second chip module comprises a second substrate, a third power chip, a fourth power chip, a second positive power input terminal, a second negative power input terminal and a second phase power output terminal; the second substrate comprises a fourth electrode part, a fifth electrode part and a sixth electrode part; one end of the fourth electrode part is welded with the second positive power input terminal; one end of the fifth electrode part is welded with the second negative power input terminal; one end of the sixth electrode part is welded with the second-phase power output terminal; the third power chip is welded on the sixth electrode part; the fourth power chip is welded on the fifth electrode part; the third power chip is electrically connected with the fourth electrode part through a binding line; the fourth power chip is electrically connected with the sixth electrode part through a binding line;
wherein the first phase power output terminal is electrically connected to the first phase power output terminal through a load; the third power chip and the second power chip are symmetrically arranged; the fourth power chip and the first power chip are symmetrically arranged.
2. The power semiconductor module package of claim 1, wherein the first positive power input terminal and the second negative power input terminal have different extended lengths;
the second positive power input terminal and the first negative power input terminal have different extension lengths;
the first phase output terminal and the second phase output terminal have different extension lengths.
3. The power semiconductor module package structure of claim 1, further comprising: a third substrate, a second heat dissipation plate, a fourth substrate and a third heat dissipation plate;
the third substrate is arranged on one side, away from the first heat dissipation plate, of the first chip module; the second heat dissipation plate is arranged on one side, far away from the first chip module, of the third substrate, and the projection part of the second heat dissipation plate on the first heat radiator covers the first heat dissipation plate;
the fourth substrate is arranged on one side, away from the first heat dissipation plate, of the second chip module; the third heat dissipation plate is arranged on one side, far away from the second chip module, of the fourth substrate; the fourth heat dissipation plate covers the first heat dissipation plate at a projection portion of the first heat dissipation plate.
4. The power semiconductor module package structure of claim 3, wherein the second heat spreader plate comprises a first water-cooled substrate and first heat spreader pin; the first water-cooling substrate is arranged between the first heat dissipation pin needle and the third substrate;
the third heat dissipation plate comprises a second water-cooling substrate and second heat dissipation pin needles; the second water-cooling base plate is arranged between the second heat dissipation pin needle and the fourth base plate.
5. The power semiconductor module package structure of claim 3, further comprising: a packaging layer;
the packaging layer, the second heat dissipation plate and the third heat dissipation plate form a sealed cavity, and sealing materials are filled in the sealed cavity.
6. The power semiconductor module package structure of claim 1, wherein the first heat spreader includes a first water-cooled planar board, a heat spreader cavity, and a second water-cooled planar board; the heat dissipation cavity is arranged between the first water-cooling plane plate and the second water-cooling plane plate.
7. The power semiconductor module package structure of claim 1, wherein the first heat sink comprises a heat sink metal plate.
8. The power semiconductor module package structure of claim 1, wherein the first power chip, the second power chip, the third power chip, and the fourth power chip each comprise a plurality of semiconductor chips connected in parallel.
9. The power semiconductor module package of claim 1, further comprising a first control signal terminal pad on the first substrate; the first control signal terminal welding spot is electrically connected with the first power chip and the second power chip through binding lines;
the second substrate also comprises a second control signal terminal welding spot; and the second control signal terminal welding spot is electrically connected with the third power chip and the fourth power chip through binding wires.
10. The power semiconductor module package structure of claim 3, wherein the first substrate and the second substrate are both double-sided copper-clad ceramic substrates;
the third substrate and the fourth substrate are both double-sided copper-clad ceramic substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210771211.XA CN115148701A (en) | 2022-06-30 | 2022-06-30 | Power semiconductor module packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210771211.XA CN115148701A (en) | 2022-06-30 | 2022-06-30 | Power semiconductor module packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115148701A true CN115148701A (en) | 2022-10-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210771211.XA Pending CN115148701A (en) | 2022-06-30 | 2022-06-30 | Power semiconductor module packaging structure |
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| Country | Link |
|---|---|
| CN (1) | CN115148701A (en) |
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- 2022-06-30 CN CN202210771211.XA patent/CN115148701A/en active Pending
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