CN115148682A - Gate driver packaging structure and packaging method - Google Patents

Gate driver packaging structure and packaging method Download PDF

Info

Publication number
CN115148682A
CN115148682A CN202210847723.XA CN202210847723A CN115148682A CN 115148682 A CN115148682 A CN 115148682A CN 202210847723 A CN202210847723 A CN 202210847723A CN 115148682 A CN115148682 A CN 115148682A
Authority
CN
China
Prior art keywords
base island
chip
base
lead
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210847723.XA
Other languages
Chinese (zh)
Inventor
吴贞国
方小飞
徐庆升
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hefei Tongfu Microelectronics Co ltd
Original Assignee
Hefei Tongfu Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hefei Tongfu Microelectronics Co ltd filed Critical Hefei Tongfu Microelectronics Co ltd
Priority to CN202210847723.XA priority Critical patent/CN115148682A/en
Publication of CN115148682A publication Critical patent/CN115148682A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention provides a grid driver packaging structure and a packaging method, wherein the packaging structure comprises a lead unit, a plurality of chips, a plurality of bonding wires and a plastic package body, wherein the lead unit comprises a plurality of base islands arranged at intervals and a plurality of pins which are positioned at the outer sides of the base islands and connected with the base islands; the lead unit also comprises a plurality of artificial feet, each base island corresponds to at least one artificial foot, the first end of each artificial foot is connected with the corresponding base island, and the second end of each artificial foot is in floating connection; the chips are arranged on the corresponding base islands, and the chips and the corresponding pins are electrically connected through bonding wires; the plastic package body wraps the lead unit, the chips and the bonding wires. According to the invention, the artificial feet are arranged on the base island, so that the base island is stabilized, the chip mounting and bonding yield is improved, the deformation risk of the base island is reduced, and the flexibility of product wiring design is improved.

Description

Gate driver packaging structure and packaging method
Technical Field
The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a grid driver packaging structure and a packaging method.
Background
A gate driver is an electronic device that amplifies a weak control signal so that it can drive a high power transistor. Gate drivers tend to need to withstand higher bias voltages. Gate drivers can be divided into two broad categories, non-isolated and isolated. Non-isolated gate drivers have many disadvantages, one of which is operating voltage substantially less than 700V, and cannot be used for high power applications; secondly, interference is easily generated between the high-voltage circuit and the low-voltage circuit, the signal transmission noise is large, and the delay is obvious; and thirdly, a common end is arranged between the high-voltage circuit and the low-voltage circuit, and the overall design of the circuit is relatively complex and inflexible. Generally, in order to overcome the above disadvantages, a separate isolator device and a non-isolated gate driver are required, which occupies a large space. The isolator function and the gate driver function are integrated in a unified package to form an isolated gate driver, so that the integration level of a product can be improved, and the difficulty of circuit design is reduced.
The isolation structure mainly comprises an optical coupling type isolation structure, an inductive isolation structure and a capacitive isolation structure, wherein the capacitive isolation structure has the advantages of high withstand voltage, high transmission rate, low transmission delay, strong anti-electromagnetic interference capability, wide working temperature range and the like. The isolated gate driver adopting the capacitive isolation structure can well meet the application requirements of emerging fields such as electric vehicles, photovoltaic power generation, 5G communication and the like, and has considerable market potential. However, the packaging structure of the existing capacitive isolation type gate driver has many problems. In the processing process, the base island on the lead frame is easy to shake and is not easy to bond, and the packaging yield is low; from the reliability point of view, because the area of the base island is larger, delamination is easy to occur between the plastic package body and the lead frame, and the reliability is invalid; from the device performance, the high voltage isolation characteristics are general and cannot meet the high voltage application.
In view of the above problems, there is a need for a gate driver package structure and a gate driver package method that are reasonable in design and effectively solve the above problems.
Disclosure of Invention
The present invention is directed to at least one of the technical problems of the prior art, and provides a gate driver package structure and a gate driver packaging method.
An aspect of the present invention provides a gate driver package structure, including:
the lead unit comprises a plurality of base islands which are arranged at intervals and a plurality of pins which are positioned on the outer sides of the base islands and connected with the base islands; wherein the content of the first and second substances,
the lead unit also comprises a plurality of artificial feet, each base island corresponds to at least one artificial foot, the first end of each artificial foot is connected with the corresponding base island, and the second end of each artificial foot is in floating connection;
the chips are arranged on the corresponding base islands, and the chips and the corresponding pins are electrically connected through the bonding wires;
and the plastic package body wraps the lead unit, the chips and the bonding wires.
Optionally, the lead unit further includes at least one pressing rib;
the first end of the pressing rib is connected with the base island, and the second end of the pressing rib is arranged in a suspended mode.
Optionally, at least one first through hole is arranged on the base island;
and a second through hole is formed in one end, facing the corresponding base island, of each pin.
Optionally, the back surface of the base island is provided with a non-through indentation.
Optionally, the lead unit further includes a plurality of connecting ribs;
the connecting ribs are respectively arranged on two sides of the lead unit in the width direction; and/or the presence of a gas in the gas,
the lead unit further comprises a plurality of inter-pin middle ribs, and the inter-pin middle ribs are connected between two adjacent pins.
Optionally, the lead unit includes three base islands, which are a first base island, a second base island and a third base island, respectively, where areas of the first base island are larger than areas of the second base island and the third base island;
the second base island and the third base island are arranged in parallel and are arranged opposite to the first base island; and the number of the first and second groups,
the gap distance between the first base island and the third base island ranges from 0.6mm to 1.5mm;
the gap distance between the second base island and the third base island ranges from 0.6mm to 1.5mm.
Optionally, the package structure includes three chips, which are a first chip, a second chip, and a third chip, respectively;
the first chip is fixedly arranged on the first base island, the second chip is fixedly arranged on the second base island, and the third chip is fixedly arranged on the third base island; wherein the content of the first and second substances,
the first chip and the second chip are electrically connected through the bonding wire, and the first chip and the third chip are electrically connected through the bonding wire.
Another aspect of the present invention provides a gate driver packaging method, in which the foregoing packaging structure is packaged, the method including:
forming the lead frame, wherein the lead frame comprises a frame body and a plurality of lead units, the lead units are arranged on the frame body in an array mode, and each lead unit comprises a plurality of base islands arranged at intervals and a plurality of pins located on the outer sides of the base islands and connected with the base islands; wherein, the first and the second end of the pipe are connected with each other,
the lead unit further comprises a plurality of prosthetic feet, each base island corresponds to at least one prosthetic foot, a first end of each prosthetic foot is connected with the corresponding base island, and a second end of each prosthetic foot is connected with the frame main body;
respectively fixedly arranging a plurality of chips on the corresponding base islands;
electrically connecting the chips and the corresponding pins through bonding wires;
forming a plastic package body, wherein the plastic package body wraps the lead frame, the plurality of chips and the plurality of bonding wires;
and cutting the plastic package body and the lead frame to form the gate driver.
Optionally, at least one of the plurality of chips is a control chip, and the rest of the chips are driving chips;
the step of respectively fixedly arranging the plurality of chips on the corresponding base islands comprises:
fixedly arranging the control chip on the corresponding base island and performing pre-curing;
and fixedly arranging the driving chip on the corresponding base island and curing.
Optionally, the pre-curing condition is 145-165 ℃ and the temperature is kept for 15-30 min;
the curing condition is 165-185 ℃ and the constant temperature is 1-1.5 h.
Optionally, when the lead unit includes a pressing rib, the electrically connecting the chips and the corresponding pins through bonding wires includes:
and clamping the pressing ribs by adopting a pressing plate and a heating block so as to bond the control chip with the corresponding driving chip and bond the chip with the corresponding lead.
Optionally, when the lead unit includes inter-pin middle ribs and connecting ribs, the plastic package body and the lead frame are cut to form the gate driver, including:
cutting off the inter-pin middle ribs among the pins;
separating the second end of the prosthetic foot from the frame body;
bending the pins into a preset shape;
separating the tie bars from the frame body to form the gate driver.
The invention relates to a packaging structure and a packaging method of a grid driver, wherein the packaging structure comprises a lead unit, a plurality of chips, a plurality of bonding wires and a plastic package body, wherein the lead unit comprises a plurality of base islands which are arranged at intervals and a plurality of pins which are positioned at the outer sides of the base islands and connected with the base islands; the lead unit also includes a plurality of prosthetic feet, each base island corresponding to at least one prosthetic foot, the first end of the prosthetic foot being connected to the corresponding base island and the second end of the prosthetic foot being floating. By arranging the artificial foot, the artificial foot is connected with the frame main body before the rib cutting and forming process so as to ensure the relative stability of the position of the base island and prevent deformation, shaking and resonance, and the artificial foot is cut off and does not extend out of the plastic package body and change the package appearance in the rib cutting and forming process; bonding process yields can be promoted through setting up the artificial foot, can reduce the risk that the base island takes place to warp in transportation and transportation, has avoided connecting the base island with a plurality of pins for stabilizing the base island to increase effective IO's figure, promoted the flexibility of product wiring design.
Drawings
Fig. 1 is a schematic diagram (top view) illustrating a gate driver package structure according to an embodiment of the invention;
FIG. 2 isbase:Sub>A cross-sectional view of the gate driver package structure of FIG. 1 taken along the direction A-A' according to the present invention;
fig. 3 is a schematic structural diagram (top view) of a lead unit according to another embodiment of the present invention;
fig. 4 is a schematic diagram of a gate driver package structure according to another embodiment of the invention;
FIG. 5 is a cross-sectional view along the direction B-B' of the gate driver package structure of FIG. 4 according to the present invention;
FIG. 6 is a flowchart illustrating a gate driver packaging method according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a package frame according to an embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1 to 5, an aspect of the present invention provides a gate driver package structure 100, where the package structure 100 includes a lead unit (not shown), a plurality of chips 120, a plurality of bonding wires 130, and a molding compound 140. The lead unit includes a plurality of base islands 112 arranged at intervals and a plurality of leads 113 located outside the base islands 112 and connected to the base islands 112. The pins 113 are used to establish electrical connections between the inside and outside of the plastic package body 140, and transmit power and signals. Of course, the number of the pins 113 in this embodiment is not particularly limited, and may be selected according to actual needs.
It should be noted that, since the gate driver adopts a dual-channel design in the present embodiment, as shown in fig. 4, each lead unit includes 3 base islands 112, namely, a first base island 112a, a second base island 112b and a third base island 112c, wherein the area of the first base island 112a is larger than the area of the second base island 112b and the area of the third base island 112c, that is, the area of the first base island 112a is the largest. The second base island 112b and the third base island 112c are arranged in parallel, and are arranged to face the first base island 112 a.
As shown in FIGS. 1 and 4, the lead unit further comprises a plurality of prosthetic feet 114, at least one prosthetic foot 114 is corresponding to each base island 112, the first end of the prosthetic foot 114 is connected with the corresponding base island 112, and the second end of the prosthetic foot is floating, wherein floating means that the second end of the prosthetic foot 114 is connected in an idle mode. Specifically, before the tendon-cutting forming process, the second end of the prosthetic foot 114 is originally connected to the frame body (not shown in the figure) to ensure relative stability at the position of the island, and deformation, shaking and resonance are not likely to occur, during the tendon-cutting forming process, the prosthetic foot 114 is cut off, so that the second end of the prosthetic foot 114 is separated from the frame body (not shown in the figure), the second end of the prosthetic foot 114 does not extend out of the plastic-sealed body 140, and the packaging appearance is not changed, that is, the second end of the prosthetic foot 114 is in a floating state in the plastic-sealed body 140. It should be noted that the number of the prosthetic feet 114 is not specifically required in this embodiment, and may be set according to actual needs.
The chip 120 is disposed on the corresponding base island 112, and the base island 112 mainly functions to support the chip 120, so as to ensure that the chip 120 is relatively stable in position during product packaging, and facilitate processing. The chips 120 and the corresponding leads 113 are electrically connected by bonding wires 130. The I/O (pads) on the chip 120 are electrically connected to the corresponding leads 113 through bonding wires 130 to implement product functions.
The molding body 140 encapsulates the lead unit, the plurality of chips 120, and the plurality of bonding wires 130. In this embodiment, the size of the plastic package body 140 is 10.3mm × 7.5mm × 2.3mm, and the size of the plastic package body 140 is not specifically required in this embodiment and can be selected as needed. The plastic package body 140 can provide better insulation characteristics to meet the isolation requirements of products; the plastic package body 140 can also isolate external dust, pollution or water vapor, etc., so as to provide a good environment for normal operation of the chip 120 and ensure product reliability.
As shown in fig. 1 and fig. 4, in this embodiment, the gate driver package structures are a SOW16 outline-isolated dual-channel gate driver package structure and a SOW14 outline-isolated dual-channel gate driver package structure, respectively, although other outline package structures may be adopted, which is not limited in this embodiment.
Specifically, as shown in fig. 1, in the present embodiment, the lead unit includes 16 pins 113, wherein 8 pins are respectively disposed at both ends in the length direction of the lead unit. As shown in fig. 4, in the present embodiment, the lead unit includes 14 pins 113, wherein 6 pins and 8 pins are respectively disposed at two ends along the length direction of the lead unit.
The gate driver packaging structure of this embodiment, through set up the artificial foot in the lead wire unit, before the eager muscle shaping process, the artificial foot will link to each other with the frame main part to guarantee in the relative stability of island position, difficult emergence is out of shape, is rocked and is resonated. In the process of rib cutting and forming, the artificial foot can be cut off, can not extend out of the plastic package body, and can not change the package appearance; bonding process yields can be promoted through setting up the prosthetic foot, can reduce the risk that the base island takes place to warp in transportation and transportation, has avoided connecting the base island with a plurality of pins for stabilizing the base island to increase effective IO's figure, promoted the flexibility of product wiring design.
Illustratively, as shown in fig. 1, fig. 3 and fig. 4, the lead unit further includes at least one pressing rib 115, a first end of the pressing rib 115 is connected to the base island 112, and a second end of the pressing rib 115 is suspended. That is, the caulking ribs 115 protrude from the base island 112, but are not connected to the frame body 111.
In this embodiment, only one base island 112 is provided with one pressing rib 115, although the number of the pressing ribs 115 is not specifically limited in this embodiment, a plurality of pressing ribs 115 may be provided on one base island 112, or a plurality of base islands 112 may be provided with the pressing ribs 115, which may be selected according to actual needs.
In the above embodiment, in the bonding process, the pressing plate and the heating block clamp the pressing rib 115, so that the base island 112 is prevented from shaking and resonating during the bonding process, and the bonding yield is improved. Meanwhile, the base island 112 is fixed by the clamp conveniently in the lead bonding process through the synergistic effect of the artificial foot 114 and the pressing rib 115, so that bonding failure caused by shaking and resonance of the base island 112 is further reduced, and the packaging yield is improved.
Illustratively, as shown in fig. 1, 3 and 4, at least one first via 116 is disposed on the base island 112. One end of the pin 113 facing the corresponding base island 112 is provided with a second through hole 113a. In this embodiment, two L-shaped first through holes 116 are formed in the first base island 112a, two first through holes 116 are formed in the second base island 112b, which are circular and elliptical, respectively, and one elliptical first through hole 116 is formed in the third base island 112 c. The number, size and shape of the first through holes 116 are not particularly limited in this embodiment, and may be selected according to actual needs.
In the above embodiment, by providing at least one first through hole 116 on the base island 112, the upper and lower portions of the plastic package body 140 are integrated through the first through hole 116 by the first through hole 116, so as to suppress the trend of relative movement between the plastic package body 140 and the pin 113 near the first through hole 116 due to different thermal expansion coefficients, reduce the probability of delamination of the plastic package body at the base island 112, and improve the reliability of the package.
Similarly, as shown in fig. 1, 3 and 4, the second through hole 113a disposed on the lead 113 has a similar function to the first through hole 116, so as to reduce the delamination probability of the plastic package body 140 at the lead 113 and improve the package reliability.
Illustratively, as shown in fig. 3, the back surface of the base island 112 is provided with non-through indentations 117. In the present embodiment, the 3 base islands are each provided with a non-through indentation 117, and the plurality of non-through indentations 117 are arranged in a matrix.
In the above embodiment, the non-through indentations 117 are provided on the back surface of the base island 112, so that the molded body 140 and the back surface of the base island 112 are engaged with each other, thereby reducing the risk of delamination of the molded body 140 on the back surface of the base island 112.
Illustratively, as shown in fig. 1, 3 and 4, the lead unit further includes a plurality of tie bars 118, and the plurality of tie bars 118 are respectively disposed at both sides of the lead unit in the width direction. Specifically, before the rib cutting and forming process, the connecting ribs 118 are connected with the frame body, and after the pins are formed, the connecting ribs 118 on the left side and the right side of the lead unit are punched, so that the packaging structure is separated from the lead frame, and a complete product is obtained. In this embodiment, the lead unit includes 4 connecting ribs 118, and two sides of the lead unit in the width direction are respectively provided with 2 connecting ribs 118. Of course, the number of the connecting ribs 118 is not specifically limited in this embodiment, and can be selected according to actual needs.
In the above embodiment, the plurality of connecting ribs 118 are respectively arranged on the two sides of the lead unit in the width direction, so that after the cutting and molding of the pins 113, the product can still be ensured to be combined with the matrix frame main body, and the subsequent process operation is facilitated.
Illustratively, as shown in fig. 2, the lead unit further includes a plurality of inter-lead ribs 119, and the inter-lead ribs 119 are connected between two adjacent leads 113.
In this embodiment, an inter-lead middle rib 129 is connected between each two adjacent leads 113, that is, the plurality of inter-lead middle ribs 119 connect the plurality of leads 113. The inter-pin ribs 119 may be provided to increase stability between the pins 113.
Illustratively, the surface of the lead element is roughened. That is, the surfaces of the base island 112, the leads 113, the prosthetic foot 114, the press-fit rib 115, and the connecting rib 118 are roughened. Specifically, the surface of the lead unit may be roughened by a brown oxidation method, a microetching method, or other methods, and this embodiment is not limited in particular.
In the above embodiment, the roughened surface of the lead unit can enable the plastic package body 140 and the surface of the lead unit to be engaged with each other, so as to increase the friction coefficient therebetween, reduce the probability of delamination caused by thermal stress, and improve the reliability of the product.
According to the invention, a series of measures such as integrating the pin 113 and the first through hole 116 on the base island 112, arranging the non-through indentation 117 on the back surface of the base island 112, roughening the surface of the lead unit and the like are taken, so that the associativity of the plastic package body 140 and the lead unit is increased, the layering probability is reduced, and the product reliability can reach MSL1.
Illustratively, as shown in fig. 4, the gap distance between the first base island 112a and the third base island 112c ranges from 0.6mm to 1.5mm. It is further preferable that the gap distance between the first base island 112a and the third base island 112c is 0.75mm to satisfy the requirement of the enhanced isolation between chips.
The gap distance between the second base island 112b and the third base island 112c ranges from 0.6mm to 1.5mm. It is further preferable that the gap distance between the second base island 112b and the third base island 112c is 0.65mm to satisfy the functional isolation requirement between chips.
In the above embodiment, in a limited package size, a sufficient gap width between the islands is reserved, and thus the requirement of functional isolation between two driving chips can be met, and the requirement of enhanced isolation voltage resistance between a control chip and a driving chip can also be met.
Illustratively, as shown in fig. 4 and 5, the package structure includes three chips 120, namely a first chip 121, a second chip 122 and a third chip 123. The first chip 121 is fixedly disposed on the first base island 112a, the second chip 122 is fixedly disposed on the second base island 112b, and the third chip 123 is fixedly disposed on the third base island 112 c. The first chip 121 and the second chip 122 are electrically connected by a bonding wire 130, and the first chip 121 and the third chip 123 are electrically connected by the bonding wire 130.
As shown in fig. 4 and 5, in this embodiment, the first chip 121 is a control chip, and the second chip 122 and the third chip 123 are both driving chips. The first chip 121 (control chip) is fixed on the first base island 112a by an adhesive layer 150, and the second chip 122 (driving chip) and the third chip 123 (driving chip) are fixed on the second base island 112b and the third base island 112c, respectively.
It should be noted that, as shown in fig. 2 and fig. 5, the material of the adhesion layer 150 may be a conductive silver paste or a conductive DAF, and is used to fix the chip 120 on the base island 112 and form an electrical connection.
Each chip comprises an isolation capacitor structure. As shown in fig. 1 and 4, the isolation capacitor of the first chip 121 (control chip) is connected in series with the isolation capacitors of the second chip 122 (driver chip) and the third chip 123 (driver chip) through the bonding wires 130, respectively, to form an enhanced isolation structure, which has a high requirement on withstand voltage, so that the gaps between the first base island 112a and the second and third base islands 112b and 112c are large. There is no electrical connection between the second chip 122 and the third chip 123, and they work independently, and need to be functionally isolated. Functional isolation between the second chip 122 and the third chip 123 is provided by the molding 140 between the second base island 112b and the third base island 112 c.
The invention reserves enough gap width between the base islands in the limited packaging size and can ensure functional isolation and enhanced isolation between chips. The packaging structure can meet the packaging requirements of an isolated dual-channel gate driver, wherein the isolation voltage is greater than 5700V, the repeatable withstand voltage peak is greater than 1414V, the bearable surge voltage peak is greater than 6250V, the maximum transient withstand voltage is greater than 8000V, and the peak current is greater than or equal to 6A.
As shown in fig. 6, another aspect of the present invention provides a packaging method S100 for a gate driver, where the packaging structure 100 is packaged by the packaging method S100, and the packaging method S100 includes:
s110, forming the lead frame, wherein the lead frame comprises a frame body and a plurality of lead units, the lead units are arranged on the frame body in an array mode, and each lead unit comprises a plurality of base islands arranged at intervals and a plurality of pins which are positioned on the outer sides of the base islands and connected with the base islands; wherein the content of the first and second substances,
the lead unit further comprises a plurality of prosthetic feet, each base island corresponds to at least one prosthetic foot, a first end of the prosthetic foot is connected with the corresponding base island, and a second end of the prosthetic foot is connected with the frame body.
Specifically, as shown in fig. 7, a plurality of rows of lead frames 110 in which lead elements are arranged in a matrix are formed on a copper alloy frame base material by an etching process. As shown in fig. 1 and 3, the lead frame 110 includes a frame body 111 and a plurality of lead units (not shown), the plurality of lead units are arranged on the frame body 111 in an array, and each lead unit includes a plurality of base islands 112 arranged at intervals and a plurality of leads 113 located outside the base islands 112 and connected to the base islands 112. Wherein the lead unit further comprises a plurality of prosthetic feet 114, at least one prosthetic foot 114 per base island 112, a first end of the prosthetic foot 114 connected to the corresponding base island 112, and a second end of the prosthetic foot 114 connected to the frame body 111.
In the embodiment, the length of the lead frame is 238mm-300mm, the width is 70mm-100mm, the thickness is 0.152mm-0.254mm, and 84-144 lead units can be formed. The matrix multi-row lead frame is used for improving the packaging processing efficiency. The surface of the lead frame needs to be roughened, and the treatment method can be a brown oxidation method or a microetching method. Silver plating treatment is needed in the welding wire area, so that the phenomenon that the bonding process cannot be finished due to oxidation of the copper alloy frame in the bonding process is avoided. Preferably, in order to further improve the product reliability, the surface of the lead frame is entirely plated with a Ni/Pd/Au plating layer without any silver plating. The Ni/Pd/Au plating layer has higher cost, but the product reliability is excellent.
And S120, respectively fixing and arranging a plurality of chips on the corresponding base islands.
Specifically, at least one of the plurality of chips 120 is a control chip, and the rest of the chips are driving chips.
Wherein, the fixing of the plurality of chips 120 on the corresponding base islands 112 respectively includes:
as shown in fig. 4 and 5, the control chip is fixedly disposed on the corresponding base island 112 and is pre-cured. In this embodiment, the first chip 121 is attached to the first base island 112a by the adhesive layer 150, and then pre-cured under 145 to 165 ℃ for 15 to 30min.
As shown in fig. 4 and 5, the driving chips are fixedly disposed on the corresponding base islands 112 and cured. In this embodiment, the second chip 122 and the third chip 123 are respectively attached to the second base island 112b and the third base island 112b through the adhesive layer 150, and then cured under the conditions of 165 to 185 ℃ and a constant temperature for 1 to 1.5 hours.
When the control chip is mounted, the control chip is pre-cured, so that the control chip can be prevented from being displaced or falling off in the process of mounting the driving chip, and the product quality and the packaging yield are improved.
S130, electrically connecting the chips and the corresponding pins through bonding wires.
For example, when the lead unit includes the pressing rib 115, the chips 120 and the corresponding leads 113 are electrically connected by the bonding wires 130, which includes:
the pressing ribs 115 are clamped by using a pressing plate and a heating block to bond the control chip with the corresponding driving chip and bond the chip 120 with the corresponding lead 113, respectively.
Specifically, as shown in fig. 2 and 5, the control chip and the driving chip are connected by thermosonic wire bonding using a bonding wire 130 (made of gold, copper, silver alloy, or the like). In the present embodiment, the first chip 121 and the second chip 122 are connected by the bonding wire 130, and the first chip 121 and the third chip 123 are connected by the bonding wire 130.
The process of forming the connecting line between the control chip and the driving chip is to bond 1 metal ball on a chip bonding pad through a ball-planting process, then carry out normal lead bonding, bond two welding points on the metal ball, and avoid the chip damage caused by the bonding of the two welding points. And repeating the processes according to the product design to complete the connection of the control chip and the driving chip. Due to the existence of the isolation capacitor structure, a bonding wire connected between the control chip and the driving chip cannot be grounded, the quality of a welding spot cannot be monitored by a conventional electrical detection method in the bonding process, and the quality of the welding spot needs to be monitored on line by an optical detection method.
The bond wires 130 are used to connect the pads on the chip 120 and the corresponding leads 113 by thermosonic wire bonding. The bonding temperature is 180-220 ℃, the ultrasonic power is 120-350 mW, the bonding time is 8-54 ms, and the bonding pressure is 0.078-0.294N. These bond wires 130 can be grounded and product quality can be monitored during bonding using conventional electrical detection methods.
S140, forming a plastic package body, wherein the plastic package body wraps the lead frame, the chips and the bonding wires.
Specifically, the lead frame after wire bonding is placed in a plastic package mold, and 2 lead frames can be placed at a time. The plastic package body 140 is formed by injection molding. In the injection molding process, the mold temperature is 165-185 ℃, the mold closing pressure is 1275-1472 kN, the injection molding pressure is 12.8-23.5 kN, and the forming time is 80-100 s. After injection molding, the molding compound needs to be cured. The curing temperature of the plastic packaging material is 150-180 ℃, and the curing time of the plastic packaging material is 4-8 hours.
S150, cutting the plastic package body and the lead frame to form the gate driver.
Illustratively, when the lead unit includes the inter-lead middle rib 119 and the connecting rib 118, the plastic package body 140 and the lead frame 110 are cut to form the gate driver, including:
and (3) sequentially performing pin rib cutting, pin bending and device separation by using a stamping method. The lead cutting rib cuts the inter-lead rib 119 of the lead frame 110, which fixes the lead 113. The product after the rib cutting will bend the pins 113 into a preset shape in a special forming die. After the leads 113 are formed, the connecting ribs 118 on the left and right sides of the lead unit are punched, so that the gate driver is separated from the lead frame 110, and a complete product is obtained.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (12)

1. A gate driver package structure, comprising:
the lead unit comprises a plurality of base islands which are arranged at intervals and a plurality of pins which are positioned at the outer sides of the base islands and connected with the base islands; wherein, the first and the second end of the pipe are connected with each other,
the lead unit also comprises a plurality of artificial feet, each base island corresponds to at least one artificial foot, the first end of each artificial foot is connected with the corresponding base island, and the second end of each artificial foot is in floating connection;
the chips are arranged on the corresponding base islands, and the chips and the corresponding pins are electrically connected through the bonding wires;
and the plastic package body wraps the lead unit, the chips and the bonding wires.
2. The package structure of claim 1, wherein the lead element further comprises at least one stitching rib;
the first end of the pressing rib is connected with the base island, and the second end of the pressing rib is arranged in a suspended mode.
3. The package structure according to claim 1, wherein the base island is provided with at least one first via;
and a second through hole is formed in one end, facing the corresponding base island, of each pin.
4. The package structure of claim 1, wherein a backside of the base island is provided with non-through indentations.
5. The package structure according to any one of claims 1 to 4, wherein the lead unit further comprises a plurality of tie bars;
the connecting ribs are respectively arranged on two sides of the width direction of the lead unit; and/or the presence of a gas in the gas,
the lead unit further comprises a plurality of inter-pin middle ribs, and the inter-pin middle ribs are connected between two adjacent pins.
6. The package structure according to any one of claims 1 to 4, wherein the lead unit includes three base islands, namely a first base island, a second base island and a third base island, wherein the area of the first base island is larger than the area of the second base island and the area of the third base island;
the second base island and the third base island are arranged in parallel and are arranged opposite to the first base island; and the number of the first and second groups,
the gap distance between the first base island and the third base island ranges from 0.6mm to 1.5mm;
the gap distance between the second base island and the third base island ranges from 0.6mm to 1.5mm.
7. The package structure according to claim 6, wherein the package structure comprises three chips, a first chip, a second chip and a third chip;
the first chip is fixedly arranged on the first base island, the second chip is fixedly arranged on the second base island, and the third chip is fixedly arranged on the third base island; wherein the content of the first and second substances,
the first chip is electrically connected with the second chip through the bonding wire, and the first chip is electrically connected with the third chip through the bonding wire.
8. A gate driver packaging method, with which the packaging structure of any one of claims 1 to 7 is packaged, the method comprising:
forming a lead frame, wherein the lead frame comprises a frame body and a plurality of lead units, the lead units are arranged on the frame body in an array manner, and each lead unit comprises a plurality of base islands arranged at intervals and a plurality of pins which are positioned outside the base islands and connected with the base islands; wherein, the first and the second end of the pipe are connected with each other,
the lead unit further comprises a plurality of prosthetic feet, each base island corresponds to at least one prosthetic foot, a first end of each prosthetic foot is connected with the corresponding base island, and a second end of each prosthetic foot is connected with the frame main body;
respectively fixedly arranging a plurality of chips on the corresponding base islands;
electrically connecting the chips and the corresponding pins through bonding wires;
forming a plastic package body, wherein the plastic package body wraps the lead unit, the chips and the bonding wires;
and cutting the plastic package body and the lead frame to form the gate driver.
9. The packaging method according to claim 8, wherein at least one of the plurality of chips is a control chip, and the rest of the chips are driving chips;
the fixing of the plurality of chips on the corresponding base islands respectively includes:
fixedly arranging the control chip on the corresponding base island and performing pre-curing;
and fixedly arranging the driving chip on the corresponding base island and curing.
10. The encapsulation method according to claim 9, wherein the pre-curing condition is 145-165 ℃ and the heat preservation is 15-30 min;
the curing condition is 165-185 ℃ and the constant temperature is 1-1.5 h.
11. The packaging method according to claim 9, wherein when the lead unit includes a stitching rib, the electrically connecting the chips and the corresponding leads by bonding wires comprises:
and clamping the pressing ribs by adopting a pressing plate and a heating block so as to bond the control chip with the corresponding driving chip and bond the chip with the corresponding lead.
12. The packaging method according to any one of claims 8 to 11, wherein when the lead unit includes inter-lead studs and tie bars, the cutting the plastic package body and the lead frame to form the gate driver includes:
cutting off the inter-pin middle ribs among the pins;
separating the second end of the prosthetic foot from the frame body;
bending the pins into a preset shape;
separating the connecting rib from the frame body to form the gate driver.
CN202210847723.XA 2022-07-19 2022-07-19 Gate driver packaging structure and packaging method Pending CN115148682A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210847723.XA CN115148682A (en) 2022-07-19 2022-07-19 Gate driver packaging structure and packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210847723.XA CN115148682A (en) 2022-07-19 2022-07-19 Gate driver packaging structure and packaging method

Publications (1)

Publication Number Publication Date
CN115148682A true CN115148682A (en) 2022-10-04

Family

ID=83412638

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210847723.XA Pending CN115148682A (en) 2022-07-19 2022-07-19 Gate driver packaging structure and packaging method

Country Status (1)

Country Link
CN (1) CN115148682A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116373209A (en) * 2023-06-05 2023-07-04 宁波中车时代传感技术有限公司 Manufacturing method of plastic package current detection device and plastic package current detection device
CN117038620A (en) * 2023-07-20 2023-11-10 上海纳矽微电子有限公司 Package structure of lead frame and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116373209A (en) * 2023-06-05 2023-07-04 宁波中车时代传感技术有限公司 Manufacturing method of plastic package current detection device and plastic package current detection device
CN117038620A (en) * 2023-07-20 2023-11-10 上海纳矽微电子有限公司 Package structure of lead frame and manufacturing method thereof
CN117038620B (en) * 2023-07-20 2024-05-03 上海纳矽微电子有限公司 Package structure of lead frame and manufacturing method thereof

Similar Documents

Publication Publication Date Title
CN115148682A (en) Gate driver packaging structure and packaging method
US6703696B2 (en) Semiconductor package
US6812554B2 (en) Semiconductor device and a method of manufacturing the same
JP5078930B2 (en) Semiconductor device
EP2963684A1 (en) Power semiconductor device
US9230891B2 (en) Semiconductor device
CN102420217A (en) Multi-chip semiconductor packages and assembly thereof
JP2000223634A (en) Semiconductor device
KR20050065340A (en) A method of manufacturing a semiconductor device
KR101249745B1 (en) Clip for semiconductor package, semiconductor package using the same amd method for fabricating the package
CN105981170A (en) Dc-dc converter having terminals of semiconductor chips
WO2006074312A2 (en) Dual flat non-leaded semiconductor package
US20230327350A1 (en) Transfer molded power modules and methods of manufacture
CN115172319A (en) Isolated transceiver packaging structure and packaging method
WO2018090470A1 (en) Intelligent power module and manufacturing method thereof
CN108110459B (en) High-power IPM module terminal connection structure
JP2012054319A (en) Lead frame, semiconductor device and manufacturing method of the same
CN217588921U (en) Lead frame for packaging grid driver
JP4277168B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP4450800B2 (en) Manufacturing method of semiconductor device
US7005728B1 (en) Lead configuration for inline packages
CN115241149A (en) Packaging structure and packaging method of capacitive digital isolator
CN115579346B (en) Connection structure, packaging structure and manufacturing process of power module
CN219303658U (en) TOLL lead frame structure and packaging element
CN215069938U (en) Semiconductor packaging structure for improving plastic package air hole

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination