CN115102540A

CN115102540A - Clock generation circuit based on phase-locked loop synchronous external clock

Info

Publication number: CN115102540A
Application number: CN202210666782.7A
Authority: CN
Inventors: 王卓; 熊进; 邝建军; 毛艺澄; 明鑫; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-06-14
Filing date: 2022-06-14
Publication date: 2022-09-23

Abstract

The invention belongs to the technical field of power supply management, and particularly relates to a clock generation circuit based on a phase-locked loop synchronous external clock. The invention combines the characteristics of a phase-locked loop, a square wave generating circuit and a digital frequency division phase splitting, can synchronize an off-chip clock, can output clock voltage signals with various duty ratios and phase differences, and can be suitable for a power supply chip adopting a multiphase interleaving control technology. In addition, the phase-locked loop has an initialization function, so that the problem that the time consumption of a synchronous off-chip clock is too long when the phase-locked loop is powered on is avoided, the 6-time clock frequency square wave generating circuit effectively utilizes the high-speed low-delay characteristic of the phase inverter to ensure that the rising and falling delay is not too large in the work of a plurality of megahertz frequency square waves, and meanwhile, the 6-time clock frequency 6 times of the off-chip clock is subjected to frequency division and phase splitting to output clock signals with various duty ratios and phase differences, so that the phase-locked loop is suitable for the control technology of various power management chips at present.

Description

Clock generation circuit based on phase-locked loop synchronous external clock

Technical Field

The invention belongs to the technical field of power supply management, and particularly relates to a clock generation circuit based on a phase-locked loop synchronous external clock.

Background

In the field of power management technology, a common chip control technology needs to have an internal clock for providing a clock reference for a ramp generation circuit or for generating a logic clock for turning on a power tube, and therefore, a power management chip needs to have at least one clock generation circuit for providing the internal clock for the chip. In addition, with the development of technology, chip power density and the like, the multiphase interleaving control technology is more and more applied to the control of power chips. For the multiphase interleaving control power management technology, the clock of the chip is required to have clock signals with different phase differences according to the number of phases, for example, the two-phase control is performed, and the phase difference between the clocks of the two phases is 180 degrees, so that the multiphase interleaving control can only realize the advantages of minimizing output voltage ripples, reducing passive power devices and the like. Therefore, the clock generation circuit needs to be able to generate a clock having a phase difference from the initial phase in addition to the clock of the initial phase. The multiphase interleaving control technology not only realizes a plurality of phase control in one chip, but also realizes the multiphase interleaving control technology by connecting a plurality of chips in parallel, so that a clock in the chip needs to have the capacity of synchronizing with an off-chip clock, and the initial phase of the clock connected in parallel and another chip can have a determined phase difference.

Disclosure of Invention

Aiming at the design requirements of the clock generating circuit in the multiphase interleaving control power management chip, the invention provides the phase-locked loop clock generating circuit which synchronizes an off-chip clock and has various phase clock outputs. When no off-chip clock is input, the invention can generate a clock with fixed frequency by a square wave generating circuit, and after the clock is input outside the chip, the invention synchronizes the off-chip clock by a phase-locked loop. Besides, the invention can generate other clock signals with various duty ratios and phase differences for the chips of the multiphase interleaving control technology.

The technical scheme of the invention is as follows:

a clock generation circuit based on a phase-locked loop synchronous external clock is characterized by comprising a phase identification and charge pump module, a clock frequency generation module and a frequency division and phase splitting module;

the phase-identifying charge pump module comprises a first NAND gate, a second NAND gate, a third NAND gate, a first phase inverter, a second phase inverter, a third phase inverter, a first D trigger, a second D trigger, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS (P-channel metal oxide semiconductor) tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a first current source, a first resistor, a first capacitor and a second capacitor; one input end of the first NAND gate is connected with the internal initial phase clock, the other input end of the first NAND gate is connected with the starting signal, and the output end of the first NAND gate is connected with the input end of the first inverter; one input end of the second NAND gate is connected with an external clock, the other input end of the second NAND gate is connected with a starting signal, and the output end of the second NAND gate is connected with the input end of the second inverter; the clock signal of the first D trigger is connected with the output end of the second inverter, and the R end of the first D trigger is connected with the output end of the third inverter; the clock signal of the second D trigger is connected with the output end of the second inverter, and the R end of the second D trigger is connected with the output end of the third inverter; the input end of the third inverter is connected with the output end of the third NAND gate, one input end of the third NAND gate is connected with the Q output end of the first D flip-flop, and the other input end of the third NAND gate is connected with the Q output end of the second D flip-flop; the source electrode of the first PMOS tube is connected with the power supply, the grid electrode of the first PMOS tube is interconnected with the drain electrode of the first PMOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube and the output end of the first current source, and the source electrode of the second NMOS tube and the source electrode of the first NMOS tube are grounded; the source electrode of the second PMOS tube is connected with a power supply, and the grid electrode of the second PMOS tube is connected with the Q non-output end of the first D trigger; the source electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the seventh NMOS tube is connected with the source electrode of the eighth NMOS tube, and the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube are connected with the starting signal; the drain electrode of the fourth NMOS tube is connected with the source electrode of the seventh NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the output end of the first current source; the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the Q output end of the second D trigger, and the source electrode of the third NMOS tube is grounded; the source electrode of the fourth PMOS tube is connected with the power supply, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with the starting signal; the drain electrode and the grid electrode of the sixth NMOS tube are connected with the drain electrode of the sixth PMOS tube, the drain electrode and the grid electrode of the fifth NMOS tube are connected with the source electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube is grounded; the source electrode of the eighth NOMOS transistor, the drain electrode of the seventh NMOS transistor, the drain electrode of the fifth PMOS transistor and the source electrode of the sixth PMOS transistor are connected with one end of a first resistor and one end of a first capacitor to serve as the output end of the phase-identifying and charge pump module, the other end of the first resistor is grounded after passing through a second capacitor, and the other end of the first capacitor is grounded;

the clock frequency generation module comprises a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a second current source, a second resistor, a third resistor and a third capacitor; the grid electrode of the seventh PMOS tube is connected with the output end of the phase detection and charge pump module, the source electrode of the seventh PMOS tube is connected with the drain electrode of the twelfth PMOS tube and the source electrode of the eighth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the grid electrode and the drain electrode of the thirteenth NMOS tube and the grid electrode of the fourteenth NMOS tube; the source electrode of the thirteenth NMOS tube and the source electrode of the fourteenth NMOS tube are grounded; a source electrode of the twelfth PMOS tube is connected with a drain electrode of the eleventh PMOS tube, and a grid electrode of the twelfth PMOS tube is connected with a grid electrode of the eleventh PMOS tube, a grid electrode of the ninth PMOS tube, a grid electrode and a drain electrode of the tenth PMOS tube, a grid electrode of the thirteenth PMOS tube, a grid electrode of the fourteenth PMOS tube and a drain electrode of the eleventh NMOS tube; the source electrode of the ninth PMOS tube is connected with the power supply, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the tenth PMOS tube; the grid electrode of the eleventh NMOS tube is connected with the grid electrode and the drain electrode of the ninth NMOS tube, the output end of the current source, the grid electrode of the tenth NMOS tube and the grid electrode of the twelfth NMOS tube; the drain electrode of the tenth NMOS tube is connected with the source electrode of the ninth NMOS tube, and the source electrode of the tenth NMOS tube is grounded; the drain electrode of the twelfth NMOS tube is connected with the source electrode of the eleventh NMOS tube, and the source electrode of the twelfth NMOS tube is grounded; the grid electrode of the eighth PMOS tube is connected with the reference voltage, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, the drain electrode of the fourteenth NMOS tube, the grid electrode of the fifteenth NMOS tube, the grid electrode of the nineteenth NMOS tube and the grid electrode of the twentieth NMOS tube; the source electrode of the fourteenth NMOS tube is grounded; the source electrode of the fourteenth PMOS tube is connected with the drain electrode of the thirteenth PMOS tube; the drain electrode of the sixteenth NMOS tube is connected with the source electrode of the fifteenth NMOS tube, and the source electrode of the sixteenth NMOS tube is grounded; a source electrode of the fifteenth PMOS tube is connected with a power supply, a grid electrode of the fifteenth PMOS tube is connected with a grid electrode and a drain electrode of the sixteenth PMOS tube, a grid electrode of the seventeenth PMOS tube, a grid electrode of the eighteenth PMOS tube and a drain electrode of the seventeenth NMOS tube, and a drain electrode of the fifteenth PMOS tube is connected with a source electrode of the sixteenth PMOS tube; the drain electrode of the eighteenth NMOS tube is connected with the source electrode of the seventeenth NMOS tube, and the source electrode of the eighteenth NMOS tube is grounded; a source electrode of the eighteenth PMOS tube is connected with a drain electrode of the seventeenth PMOS tube, and a drain electrode of the eighteenth PMOS tube is connected with a drain electrode of the twenty-fourth NMOS tube, a source electrode of the twentieth PMOS tube and a source electrode of the twenty-third NMOS tube; the source electrode of the nineteenth PMOS tube is connected with the power supply, the grid electrode of the nineteenth PMOS tube is connected with the output end of the sixth phase inverter, and the drain electrode of the nineteenth PMOS tube is connected with the drain electrode of the nineteenth NMOS tube, the source electrode of the twenty-first PMOS tube and the source electrode of the twenty-first NMOS tube; the drain electrode of the twentieth NMOS tube is connected with the source electrode of the nineteenth NMOS tube, and the source electrode of the twentieth NMOS tube is grounded; the grid electrode of the twentieth PMOS tube is connected with the output end of the seventh phase inverter, and the drain electrode of the twentieth PMOS tube is connected with the drain electrode of the twenty-third NMOS tube, the input end of the fourth phase inverter, the drain electrode of the twenty-second NMOS tube, the drain electrode of the twenty-first PMOS tube, the drain electrode of the twenty-first NMOS tube and one end of the third capacitor; the grid electrode of the twenty-third NMOS tube is connected with the output end of the sixth inverter; the grid electrode of the twenty-second NMOS tube is connected with the starting signal, and the source electrode of the twenty-second NMOS tube is grounded; the grid electrode of the twenty-first PMOS tube is connected with the output end of the sixth phase inverter, and the grid electrode of the twenty-first NMOS tube is connected with the output end of the seventh phase inverter; the input end of the fifth inverter is connected with the output end of the fourth inverter, the output end of the fifth inverter is connected with the input end of the sixth inverter and one end of the second resistor, the other end of the second resistor is connected with the other end of the third capacitor and one end of the third resistor, and the other end of the third resistor is grounded; the output end of the sixth inverter outputs a 6-time clock frequency signal and is connected with the input end of the seventh inverter in parallel, and the seventh inverter outputs a control signal; the 6-time clock frequency signal is a 6-time clock frequency signal of an external clock;

the input of the frequency division phase separation module is a 6-time clock frequency signal, and the 6-time clock frequency signal generates clock output with the duty ratios of 1/12, 1/6, 1/3 and 1/2 after passing through the frequency division phase separation module.

The invention has the advantages that: the phase-locked loop clock generating circuit for synchronizing the off-chip clock and outputting the clocks with various phases, provided by the invention, realizes the function of synchronizing the off-chip clock and can output the clock signals with various duty ratios and various phase differences by combining the phase-locked loop, the frequency generating circuit and the frequency dividing circuit.

Drawings

FIG. 1 is a block diagram of the system of the present invention.

Fig. 2 is a circuit for implementing phase detection and charge pump.

Fig. 3 is a circuit for implementing clock frequency generation.

FIG. 4 is a circuit diagram of a specific implementation of the frequency-dividing phase-splitting module.

FIG. 5 is a specific arrangement of state machines in the frequency-dividing phase-splitting circuit.

FIG. 6 is a simulated operating waveform for synchronizing an off-chip 650kHz clock signal.

Fig. 7 is a partial view of the simulated waveform of fig. 6.

FIG. 8 is a waveform of a simulation of clock signal outputs of various phases and duty cycles in accordance with the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a specific design block diagram of the present invention, and it can be known from FIG. 1 that the technical implementation process of the present invention is firstly to convert the phase difference between the off-chip clock and the on-chip initial phase clock into a control voltage by identifying the phase of the charge pump module, the specific conversion process is shown in FIG. 2 and its description, the clock frequency generation module will correspondingly change the magnitude of the 6 times clock frequency of its output by controlling the different magnitudes of the voltages to achieve the synchronization of the on-chip initial phase clock and the off-chip clock, the specific implementation circuit is shown in FIG. 3 and its description, in order to achieve the clock output of various duty ratios and various phases, the clock generated by the clock generation module of the present invention is 6 times frequency of the off-chip clock, so that the frequency-dividing phase-splitting module can firstly obtain the clock which has the same frequency and phase as the off-chip clock and also have different duty ratios of phase difference with the off-chip clock, the specific implementation circuit is shown in fig. 4 and the description thereof.

Fig. 2 is a circuit implementation of the phase detection and charge pump module, and since the present invention is suitable for use in a power management chip, a voltage VCC1 of 2.4V commonly used in a digital circuit inside the power management chip can be used as a power supply rail of the phase detection and charge pump module of the present invention, and the specific working principle is as follows: the start signal is usually a logic voltage signal in the whole power-on process of the power chip, the power management chip generally has this signal, after the internal power rail VCC1 of the voltage management chip is established, the start signal is changed from low level to high level, the circuit shown in fig. 2 starts to work, firstly, the difference between the rising edges of the off-chip clock and the in-chip clock is detected by the phase detection circuit composed of logic gates Q1-Q6 and D1-D2, wherein the off-chip clock and the in-chip clock may be voltage signals with different duty ratios, the difference between the rising edges thereof will be reflected to the turn-on and turn-off of the MOS transistors MP2 and MN3 in the charge pump circuit composed of MOS transistors MN 1-MN 8, MP 1-MP 6 and off-chip compensation Rs, Cs and Cp, for example, after the start signal is changed from low level to high level, the MOS transistors MN8 and MN7 are turned on, if the rising edge of the off-chip clock is earlier than the initial phase clock, then QN of the flip-flop D1 is low and the output of D2 is also low, then MP2 is turned on, MN3 is turned off, and then a current will flow through the mirror MOS transistor MP3 to charge the off-chip compensation device, so as to control the voltage rise. When the rising edges of the off-chip clock and the on-chip initial phase clock come, the D1 and the D2 reset the D1 and the D2 at the output of Q, so that the phase detection function is ensured to only detect the phase difference and is not related to the duty ratio of the clock signal. In addition, because the off-chip compensation element is usually a large capacitor and resistor, a certain time is required for the control voltage to rise from 0V to a stable voltage through microampere current charging and discharging of the MOS tubes MN4 and MN3, therefore, the invention has an initialization circuit structure consisting of MOS transistors MP 4-MP 6, MN5 and MN6, in the time period when the start signal is low, the MOS transistors MP5 and MP6 are turned on, the current flowing through the MP4 generates a double gate-source voltage on the MOS transistors MN6 and MN5, in the BCD process, the threshold voltage of a low-voltage device is generally between 0.6V and 0.75V, therefore, by setting the magnitude of the mirror current of the MP4 transistor and the sizes of the MOS transistors MN5 MN6, the initial value of the control voltage can be between 1.2V and 1.5V and is close to the control voltage of the central frequency of the post-generation circuit of the invention, namely the control voltage is 1.2V, and the phase-locked loop adjusts the control voltage to high frequency and low frequency through the central frequency better than the control voltage starting from 0V.

Fig. 3 Is a specific implementation circuit of the clock frequency generation module of the present invention, in which a voltage VCC2 used by a transconductance amplifier structure where MOS transistors MN9 to MN29 and MP9 to MP18 are located Is a 5V voltage rail that Is usually used in a power management chip, inverters Q5 to Q8 still use VCC1 as a power rail, and a reference voltage Is usually 1.2V voltage, so that the circuit in fig. 2 sets a control voltage initial value at about 1.2V and ensures that the initial frequency Is at a central frequency, the clock frequency generation module specifically works in such a way that Ib Is a mirror current, which Is obtained by mirroring two mirror currents Ia and Is an image current through mirror transistors MN9 to MN12 and MP9 to MP14, and MOS transistors MP7, MP8, MP11, MP12, MN13 and MN14, a differential structure formed by MOS transistors MP7, MP8, MP11, MP12 and MN 3684 converts a differential pressure difference of the control voltage into a current flowing into a drain terminal of the MP8 tube, and flowing out when the control voltage Is equal to the reference voltage, and the current flowing into the drain terminal Ig 16 of the mirror tube MN16, the currents Ic and Is satisfy the following relation according to the transconductance of the differential pair

I _c ＝I _s +g _m (ΔV) (1)

Gm in the equation represents the transconductance of the conventional differential amplifier structure composed of MOS transistors MP7, MP8, MP11, MP12, MN13, and MN14, and Δ V represents the difference between the control voltage and the reference voltage.

Therefore, the magnitude of the current Ic is adjusted by controlling the voltage, and the current Ic is mirrored by the current mirror formed by the MOS transistors MN15 to MN20 and MP15 to MP18, so that the mirrored current magnitude is nIc, and the MOS transistors MN15 to MN24, MP15 to MP21, the inverters Q5 to Q5, the resistors R5 and R5, and the capacitor C5 form a square wave generating structure in the frequency generating circuit, in the process, the initial signal is pulled down to 0V by briefly turning on the MOS transistor MN5 in the power-on stage, at this time, the 6-fold clock frequency is high, the control signal 1 is low, the transmission gate formed by the MP5 and MN5 is opened, the transmission gate formed by the MP5 and MN5 is closed, because the MP5 is opened, the current MP5 passing through the mirror of the MOS transistors MN5 and MN5 flows into the capacitor C5, and the capacitor C5 starts to rise, and the current flows through the capacitor C5. When the voltage exceeds the threshold voltage of the inverter Q5 by about 1.2V, the inverter outputs a high level of 2.4V, since R1 is R2, the lower plate of the capacitor C1 is raised by 1.2V, the upper plate of C1 is raised instantaneously to 2.4V, at this time, the 6-fold clock frequency is low, the control signal 1 is high, the transmission gate composed of MP20 and MN23 is closed, the transmission gate composed of MP21 and MN21 is opened, the current mirrored by MN19 and MN20 starts to discharge to the upper plate of the capacitor C1 until it is less than 1.2V, the inverter Q6 outputs a low level, the lower plate of the capacitor C1 is changed from 1.2V to 0V, the upper plate thereof is also changed to 0V, i.e., the initial value is restored, and through the above process, the inverter Q7 can output a square wave voltage with a duty ratio of 0.5, and the frequency magnitude can be expressed as the following formula

In the formula f _{6 frequency multiplication} Representing a 6-fold clock frequency, which is set to 6-fold the off-chip clock frequency, V, by the 1/6 divide function of the pll and post-stage divider circuit _TH The threshold voltage of the inverter Q5 is usually 1.2V, C1 is the capacitance of the capacitor C1, and n is the mirror ratio of the current mirror composed of MOS transistors MN15 to MN20 and MP15 to MP 18.

The central frequency set by the Is in the megahertz range, and the invention can effectively realize the effective generation of a plurality of megahertz frequencies through the inherent state latching and low time delay characteristics of the phase inverter, and can not have overlong square wave rising time delay and falling time delay to influence the setting of specific duty ratio. It can be known from the formulas (1) and (2) that the frequency control of the invention is based on a central frequency, the central frequency corresponds to the control voltage of 1.2V, and at this time, I _C ＝I _S The maximum and minimum values of the frequency are respectively about

Through the clock frequency generation module, the control voltage generated by the phase detection and charge pump module can be converted into 6 times of clock frequency which changes around the center frequency set by Is, so that the 6 times of clock frequency Is set, because the cycle length of the 6 times of clock frequency Is the duty ratio of 1/6 of the off-chip clock, which Is the cycle length of the off-chip clock, Is also 1/2, the synchronous off-chip clock signal with the minimum 1/12 duty ratio and the phase difference of minimum 30 degrees can be realized through the frequency division phase separation module, and the specific implementation process Is shown in fig. 4 and 5.

Because the invention combines a phase-locked loop structure, the frequency of a clock frequency generation module is 6 times of that of an off-chip clock, a frequency division phase-splitting circuit utilizes triggers L1-L3 in FIG. 4 to form an 8-bit state machine, the state switching sequence is shown in FIG. 5, states S2-S7 form 6 cycle states in a Gray code mode, when the rising edge of the 6 times clock frequency comes each time, the states are switched once, and S2-S7 forms a period of outputting a clock signal once per cycle, thus the 6 frequency division function of the 6 times clock frequency can be completed. For example, as shown in fig. 4, the on-chip initial phase clock in the dashed line frame is a signal of 1/12 duty cycle synchronization and an off-chip clock, and the high level of the middle 6 times clock frequency of the state S2 is output as the high level of the output clock signal, so that 1/12 duty cycle generation can be completed, since the effective setting of the state codes S2 and S7 eliminates the 000 state and the 111 state, each of the states S2 to S7 can be represented by the output of a two-bit D flip-flop, and since the high level of the 6 times clock frequency of the duty cycle 1/2 is added to the nand gate, the on-chip initial phase clock of 1/12 duty cycle can be generated, and since the clock signals of L1 to L3, i.e. the 6 times clock frequency, are introduced as the input of the nand gate, in order to avoid clock jitter, the inputs of the inverters L5 and L4 triggered by the falling edge also need to be introduced to the 1/12 duty cycle generation, i.e. triggered by the falling edge of the clock principle The characteristics are that the state of the NAND output is locked, the output of the NAND gate is not jittered when the 6-time clock changes, the flip-flops L4 and L5 are only needed when the 6-time clock frequency is needed to be used as the input of the NAND gate, and the rest are not needed.

With the various states in fig. 5, the present invention can output clock outputs with duty ratios of 1/12, 1/6, 1/3, 1/2, and output 1 or more of states S2 to S7 as high level and the rest as low level of the output clock, specifically see the example of the dashed line box in fig. 4, and can also output clock signals with a minimum 30 ° phase difference with respect to the on-chip initial phase clock, as shown in the dashed line box, the initial phase output by state S2, and the clock frequency 6 times at low level in state S3 is the clock with 90 ° phase difference with state S2.

The invention works in the loop of the phase-locked loop as a whole, so the stability problem of the loop is involved, the stability setting is needed to be carried out through the off-chip compensation in the figure 2, and the loop gain expression of the phase-locked loop is

In the formula I _CP N and g are currents flowing through MOS tubes MP3 and MN4 in the phase detection and charge pump circuit _m 、C1、V _TH In the same formula (1), Rs, Cs, Cp are the resistance value of the off-chip compensation resistor and the capacitance value of the capacitor in fig. 2. The loop phase margin can be easily set to about 60 degrees through the second pole consisting of Cp and Rs and the zero consisting of Rs and Cs according to the formula (3), and the bandwidth is set through the formula (4)

Fig. 6 shows the working waveform of the clock of 650kHz outside the chip of the invention, fig. 7 shows the local waveform after the phase locking is completed, it can be seen from fig. 6 that when the power is on, the control voltage is initialized to about 1.2V, i.e. the control voltage of the center frequency is, at this time, because the frequency of the off-chip clock is greater than 500kHz of the center frequency, the control voltage starts to rise until the off-chip clock is in phase with the initial phase clock inside the chip, as shown in fig. 7, it can also be seen that the duty ratio of the initial phase clock inside the chip is 1/12, which meets the expected design of the invention.

FIG. 8 is a simulated waveform for multiple phases and multiple duty cycles output according to the present invention. It can be known from the simulation waveforms of fig. 8 that the present invention can realize clock signal outputs with different duty ratios and phase differences, which is in line with the expectation of the present invention.

In summary, the invention combines the characteristics of the phase-locked loop, the square wave generating circuit and the digital frequency division phase splitting, and provides a clock voltage signal which can synchronize an off-chip clock and output various duty ratios and phase differences, and can be applied to a power supply chip adopting a multiphase interleaving control technology. In addition, the phase-locked loop has an initialization function, so that the problem that the time consumption of a synchronous off-chip clock is too long when the phase-locked loop is powered on is avoided, the 6-time clock frequency square wave generating circuit effectively utilizes the high-speed low-delay characteristic of the phase inverter to ensure that the rising and falling delay is not too large in the work of a plurality of megahertz frequency square waves, and meanwhile, the 6-time clock frequency 6 times of the off-chip clock is subjected to frequency division and phase splitting to output clock signals with various duty ratios and phase differences, so that the phase-locked loop is suitable for the control technology of various power management chips at present.

Claims

1. A clock generation circuit based on a phase-locked loop synchronous external clock is characterized by comprising a phase identification and charge pump module, a clock frequency generation module and a frequency division and phase splitting module;

the clock frequency generation module comprises a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a second current source, a second resistor, a third resistor and a third capacitor; the grid electrode of the seventh PMOS tube is connected with the output end of the phase discrimination and charge pump module, the source electrode of the seventh PMOS tube is connected with the drain electrode of the twelfth PMOS tube and the source electrode of the eighth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the grid electrode and the drain electrode of the thirteenth NMOS tube and the grid electrode of the fourteenth NMOS tube; the source electrode of the thirteenth NMOS tube and the source electrode of the fourteenth NMOS tube are grounded; a source electrode of the twelfth PMOS tube is connected with a drain electrode of the eleventh PMOS tube, a grid electrode of the twelfth PMOS tube is connected with a grid electrode of the eleventh PMOS tube, a grid electrode of the ninth PMOS tube, a grid electrode and a drain electrode of the tenth PMOS tube, a grid electrode of the thirteenth PMOS tube, a grid electrode of the fourteenth PMOS tube and a drain electrode of the eleventh NMOS tube; the source electrode of the ninth PMOS tube is connected with the power supply, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the tenth PMOS tube; the grid electrode of the eleventh NMOS tube is connected with the grid electrode and the drain electrode of the ninth NMOS tube, the output end of the current source, the grid electrode of the tenth NMOS tube and the grid electrode of the twelfth NMOS tube; the drain electrode of the tenth NMOS tube is connected with the source electrode of the ninth NMOS tube, and the source electrode of the tenth NMOS tube is grounded; the drain electrode of the twelfth NMOS tube is connected with the source electrode of the eleventh NMOS tube, and the source electrode of the twelfth NMOS tube is grounded; the grid electrode of the eighth PMOS tube is connected with the reference voltage, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fourteenth PMOS tube, the drain electrode of the fourteenth NMOS tube, the grid electrode of the fifteenth NMOS tube, the grid electrode of the nineteenth NMOS tube and the grid electrode of the twentieth NMOS tube; the source electrode of the fourteenth NMOS tube is grounded; the source electrode of the fourteenth PMOS tube is connected with the drain electrode of the thirteenth PMOS tube; the drain electrode of the sixteenth NMOS tube is connected with the source electrode of the fifteenth NMOS tube, and the source electrode of the sixteenth NMOS tube is grounded; the source electrode of the fifteenth PMOS tube is connected with the power supply, the grid electrode of the fifteenth PMOS tube is connected with the grid electrode and the drain electrode of the sixteenth PMOS tube, the grid electrode of the seventeenth PMOS tube, the grid electrode of the eighteenth PMOS tube and the drain electrode of the seventeenth NMOS tube, and the drain electrode of the fifteenth PMOS tube is connected with the source electrode of the sixteenth PMOS tube; the drain electrode of the eighteenth NMOS tube is connected with the source electrode of the seventeenth NMOS tube, and the source electrode of the eighteenth NMOS tube is grounded; a source electrode of the eighteenth PMOS tube is connected with a drain electrode of the seventeenth PMOS tube, and a drain electrode of the eighteenth PMOS tube is connected with a drain electrode of the twenty-fourth NMOS tube, a source electrode of the twentieth PMOS tube and a source electrode of the twenty-third NMOS tube; the source electrode of the nineteenth PMOS tube is connected with the power supply, the grid electrode of the nineteenth PMOS tube is connected with the output end of the sixth phase inverter, and the drain electrode of the nineteenth PMOS tube is connected with the drain electrode of the nineteenth NMOS tube, the source electrode of the twenty-first PMOS tube and the source electrode of the twenty-first NMOS tube; the drain electrode of the twentieth NMOS tube is connected with the source electrode of the nineteenth NMOS tube, and the source electrode of the twentieth NMOS tube is grounded; the grid electrode of the twentieth PMOS tube is connected with the output end of the seventh phase inverter, and the drain electrode of the twentieth PMOS tube is connected with the drain electrode of the twenty-third NMOS tube, the input end of the fourth phase inverter, the drain electrode of the twenty-second NMOS tube, the drain electrode of the twenty-first PMOS tube, the drain electrode of the twenty-first NMOS tube and one end of the third capacitor; the grid electrode of the twenty-third NMOS tube is connected with the output end of the sixth inverter; the grid electrode of the twenty-second NMOS tube is connected with the starting signal, and the source electrode of the twenty-second NMOS tube is grounded; the grid electrode of the twenty-first PMOS tube is connected with the output end of the sixth phase inverter, and the grid electrode of the twenty-first NMOS tube is connected with the output end of the seventh phase inverter; the input end of the fifth inverter is connected with the output end of the fourth inverter, the output end of the fifth inverter is connected with the input end of the sixth inverter and one end of the second resistor, the other end of the second resistor is connected with the other end of the third capacitor and one end of the third resistor, and the other end of the third resistor is grounded; the output end of the sixth inverter outputs a 6-time clock frequency signal and is connected with the input end of the seventh inverter in parallel, and the seventh inverter outputs a control signal; the 6-time clock frequency signal is a 6-time clock frequency signal of an external clock;

the input of the frequency division phase separation module is a 6-time clock frequency signal, and the 6-time clock frequency signal generates clock outputs with duty ratios of 1/12, 1/6, 1/3 and 1/2 after passing through the frequency division phase separation module.