CN115084272A - Shielding gate MOSFET device structure and preparation method thereof - Google Patents
Shielding gate MOSFET device structure and preparation method thereof Download PDFInfo
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- CN115084272A CN115084272A CN202211003471.9A CN202211003471A CN115084272A CN 115084272 A CN115084272 A CN 115084272A CN 202211003471 A CN202211003471 A CN 202211003471A CN 115084272 A CN115084272 A CN 115084272A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
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- 238000005530 etching Methods 0.000 claims description 56
- 210000000746 body region Anatomy 0.000 claims description 48
- 238000005468 ion implantation Methods 0.000 claims description 17
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- 230000003647 oxidation Effects 0.000 claims description 11
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- 239000004065 semiconductor Substances 0.000 abstract description 2
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- 239000000758 substrate Substances 0.000 description 13
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- 238000005457 optimization Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
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- 125000006850 spacer group Chemical group 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The invention discloses a shielded gate MOSFET device structure and a preparation method thereof, and relates to the technical field of semiconductor power devices. The method comprises the following steps: a first groove and a second groove are arranged in the first conductive epitaxial layer; the first groove comprises a first gate oxide layer and a first polycrystalline silicon layer from outside to inside; the second groove is divided into an upper part and a lower part from bottom to top by a second gate oxide layer, the lower part comprises a first gate oxide layer and a first polycrystalline silicon layer from outside to inside, and the upper part comprises a second polycrystalline silicon layer, a second gate oxide layer and an isolation oxide layer from outside to inside; a second gate oxide layer, an isolation oxide layer and a metal layer are sequentially arranged on the first conductive epitaxial layer; contact holes are formed in the second groove, between the first groove and the second groove and on one side, far away from the first groove, of the second groove.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a shielded gate MOSFET device structure and a preparation method thereof.
Background
Compared with the traditional trench MOSFET, the SGT (shielded Gate MOSFET) device structure has the advantages of low on-resistance and small Miller capacitance. SGT has significant advantages in terms of figure of merit FOM (FOM = on-resistance Ron × gate charge Qg), etc., meaning that it can have higher power density and lower switching loss, and thus has attracted extensive attention and become a mainstream device in the middle and low voltage fields.
The grid electrode of the shielded grid groove type MOSFET structure simultaneously comprises a shielded grid and a control grid. Conventional shielded gate MOSFET device structures are generally divided into an up-down structure and a left-right structure according to the relative positions of a shielded gate (also called Source poly layer) and a control gate in a trench.
The vertical cross-sectional structure of the conventional SGT cell is shown in fig. 1A and 1B, and specifically, as shown in fig. 1A, the shield gate is located at the bottom of the trench, the gate is located at the top of the trench, and the gate and the shield gate are in a vertical structure relationship. For the shielding grid MOSFET device structure with the upper structure and the lower structure, an oxide layer exists between the shielding grid and the control grid for isolation. The formation of the control gate and the shield gate and their Inter-electrode Oxide (Inter Poly Oxide) is a key point of the SGT MOSFET process, and is also a feature of the structure, and the quality of the Oxide determines the performance of the device. There are two currently mature manufacturing processes for inter-electrode oxide growth: high density plasma chemical vapor deposition (HDP CVD) and Thermal oxidation (Thermal Oxide) or both are used alternately; the method of HDP CVD can control the thickness of the oxide layer between the grids more accurately, but the manufacturing cost is higher; the control grid of the thermal oxidation method is surrounded around the upper part of the shielding grid like a top cap, so that the capacitance area between the shielding grid and the control grid is larger, the input capacitance of the device is relatively larger, and meanwhile, a sharp corner also exists at the bottom of the control grid, so that the electric leakage between the shielding grid and the control grid is easy to increase, and the reliability of the device is reduced. As such, SGTs of the top-bottom structure face complex process challenges.
As shown in fig. 1B, in the left-right structure, the shielding gate usually extends from the bottom of the trench to the top of the trench, the control gate is disposed on the left and right sides of the shielding gate in the top region of the trench, and the gate in the same trench is split into two structures. For the shielding grid MOSFET device structure with a left structure and a right structure, the problem of SGT (SGT complex process) complex process with an upper structure and a lower structure is avoided, but parasitic Miller capacitance C introduced by the structure gd Will be larger, gate charge Q g Is relatively large. The switching speed is slow, the switching loss is large, and the performance of the SGT structure is reduced under the high-frequency application condition.
Disclosure of Invention
The embodiment of the invention provides a shielding gate MOSFET device structure and a preparation method thereof, wherein a triangular structure provided by the embodiment of the invention is formed by etching a first polysilicon layer, so that the optimization of the device structure is realized, and the aim of further reducing the dynamic parameters (such as gate charge Qg) of the device on the premise of not increasing the on-resistance is fulfilled, thereby finally reducing the optimal FOM of the device and having higher cost performance; the conventional SGT cannot adjust the dynamic parameters of the device due to its structural limitation. The novel triangular SGT structure provided by the invention realizes the adjustment of dynamic parameters (such as gate charge Qg) of a device by properly adjusting the height of the first polysilicon layer, namely the height of the top of the first polysilicon layer is within +/-30% of the height of the bottom of the second polysilicon layer, so that the novel triangular SGT structure meets the requirements of more specific applications.
The embodiment of the invention provides a shielded gate MOSFET device structure, which comprises:
a first groove and a second groove are arranged in the first conductive epitaxial layer;
the first groove comprises a first gate oxide layer and a first polycrystalline silicon layer from outside to inside;
the second groove is divided into an upper part and a lower part from bottom to top by a second gate oxide layer, the lower part of the second groove comprises a first gate oxide layer and a first polycrystalline silicon layer from outside to inside, and the upper part of the second groove comprises a second polycrystalline silicon layer, a second gate oxide layer and an isolation oxide layer from outside to inside;
a second gate oxide layer, an isolation oxide layer and a metal layer are sequentially arranged on the first conductive epitaxial layer;
contact holes are formed in the second groove, between the first groove and the second groove and on one side, far away from the first groove, of the second groove.
Preferably, a second conductive type body region and a first conductive type source region are further included;
a second conductive type body region is included between the first trench and the second trench;
one side of the second groove, which is far away from the first groove, comprises a second conductive type body region and a first conductive type source region from bottom to top;
wherein a lower surface of the second conductive type body region is higher than an upper surface of the first polysilicon layer located in the second trench.
Preferably, the contact holes are divided into a first contact hole, a second contact hole and a third contact hole;
the first contact hole is positioned on the first groove, and one end of the first contact hole penetrates through the second gate oxide layer and is in contact with the first polycrystalline silicon layer arranged in the first groove;
the second contact hole is positioned between the first groove and the second groove, and one end of the second contact hole penetrates through the second gate oxide layer and is in contact with the second conductive type body region;
the third contact hole is positioned on one side of the second groove far away from the first groove, and one end of the third contact hole penetrates through the second gate oxide layer and the first conduction type source region to be contacted with the second conduction type body region.
The embodiment of the invention also provides a preparation method of the structure of the shielded gate MOSFET device, which comprises the following steps:
forming a second photoresist layer on the top of the first groove and one side of the first groove far away from the second groove, and etching the first gate oxide layer of the second groove and the first gate oxide layers on two sides of the top of the second groove by an etching method; removing the second photoresist layer, and forming a second gate oxide layer in the second groove, on two sides of the top of the second groove, on the top of the first groove and on two sides of the top of the first groove through a thermal oxidation process;
forming a second polycrystalline silicon layer in the second groove and on the upper layer of the second gate oxide layer; forming a third photoresist layer on the top of the first groove, two sides of the top of the first groove, the top of the second groove and two sides of the top of the second groove; etching the second gate oxide layer and the first polysilicon layer in the second groove by an etching method;
forming a second conductive type body region between the second groove and the first groove by ion implantation, and forming the second conductive type body region and the first conductive type source region from bottom to top on one side of the second groove far away from the first groove; and forming an isolation oxide layer above the second gate oxide layer, and preparing a contact hole on the isolation oxide layer.
Preferably, before forming the second photoresist layer on the top of the first trench and on the side of the first trench far from the second trench, the method further includes:
removing the first oxide layer and the first photoresist layer on the first conductive epitaxial layer;
forming a first gate oxide layer in the first trench, on the top side of the first trench, in the second trench and on the top side of the second trench;
and forming a first polysilicon layer on the first gate oxide layer in the first trench, on the top side surface of the first trench, in the second trench and on the top side surface of the second trench.
Preferably, before forming the second photoresist layer on the top of the first trench and on the side of the first trench far from the second trench, the method further includes:
and removing the first polycrystalline silicon layer on the first conductive epitaxial layer by an etching method so that the upper surfaces of the first polycrystalline silicon layer in the first polycrystalline silicon layer and the second polycrystalline silicon layer in the first groove and the upper surface of the first gate oxide layer on the first conductive epitaxial layer have the same height.
Preferably, the etching of the first gate oxide layer in the second trench and the first gate oxide layers on two sides of the top of the second trench by an etching method specifically includes:
etching the first gate oxide layer in the second groove, so that the upper part of the first gate oxide layer in the second groove is etched;
and etching the first gate oxide layers on two sides of the top of the second groove so as to etch the first gate oxide layers on two sides of the top of the second groove.
Preferably, the etching the second gate oxide layer and the first polysilicon layer in the second trench by using an etching method specifically includes:
and etching the second gate oxide layer and the first polycrystalline silicon layer in the second groove by an etching method so that the upper surface of the etched first polycrystalline silicon layer and the lower surface of the second polycrystalline silicon layer have the same height.
Preferably, before the ion implantation, the method further comprises:
through a thermal oxidation process, the inner side of the second polycrystalline silicon layer positioned in the second groove is oxidized to generate a second gate oxide layer, and the upper surface of the first polycrystalline silicon layer is oxidized to generate the second gate oxide layer;
the second gate oxide layer positioned on the upper surface of the first polycrystalline silicon layer is contacted with the first gate oxide layer positioned below the second polycrystalline silicon layer.
Preferably, the forming, by ion implantation, a second conductive type body region between the second trench and the first trench, and forming, from bottom to top, the second conductive type body region and the first conductive type source region on a side of the second trench far from the first trench specifically include:
forming a second conductive type body region between the second trench and the first trench on one side of the second trench far away from the first trench through first ion implantation, wherein the lower surface of the second conductive type body region is higher than the upper surface of the first polycrystalline silicon layer in the second trench;
and forming a first conductive type source region on one side of the second groove far away from the first groove by second ion implantation, wherein the first conductive type source region is positioned in the second conductive type body region, and the upper surface of the first conductive type source region and the upper surface of the first conductive type epitaxial layer have the same height.
The embodiment of the invention provides a shielded gate MOSFET device structure and a preparation method thereof, wherein the preparation method comprises the following steps: forming a second photoresist layer on the top of the first groove and one side of the first groove far away from the second groove, and etching the first gate oxide layer in the second groove and the first gate oxide layers on two sides of the top of the second groove by an etching method; removing the second photoresist layer, and forming a second gate oxide layer in the second trench, on two sides of the top of the second trench, on the top of the first trench and on two sides of the top of the first trench through a thermal oxidation process; forming a second polycrystalline silicon layer in the second groove and on the upper layer of the second gate oxide layer; forming a third photoresist layer on the top of the first groove, two sides of the top of the first groove, the top of the second groove and two sides of the top of the second groove; etching the second gate oxide layer and the first polysilicon layer in the second groove by an etching method; forming a second conductive type body region between the second groove and the first groove through ion implantation, and forming the second conductive type body region and a first conductive type source region on one side of the second groove far away from the first groove from bottom to top; and forming an isolation oxide layer above the second gate oxide layer, and preparing a contact hole on the isolation oxide layer. According to the preparation method, the third photoresist layer is arranged, and the triangular structure provided by the embodiment of the invention is formed by etching the first polysilicon layer, so that the optimization of the device structure is realized, and the aim of further reducing the dynamic parameters (such as gate charge Qg) of the device on the premise of not increasing the on-resistance is fulfilled, so that the optimal FOM of the device is reduced and the device has higher cost performance; the novel triangular SGT structure provided by the invention realizes the adjustment of dynamic parameters (such as gate charge Qg) of a device by properly adjusting the height of the first polysilicon layer, namely the height of the top of the first polysilicon layer is within +/-30% of the height of the bottom of the second polysilicon layer, so that the novel triangular SGT structure meets the requirements of more specific applications. Moreover, the third photoresist layer is arranged, so that the peripheral terminal trench is effectively protected, no gate poly residue is left in the process, and electric leakage caused by short circuit of a source electrode and a grid electrode is avoided; furthermore, the contact holes of the grid polysilicon layers on two sides in the groove are led out at the position of the gate bus finger pick-up of the device, and the leakage from the grid to the drain caused by the traditional arrangement of the contact holes in the middle position is effectively prevented.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1A is a schematic diagram of a vertical cross-section of a conventional SGT cell;
FIG. 1B is a schematic diagram of another vertical cross-sectional structure of a conventional SGT cell;
fig. 2A is a schematic structural diagram of a shielded gate MOSFET device according to an embodiment of the present invention;
fig. 2B is a schematic diagram of a gate bus finger pick-up structure included in a shielded gate MOSFET device structure according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a manufacturing process of a shielded gate MOSFET device structure according to an embodiment of the present invention;
fig. 4A is a schematic diagram illustrating a location of a trench defined in a first conductive epitaxial layer according to an embodiment of the present invention;
FIG. 4B is a schematic diagram illustrating trench preparation according to an embodiment of the present invention;
FIG. 4C is a schematic diagram of removing the photoresist and the first oxide layer according to an embodiment of the present invention;
FIG. 4D is a schematic diagram illustrating the formation of a first gate oxide layer in a trench according to an embodiment of the present invention;
FIG. 4E is a schematic diagram illustrating a first polysilicon layer formed in the trench according to an embodiment of the present invention;
FIG. 4F is a schematic view of a second photoresist layer formed according to an embodiment of the present invention;
fig. 4G is a schematic diagram of etching the first gate oxide layer according to the embodiment of the invention;
FIG. 4H is a schematic diagram illustrating the fabrication of a second gate oxide layer according to an embodiment of the present invention;
FIG. 4I is a schematic diagram of a second polysilicon layer according to an embodiment of the present invention;
FIG. 4J is a schematic view of a third photoresist layer prepared according to an embodiment of the present invention;
FIG. 4K is a schematic diagram illustrating etching of a second gate oxide layer and a first polysilicon layer in a second trench according to an embodiment of the present invention;
FIG. 4L is a schematic view of the third photoresist layer being removed according to an embodiment of the present invention;
FIG. 4M is a schematic diagram of two ion implantations according to an embodiment of the present invention;
fig. 4N is a schematic diagram of an isolation oxide layer according to an embodiment of the invention;
FIG. 4O is a schematic diagram of a contact hole preparation process provided in an embodiment of the invention;
FIG. 4P is a schematic diagram of a metal layer preparation according to an embodiment of the present invention;
wherein the first conductivity type substrate layer 101; a first conductive epitaxial layer 102; a first oxide layer 103; a first photoresist layer 104; a first trench 105-1; a second trench 105-2; a first gate oxide layer 106-1; first polysilicon layer 107-1; a second gate oxide layer 106-2; second polysilicon layer 107-2; a second photoresist layer 108; a third photoresist layer 110; the second conductivity type body region 111; a first conductive type source region 112; an isolation oxide layer 113; a contact hole 114; metal layer 115, passivation layer 116.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 2A is a schematic structural diagram of a shielded gate MOSFET device according to an embodiment of the present invention; fig. 2B is a schematic diagram of a gate bus finger pick-up structure included in a shielded gate MOSFET device structure according to an embodiment of the present invention; as shown in fig. 2A and 2B, the shielded gate MOSFET device structure mainly includes a first trench 105-1, a second trench 105-2, a first conductive epitaxial layer 102, a first polysilicon layer 107-1, a second polysilicon layer 107-2, a first gate oxide layer 106-1, a second gate oxide layer 106-2, a second conductivity type body region 111, and a first conductivity type source region 112.
Specifically, the notches of the first trench 105-1 and the second trench 105-2 have the same height as the upper surface of the first conductive epitaxial layer 102, i.e., the notches of the first trench 105-1 and the second trench 105-2 are located on the upper surface of the first conductive epitaxial layer 102; and the lower ends of the first trenches 105-1 and the second trenches 105-2 extend into the first conductive epitaxial layer 102.
Further, a first gate oxide layer 106-1, a first polysilicon layer 107-1 and a contact hole 114 are sequentially arranged in the first trench 105-1 from outside to inside; the lower half part of the second trench 105-2 is provided with a first gate oxide 106-1 and a first polysilicon layer 107-1 from outside to inside, the upper half part is provided with a second gate oxide 106-2, a second polysilicon layer 107-2, a second gate oxide 106-2 and an isolation oxide layer 113 from outside to inside, and a second gate oxide 106-2 is arranged between the first polysilicon layer 107-1 and the second polysilicon layer 107-2, i.e. the second trench 105-2 is divided into an upper half part and a lower half part from top to bottom by the second gate oxide 106-2 arranged between the first polysilicon layer 107-1 and the second polysilicon layer 107-2.
Further, a second gate oxide layer 106-2, an isolation oxide layer 113 and a metal layer 115 are sequentially disposed above the first conductive epitaxial layer 102.
Further, a second conductive type body region 111 and a first conductive type source region 112 are distributed on one side of the second trench 105-2 away from the first trench 105-1, wherein the first conductive type source region 112 is located in the second conductive type body region 111, and the first conductive type source region 112, the second conductive type body region 111 and the upper surface of the first conductive epitaxial layer 102 have the same height; a second conductive-type body region 111 is disposed between the second trench 105-2 and the first trench 105-1.
Further, a first contact hole 114 is located on the first trench 105-1, and one end thereof penetrates through the second gate oxide layer 106-2 to contact with the first polysilicon layer 107-1 disposed in the first trench 105-1; the second contact hole 114 is located between the first trench 105-1 and the second trench 105-2, and one end thereof penetrates through the second gate oxide layer 106-2 to be in contact with the second conductive type body region 111; the third contact hole 114 is located on a side of the second trench 105-2 away from the first trench 105-1, and has one end penetrating through the second gate oxide layer 106-2, the first conductive type source region 112 and the second conductive type body region 111.
In the embodiment of the invention, the third photoresist layer is arranged, and the triangular structure provided by the embodiment of the invention is formed by etching the first polysilicon layer, so that the optimization of the device structure is realized, and the aim of further reducing the dynamic parameters (such as gate charge Qg) of the device on the premise of not increasing the on-resistance is fulfilled, thereby finally reducing the optimal FOM of the device and having higher cost performance; the conventional SGT cannot adjust the dynamic parameters of the device due to its structural limitation. The novel triangular SGT structure provided by the invention realizes the adjustment of dynamic parameters (such as gate charge Qg) of a device by properly adjusting the height of the first polysilicon layer, namely the height of the top of the first polysilicon layer is within +/-30% of the height of the bottom of the second polysilicon layer, so that the novel triangular SGT structure meets the requirements of more specific applications.
Fig. 3 is a schematic flow chart of a manufacturing process of a shielded gate MOSFET device structure according to an embodiment of the present invention; fig. 4A is a schematic diagram illustrating a location of a trench defined in a first conductive epitaxial layer according to an embodiment of the present invention; FIG. 4B is a schematic diagram illustrating trench preparation according to an embodiment of the present invention; FIG. 4C is a schematic diagram of removing the photoresist and the first oxide layer according to an embodiment of the present invention; FIG. 4D is a schematic diagram illustrating the formation of a first gate oxide layer in a trench according to an embodiment of the present invention; FIG. 4E is a schematic diagram illustrating the preparation of a first polysilicon layer in a trench according to an embodiment of the present invention; FIG. 4F is a schematic view of a second photoresist layer formed according to an embodiment of the present invention; fig. 4G is a schematic diagram of etching the first gate oxide layer according to the embodiment of the invention; FIG. 4H is a schematic diagram of the fabrication of a second gate oxide layer according to an embodiment of the present invention; FIG. 4I is a schematic diagram of a second polysilicon layer according to an embodiment of the present invention; FIG. 4J is a schematic view of a third photoresist layer prepared according to an embodiment of the present invention; FIG. 4K is a schematic diagram illustrating etching of a second gate oxide layer and a first polysilicon layer in a second trench according to an embodiment of the present invention; FIG. 4L is a schematic view of the third photoresist layer being removed according to an embodiment of the present invention; FIG. 4M is a schematic diagram of two ion implantations according to an embodiment of the present invention; fig. 4N is a schematic diagram of an isolation oxide layer according to an embodiment of the invention; FIG. 4O is a schematic diagram of a contact hole preparation process provided in an embodiment of the invention; FIG. 4P is a schematic diagram of a metal layer preparation according to an embodiment of the present invention;
in the following, a method for manufacturing a shielded gate MOSFET device structure provided in fig. 3 is described in detail with reference to the schematic manufacturing diagrams provided in fig. 4A to 4P, and specifically, as shown in fig. 3, the method mainly includes the following steps:
specifically, as shown in fig. 4A, a first conductive epitaxial layer 102 is formed on a provided first conductive type substrate layer 101, and a first oxide layer 103 is formed on the first conductive epitaxial layer 102 as a barrier layer for trench etching.
In the embodiment of the present invention, a first conductivity type substrate layer may be provided first, and a first conductivity type epitaxial layer is generated on the first conductivity type substrate layer, where the first conductivity type substrate layer may be an N-type substrate or a P-type substrate, and when the first conductivity type substrate layer is an N-type substrate, the first conductivity type epitaxial layer disposed on the N-type substrate is an N-type epitaxial layer; when the first conductive type substrate layer is a P-type substrate, the first conductive epitaxial layer arranged on the P-type substrate is a P-type epitaxial layer.
A first photoresist layer 104 is formed on the first oxide layer 103, and notch positions of the first trench 105-1 and the second trench 105-2 are defined by the first photoresist layer 104. Then, the first oxide layer 103 is etched to the upper surface of the first conductive epitaxial layer 102, that is, the first oxide layer 103 on the first conductive epitaxial layer 102 is etched to form a trench.
As shown in fig. 4B, first trench 105-1 and second trench 105-2 etches within first conductive epitaxial layer 102. It should be noted that the first trench 105-1 is located in a terminal region in the first conductive epitaxial layer 102, and the second trench 105-2 is located in a cell region in the first conductive epitaxial layer 102.
As shown in fig. 4C, the first photoresist layer 104 and the first oxide layer 103 on the upper surface of the first conductive epitaxial layer 102 are removed, and a sacrificial oxide layer is formed inside the first trench 105-1, inside the second trench 105-2 and on the upper surface of the first conductive epitaxial layer 102, wherein the sacrificial oxide layer is located on the bottom and the sidewall of the first trench 105-1 and the second trench 105-2.
As shown in fig. 4D, the sacrificial oxide layer is removed, and then a relatively thick first gate oxide layer 106-1 is formed inside the first trench 105-1, inside the second trench 105-2, and on the upper surface of the first conductive epitaxial layer 102, wherein the first gate oxide layer 106-1 is located on the bottom and sidewalls of the first trench 105-1 and the second trench 105-2.
As shown in fig. 4E, a first polysilicon layer 107-1 is formed in the first trench 105-1, the second trench 105-2 and the top side surfaces of the two trenches, the first polysilicon layer 107-1 is etched for the first time by a dry etch back method, that is, the first polysilicon layer 107-1 on both sides of the two trenches is removed, that is, only the first polysilicon layer 107-1 in the first trench 105-1 and the second trench 105-2 remains, after etching, the upper surface of the first polysilicon layer 107-1 in the first trench 105-1 and the second trench 105-2 has the same height as the upper surface of the first gate oxide layer 106-1 disposed above the first conductive epitaxial layer 102.
specifically, as shown in fig. 4F, a second photoresist layer 108 is formed on the top of the first trench 105-1 and on the side of the first trench 105-1 away from the second trench 105-2, that is, the second photoresist layer 108 covers the top of the first trench 105-1 and the side of the first trench 105-1 away from the second trench 105-2, it should be noted that the second photoresist only covers the top of the second trench 105-2 and does not cover the first gate oxide layer 106-1 between the first trench 105-1 and the second trench 105-2.
As shown in fig. 4G, the first gate oxide layer 106-1 within the second trench 105-2 and on both sides of the top of the second trench 105-2 is etched. Specifically, the first gate oxide layer 106-1 in the second trench 105-2 is etched such that the upper surface of the first gate oxide layer 106-1 in the second trench 105-2 is lower than the upper surface of the first polysilicon layer 107-1 in the second trench 105-2, wherein the upper surface of the first polysilicon layer 107-1 in the second trench 105-2 has the same height as the upper surface of the first conductive epitaxial layer 102. Furthermore, the first gate oxide layers 106-1 on both sides of the top of the second trench 105-2 are etched away, so that the first gate oxide layers 106-1 on both sides of the top of the second trench 105-2 are etched, and it should be noted that, since the second photoresist only covers the top of the first trench 105-1 and one side of the first trench 105-1 far away from the second trench 105-2, all the first gate oxide layers 106-1 between the first trench 105-1 and the second trench 105-2 are etched away.
It should be noted that, in the above-mentioned etching of the first gate oxide layer 106-1 in the second trench 105-2, the etching depth may be determined according to specific process parameters, and in the embodiment of the present invention, the etching depth of the first gate oxide layer 106-1 in the second trench 105-2 is not specifically limited.
Further, as shown in fig. 4H, the second photoresist is removed, and a high quality gate oxide layer, referred to herein as a second gate oxide layer 106-2, is formed in the second trench 105-2, on both sides of the top of the second trench 105-2, on the top of the first trench 105-1, and on both sides of the top of the first trench 105-1 by a thermal oxidation process. It should be noted that the second gate oxide layer 106-2 formed in the second trench 105-2 is located on the upper surface of the first gate oxide layer 106-1, two sides of the second trench 105-2, and the upper surface of the first polysilicon layer 107-1; the second gate oxide layers 106-2 are generated on two sides of the top of the second trench 105-2 and are positioned on the upper surface of the first conductive epitaxial layer 102; the second gate oxide layer 106-2 generated on the top of the first trench 105-1 is positioned on the upper surfaces of the first gate oxide layer 106-1 and the first polysilicon layer 107-1, and the second gate oxide layer 106-2 generated on the side of the first trench 105-1 far away from the second trench 105-2 is positioned on the upper surface of the first gate oxide layer 106-1. Further, the second gate oxide layer 106-2 on the first conductive epitaxial layer 102 has the same height.
specifically, as shown in fig. 4I, a heavily doped gate polysilicon layer, i.e., a second polysilicon layer 107-2, is formed on the top of the first trench 105-1, on both sides of the first trench 105-1, and in the second trench 105-2, on both sides of the top of the second trench 105-2 by a deposition process.
Further, the second polysilicon layer 107-2 located at both sides of the top of the first trench 105-1 and both sides of the top of the second trench 105-2 is etched away, and specifically, the upper surface of the second trench 105-2 includes the second gate oxide layer 106-2, the second polysilicon layer 107-2 and the second gate oxide layer 106-2 from the outside to the inside, while the upper surface of the first trench 105-1 includes only the second gate oxide layer 106-2, and both sides of the top of the second trench 105-2 and both sides of the top of the first trench 105-1 include only the second gate oxide layer 106-2.
As shown in fig. 4J, a third photoresist layer 110 is formed on the top of the first trench 105-1, both sides of the top of the first trench 105-1, the top of the second trench 105-2, and both sides of the top of the second trench 105-2, i.e., the third photoresist layer 110 is formed on the upper surface of the second gate oxide layer 106-2. It should be noted that the third photoresist leaves a window to be etched on the upper surface of the second trench 105-2.
As shown in fig. 4K, the second gate oxide layer 106-2 on the top of the first polysilicon layer 107-1 is etched by etching, and then the etching depth of the first polysilicon layer 107-1 is determined according to the process parameters, where the etching depth of the first polysilicon layer 107-1 is not limited.
Further, as shown in fig. 4L, the third photoresist is removed, and a thermal oxidation process is performed, so that the second gate oxide layer 106-2 is formed by oxidizing the inner side of the second polysilicon layer 107-2 in the second trench 105-2, and the second gate oxide layer 106-2 is formed by oxidizing the upper surface of the first polysilicon layer 107-1; specifically, the second gate oxide layer 106-2 located on the upper surface of the first polysilicon layer 107-1 is in contact with the first gate oxide layer 106-1 located under the second polysilicon layer 107-2.
In the above steps, the third photoresist layer is provided, so that the peripheral terminal trench is effectively protected, no gate poly residue is left in the process, and leakage caused by short circuit between the source and the gate is avoided; by arranging the third photoresist layer and etching the first polysilicon layer, the novel triangular structure provided by the invention is formed, the optimization of the device structure is realized, and the purpose of further reducing the dynamic parameters (such as gate charge Qg) of the device on the premise of not increasing the on-resistance is achieved, so that the optimal FOM of the device is reduced and the device has higher cost performance. The novel triangular SGT structure provided by the invention realizes the adjustment of dynamic parameters (such as gate charge Qg) of a device by properly adjusting the height of the first polysilicon layer, namely the height of the top of the first polysilicon layer is within +/-30% of the height of the bottom of the second polysilicon layer, so that the novel triangular SGT structure meets the requirements of more specific applications.
Specifically, as shown in fig. 4M, a photoresist layer of the second conductive type body region 111, i.e., a fourth photoresist layer, is formed on the second gate oxide layer 106-2 through a photolithography process. Specifically, the third photoresist layer 110 is located on one side of the first trench 105-1 away from the second trench 105-2 and on the top of the first trench 105-1, an implantation region of the second conductive type body region 111 is defined in the first conductive epitaxial layer 102 through a photolithography process, a first ion implantation is performed on the first conductive epitaxial layer 102, after the fourth photoresist is removed, the second conductive type body region 111 is pushed to a required junction depth in a hot well pushing manner, and the second conductive type body region 111 is formed in the first conductive epitaxial layer 102 on both sides of the second trench 105-2. Note that the lower surface of the second conductivity type body region 111 is higher than the upper surface of the first polysilicon layer 107-1 in the second trench 105-2, i.e., the junction depth is above the bottom of the gate polysilicon layer.
Further, a first conductive type source region 112 photoresist layer, i.e., a fifth photoresist layer, is formed on the second gate oxide layer 106-2 through a photolithography process. Specifically, the fifth photoresist layer is located on the top of the first trench 105-1, on both sides of the top of the first trench 105-1, between the second trench 105-2 and the first trench 105-1, and on the top of the first trench. When the implantation region of the first conductive type source region 112 is defined, a second ion implantation is performed on the first conductive epitaxial layer 102, so as to form the first conductive type source region 112 in the first conductive epitaxial layer 102.
As shown in fig. 4N, after the second conductive type body region 111 and the first conductive type source region 112 are sequentially formed in the first conductive epitaxial layer 102, the isolation oxide layer 113 starts to be formed on the upper surface of the second gate oxide layer 106-2, and the isolation oxide layer 113 is also formed on the second gate oxide layer 106-2 in the second trench 105-2. In one embodiment of the present invention, the spacer oxide layer is LTO and BPSG.
As shown in fig. 4O, after the isolation oxide layer 113 is formed, a sixth photoresist layer is formed on the isolation oxide layer 113, the position of the contact hole 114 is defined by the photoresist, and the contact hole 114 is formed on the isolation oxide layer 113. Wherein, the first contact hole 114 is located on the first trench 105-1, and one end thereof penetrates through the second gate oxide 106-2 and contacts with the first polysilicon layer 107-1 arranged in the first trench 105-1; the second contact hole 114 is located between the first trench 105-1 and the second trench 105-2, and one end thereof penetrates through the second gate oxide layer 106-2 to be in contact with the second conductive type body region 111; the third contact hole 114 is located on a side of the second trench 105-2 away from the first trench 105-1, and has one end penetrating through the second gate oxide layer 106-2, the first conductive type source region 112 and the second conductive type body region 111.
Further, ion implantation is performed at the bottom of the contact hole, impurities are activated, and then filling of Ti/TiN and metal W is performed by using a sputtering process.
As shown in fig. 4P, a metal layer 115 is deposited on the isolation oxide layer 113, and then a source metal region and a gate metal region are defined by photolithography, and a source metal layer 115 and a gate metal layer 115 are defined by etching, so as to form an optimized structure profile of the periphery of the active region as shown in fig. 2A and the gate bus finger pick-up position as shown in fig. 2B.
Finally, a passivation layer 116 is formed over the metal layer 115.
It should be noted that the manufacturing method provided by the embodiment of the present invention bypasses the process challenge of the conventional structure, has a better control and operation process flow, can be well compatible with the manufacturing process of the existing Shield Gate Trench MOSFET device, and has a very high conversion value. Furthermore, the process can control the appearance of the IPO to be smooth, and reduce the dynamic parameters of the device, thereby reducing the switching loss at the application end.
In summary, the embodiment of the present invention provides a shielded gate MOSFET device structure and a manufacturing method thereof, where the manufacturing method includes: forming a second photoresist layer on the top of the first groove and one side of the first groove far away from the second groove, and etching the first gate oxide layer in the second groove and the first gate oxide layers on two sides of the top of the second groove by an etching method; removing the second photoresist layer, and forming a second gate oxide layer in the second trench, on two sides of the top of the second trench, on the top of the first trench and on two sides of the top of the first trench through a thermal oxidation process; forming a second polycrystalline silicon layer in the second groove and on the upper layer of the second gate oxide layer; forming a third photoresist layer on the top of the first groove, two sides of the top of the first groove, the top of the second groove and two sides of the top of the second groove; etching the second gate oxide layer and the first polysilicon layer in the second groove by an etching method; forming a second conductive type body region between the second groove and the first groove through ion implantation, and forming the second conductive type body region and a first conductive type source region on one side of the second groove far away from the first groove from bottom to top; and forming an isolation oxide layer above the second gate oxide layer, and preparing a contact hole on the isolation oxide layer. According to the preparation method, the third photoresist layer is arranged, and the triangular structure provided by the embodiment of the invention is formed by etching the first polysilicon layer, so that the optimization of the device structure is realized, and the aim of further reducing the dynamic parameters (such as gate charge Qg) of the device on the premise of not increasing the on-resistance is fulfilled, so that the optimal FOM of the device is reduced and the device has higher cost performance; the novel triangular SGT structure provided by the invention realizes the adjustment of dynamic parameters (such as gate charge Qg) of a device by properly adjusting the height of the first polycrystalline silicon layer, namely the top height of the first polycrystalline silicon layer is positioned in a range of +/-30% near the bottom height of the second polycrystalline silicon layer, so that the novel triangular SGT structure meets the requirements of more specific applications. Moreover, the third photoresist layer is arranged, so that the peripheral terminal trench is effectively protected, no gate poly residue is left in the process, and electric leakage caused by short circuit of a source electrode and a grid electrode is avoided; furthermore, the contact holes of the grid polysilicon layers on two sides in the groove are led out at the position of the gate bus finger pick-up of the device, and the leakage from the grid to the drain caused by the traditional arrangement of the contact holes in the middle position is effectively prevented.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A shielded gate MOSFET device structure, comprising:
a first groove and a second groove are arranged in the first conductive epitaxial layer;
the first groove comprises a first gate oxide layer and a first polycrystalline silicon layer from outside to inside;
the second groove is divided into an upper part and a lower part from bottom to top by a second gate oxide layer, the lower part of the second groove comprises a first gate oxide layer and a first polycrystalline silicon layer from outside to inside, and the upper part of the second groove comprises a second polycrystalline silicon layer, a second gate oxide layer and an isolation oxide layer from outside to inside;
a second gate oxide layer, an isolation oxide layer and a metal layer are sequentially arranged on the first conductive epitaxial layer;
contact holes are formed in the second groove, between the first groove and the second groove and on one side, far away from the first groove, of the second groove.
2. The shielded gate MOSFET device structure of claim 1 further comprising a second conductivity type body region and a first conductivity type source region;
a second conductive type body region is included between the first trench and the second trench;
one side of the second groove, which is far away from the first groove, comprises a second conductive type body region and a first conductive type source region from bottom to top;
wherein a lower surface of the second conductive type body region is higher than an upper surface of the first polysilicon layer located in the second trench.
3. The shielded gate MOSFET device structure of claim 2, wherein the contact holes are divided into a first contact hole, a second contact hole and a third contact hole;
the first contact hole is positioned on the first groove, and one end of the first contact hole penetrates through the second gate oxide layer and is in contact with the first polycrystalline silicon layer arranged in the first groove;
the second contact hole is positioned between the first groove and the second groove, and one end of the second contact hole penetrates through the second gate oxide layer and is in contact with the second conductive type body region;
the third contact hole is positioned on one side of the second groove far away from the first groove, and one end of the third contact hole penetrates through the second gate oxide layer and the first conduction type source region to be contacted with the second conduction type body region.
4. A method for manufacturing a shielded gate MOSFET device structure is characterized by comprising the following steps:
forming a second photoresist layer on the top of the first groove and one side of the first groove far away from the second groove, and etching the first gate oxide layer of the second groove and the first gate oxide layers on two sides of the top of the second groove by an etching method; removing the second photoresist layer, and forming a second gate oxide layer on the second groove, two sides of the top of the second groove, the top of the first groove and two sides of the top of the first groove through a thermal oxidation process;
forming a second polycrystalline silicon layer in the second groove and on the upper layer of the second gate oxide layer; forming a third photoresist layer on the top of the first groove, two sides of the top of the first groove, the top of the second groove and two sides of the top of the second groove; etching the second gate oxide layer and the first polycrystalline silicon layer in the second groove by an etching method;
forming a second conductive type body region between the second groove and the first groove by ion implantation, and forming the second conductive type body region and the first conductive type source region from bottom to top on one side of the second groove far away from the first groove; and forming an isolation oxide layer above the second gate oxide layer, and preparing a contact hole on the isolation oxide layer.
5. The method of claim 4, wherein before forming the second photoresist layer on the top of the first trench and on a side of the first trench remote from the second trench, further comprising:
removing the first oxide layer and the first photoresist layer on the first conductive epitaxial layer;
forming a first gate oxide layer in the first trench, on the top side of the first trench, in the second trench and on the top side of the second trench;
and forming a first polysilicon layer on the first gate oxide layer in the first trench, on the top side surface of the first trench, in the second trench and on the top side surface of the second trench.
6. The method of claim 5, wherein before forming the second photoresist layer on the top of the first trench and on a side of the first trench remote from the second trench, further comprising:
and removing the first polycrystalline silicon layer on the first conductive epitaxial layer by an etching method so that the upper surfaces of the first polycrystalline silicon layer in the first polycrystalline silicon layer and the second polycrystalline silicon layer in the first groove and the upper surface of the first gate oxide layer on the first conductive epitaxial layer have the same height.
7. The method according to claim 4, wherein the etching the first gate oxide layer in the second trench and the first gate oxide layers on two sides of the top of the second trench by an etching method specifically comprises:
etching the first gate oxide layer in the second groove, so that the upper part of the first gate oxide layer in the second groove is etched;
and etching the first gate oxide layers on two sides of the top of the second groove so as to etch the first gate oxide layers on two sides of the top of the second groove.
8. The preparation method of claim 4, wherein the etching of the second gate oxide layer and the first polysilicon layer in the second trench by the etching method specifically comprises:
and etching the second gate oxide layer and the first polycrystalline silicon layer in the second groove by an etching method so that the upper surface of the etched first polycrystalline silicon layer and the lower surface of the second polycrystalline silicon layer have the same height.
9. The method of claim 4, wherein prior to said passing, further comprising:
through a thermal oxidation process, the inner side of the second polycrystalline silicon layer positioned in the second groove is oxidized to generate a second gate oxide layer, and the upper surface of the first polycrystalline silicon layer is oxidized to generate the second gate oxide layer;
the second gate oxide layer positioned on the upper surface of the first polycrystalline silicon layer is contacted with the first gate oxide layer positioned below the second polycrystalline silicon layer.
10. The method according to claim 4, wherein the forming a body region of the second conductivity type between the second trench and the first trench and forming the body region of the second conductivity type and the source region of the first conductivity type from bottom to top on a side of the second trench far from the first trench by ion implantation specifically comprises:
forming a second conductive type body region between the second trench and the first trench on one side of the second trench far away from the first trench through first ion implantation, wherein the lower surface of the second conductive type body region is higher than the upper surface of the first polysilicon layer in the second trench;
and forming a first conductive type source region on one side of the second groove far away from the first groove by second ion implantation, wherein the first conductive type source region is positioned in the second conductive type body region, and the upper surface of the first conductive type source region and the upper surface of the first conductive type epitaxial layer have the same height.
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| CN109888003A (en) * | 2019-03-12 | 2019-06-14 | 电子科技大学 | A kind of power MOS (Metal Oxide Semiconductor) device of separate gate enhancing |
| US20200328302A1 (en) * | 2019-04-10 | 2020-10-15 | Mosel Vitelic Inc. | Mosfet and manufacturing method thereof |
| CN112687735A (en) * | 2019-10-14 | 2021-04-20 | 无锡先瞳半导体科技有限公司 | Shielding gate power device and preparation method thereof |
| CN114496762A (en) * | 2022-04-13 | 2022-05-13 | 杭州芯迈半导体技术有限公司 | Method for manufacturing trench MOSFET |
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| CN109888003A (en) * | 2019-03-12 | 2019-06-14 | 电子科技大学 | A kind of power MOS (Metal Oxide Semiconductor) device of separate gate enhancing |
| US20200328302A1 (en) * | 2019-04-10 | 2020-10-15 | Mosel Vitelic Inc. | Mosfet and manufacturing method thereof |
| CN112687735A (en) * | 2019-10-14 | 2021-04-20 | 无锡先瞳半导体科技有限公司 | Shielding gate power device and preparation method thereof |
| CN114496762A (en) * | 2022-04-13 | 2022-05-13 | 杭州芯迈半导体技术有限公司 | Method for manufacturing trench MOSFET |
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