CN115079477A - Driving substrate and display panel thereof - Google Patents
Driving substrate and display panel thereof Download PDFInfo
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- CN115079477A CN115079477A CN202210583551.XA CN202210583551A CN115079477A CN 115079477 A CN115079477 A CN 115079477A CN 202210583551 A CN202210583551 A CN 202210583551A CN 115079477 A CN115079477 A CN 115079477A
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- 239000000758 substrate Substances 0.000 title claims abstract description 103
- 239000010409 thin film Substances 0.000 claims description 288
- 239000003990 capacitor Substances 0.000 claims description 25
- 239000004973 liquid crystal related substance Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 20
- 239000010410 layer Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The application provides a drive base plate and display panel thereof, and the drive base plate includes substrate, many scanning lines, many data lines and scanning drive circuit. The substrate is provided with a display area; a plurality of scanning lines and a plurality of data lines are arranged on the substrate; the plurality of scanning lines and the plurality of data lines are crossed in a crisscross mode to define a plurality of pixel regions; and the pixel region is located in the display region; the row directions of the pixel regions are parallel to the scanning lines; the scanning driving circuit is arranged in a display area of the substrate and comprises a plurality of cascaded scanning driving units; the same scanning driving unit is arranged in at least two rows of pixel areas and can output at least one row of grid scanning signals. According to the pixel opening ratio is improved by dispersedly arranging the single scanning driving unit in the display area in the multi-row pixel area, so that the space occupied by the scanning driving unit in the single-row pixel area is reduced.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a driving substrate and a display panel thereof.
Background
With the increasing demand of people for the taste of the display, the demand of the borderless display is higher and higher at present. The display in the prior art includes non-display areas on the upper, lower, left, and right sides, wherein the left and right non-display areas are mainly occupied by a Gate Driver on Array (GOA) circuit, so that the left and right frames cannot be frameless.
In this regard, the conventional method is to place the GOA circuits of the current row in the pixel display areas of the corresponding row. However, the GOA circuit is disposed in the display area, which greatly reduces the aperture ratio of the pixels, thereby causing the problem of insufficient brightness of the lcd.
Disclosure of Invention
The technical problem that this application mainly solved provides a drive base plate and display panel thereof, places the GOA circuit in the pixel display area among the solution prior art for the problem that pixel aperture ratio reduces.
In order to solve the above technical problem, a first technical solution provided by the present application is: a driving substrate for a liquid crystal display panel is provided, the driving substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a scan driving circuit. The substrate is provided with a display area; the plurality of scanning lines and the plurality of data lines are arranged on the substrate; the plurality of scanning lines and the plurality of data lines are crossed in a crisscross mode to define a plurality of pixel regions; and the pixel region is located in the display region; the row directions of the pixel regions are parallel to the scanning lines; the scanning driving circuit is arranged in a display area of the substrate and comprises a plurality of cascaded scanning driving units; the same scanning driving unit is arranged in at least two rows of pixel areas and can output at least one row of grid scanning signals.
The scanning driving unit comprises a charging unit, a resetting unit and an output unit; the output unit is positioned in one row or two rows of pixel areas, and the charging unit and the reset unit are positioned in the other row of pixel areas; or the output unit, the charging unit and the reset unit are respectively located in a row of pixel regions.
The scanning driving unit comprises a plurality of thin film transistors which are arranged in two rows or three rows of pixel areas in a dispersed mode.
The output unit comprises a switch thin film transistor, a single switch thin film transistor comprises a plurality of sub thin film transistors, and the plurality of sub thin film transistors are connected in parallel and are dispersedly arranged in at least two rows of pixel areas.
The output unit comprises a switch thin film transistor which is connected with a plurality of scanning lines, so that the scanning driving unit can output a plurality of rows of grid scanning signals at the same time.
The scanning driving unit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a capacitor C;
the source electrode of the first thin film transistor is connected with the drain electrode of the first thin film transistor and is connected with the output end of the grid scanning signal of the previous stage, and the drain electrode of the first thin film transistor is respectively connected with the source electrode of the fourth thin film transistor and the grid electrode of the second thin film transistor;
the source electrode of the second thin film transistor is connected with a clock signal, and the drain electrode of the second thin film transistor is connected with at least one scanning line to output at least one row of grid scanning signals;
the grid electrodes of the third thin film transistor and the fourth thin film transistor are connected with the same scanning line, and the source electrode of the third thin film transistor and the drain electrode of the second thin film transistor are connected with the same scanning line; the drain electrode of the third thin film transistor and the drain electrode of the fourth thin film transistor are respectively connected with a low level signal;
the capacitor C is respectively connected with the grid electrode of the second thin film transistor and the drain electrode of the second thin film transistor; the grid electrode of the first thin film transistor, the drain electrode of the second thin film transistor and the grid electrode of the third thin film transistor are respectively connected with different scanning lines.
The drain electrode of the second thin film transistor is respectively connected with the scanning line of the nth row and the scanning line of the (n + 1) th row so as to simultaneously output the grid scanning signal of the nth row and the grid scanning signal of the (n + 1) th row; the grid electrodes of the third thin film transistor and the fourth thin film transistor are respectively connected with the scanning lines of the (n + 2) th row; n is an integer of 1 or more.
The display device further comprises a clock signal line for providing a clock signal and a low-level signal line for providing a low-level signal, wherein the clock signal line and the data line are arranged at intervals along the extension direction of the data line, and the clock signal line is connected with the source electrode of the second thin film transistor; the low-level signal line is arranged at an interval with the data line along the extending direction of the data line, and the low-level signal line is respectively connected with the drain electrode of the third thin film transistor and the drain electrode of the fourth thin film transistor.
Wherein the same scan drive unit is arranged in at least two rows of pixel regions
In order to solve the above technical problem, a second technical solution provided by the present application is: a display panel is provided, which includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate is the driving substrate; the first substrate and the second substrate are oppositely arranged; the liquid crystal layer is arranged between the first substrate and the second substrate.
The beneficial effect of this application: being different from the prior art, the application provides a driving substrate and a display panel thereof, and the driving substrate comprises a substrate, a plurality of scanning lines, a plurality of data lines and a scanning driving circuit. The substrate is provided with a display area; a plurality of scanning lines and a plurality of data lines are arranged on the substrate; the plurality of scanning lines and the plurality of data lines are crossed in a crisscross mode to define a plurality of pixel regions; and the pixel region is located in the display region; the row directions of the pixel regions are parallel to the scanning lines; the scanning driving circuit is arranged in the display area of the substrate and comprises a plurality of cascaded scanning driving units; the same scanning driving unit is arranged in at least two rows of pixel areas and can output at least one row of grid scanning signals. According to the pixel opening ratio is improved by dispersedly arranging the single scanning driving unit in the display area in the multi-row pixel area, so that the space occupied by the scanning driving unit in the single-row pixel area is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without any inventive work.
Fig. 1 is a schematic structural diagram of an embodiment of a display panel provided in the present application;
FIG. 2 is a schematic structural diagram of an embodiment of a driving substrate provided in the present application;
FIG. 3 is a schematic diagram of a cascade structure of an embodiment of a scan driving circuit provided in the present application;
fig. 4 is a schematic structural diagram of a first embodiment of a scan driving unit in a driving substrate provided in the present application;
FIG. 5 is a schematic structural diagram of a second embodiment of a scan driving unit in a driving substrate provided in the present application;
fig. 6 is a schematic structural diagram of a third embodiment of a scan driving unit in a driving substrate provided in the present application;
fig. 7 is a schematic structural diagram of a fourth embodiment of a scan driving unit in a driving substrate provided in the present application;
fig. 8 is a schematic structural diagram of a fifth embodiment of a scan driving unit in a driving substrate provided in the present application;
fig. 9 is a schematic structural diagram of a sixth embodiment of a scan driving unit in a driving substrate provided in the present application;
fig. 10 is a schematic structural diagram of another embodiment of a driving substrate provided in the present application.
The reference numbers illustrate:
a first substrate-1, a first substrate-11, a display region-111, a non-display region-112, a scan line-12, a data line-13, a pixel electrode-14, a scan driving circuit-15, a scan driving unit-150, a charging unit-151, a reset unit-152, an output unit-153, a first thin film transistor-T 1 A second thin film transistor-T 2 A first sub-thin film transistor-T 2-1 Second sub-thin film transistor-T 2-2 A third thin film transistor-T 3 And a fourth thin film transistor-T 4 The fifth thin film transistor-T 5 And a sixth thin film transistor-T 6 The seventh thin film transistor-T 7 The eighth thin film transistor-T 8 A capacitor-C, a clock signal line-CLK/CLKB, a low level signal line-Vss, a pixel region-17, a second substrate-2, a second substrate-21, a filter layer-22, a black matrix layer-23, a liquid crystal layer-3, a liquid crystal-31, a driverSubstrate-4, display panel-100.
Detailed Description
The following describes in detail the embodiments of the present application with reference to the drawings attached hereto.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present application.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or regions is not limited to the listed steps or regions but may alternatively include additional steps or regions not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a display panel provided in the present application.
The display panel 100 is a liquid crystal panel. The display panel 100 includes a first substrate 1, a second substrate 2, and a liquid crystal layer 3. The first substrate 1 and the second substrate 2 are oppositely arranged, and the first substrate 1 and the second substrate 2 clamp the liquid crystal layer 3 positioned in the spacing space of the first substrate 1 and the second substrate 2.
One of the first substrate 1 and the second substrate 2 is an array substrate, and the other is a color film substrate. In this embodiment, the first substrate 1 is an array substrate, and the second substrate 2 is a color filter substrate.
The second substrate 2, that is, the color filter substrate, includes a second substrate 21, a filter layer 22 and a black matrix layer 23 on one side of the second substrate 21 close to the array substrate. The filter layer 22 includes filters of three colors of red, blue, and green. The black matrix layer 23 can separate the three primary colors of red, green, and blue in the filter layer 22 by means of a material having a high light-shielding property, and prevent light leakage, thereby contributing to improvement of the contrast of each color block. The filter layer 22 can realize full color display of the display panel 100. The material of the second substrate 21 is typically alkali-free borosilicate glass with excellent mechanical properties, heat resistance and chemical resistance. The color film substrate may further include other functional layers, which are the same as or similar to those in the prior art, and are not limited herein.
The liquid crystal layer 3 includes a liquid crystal 31, and the liquid crystal 31 functions like a light valve in the display, and can control the brightness of the transmitted light, thereby achieving the effect of information display.
Referring to fig. 1 and fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a driving substrate provided in the present application.
The first substrate 1 in this embodiment may be a driving substrate 4, and the driving substrate 4 includes a first substrate 11, a scanning line 12, a data line 13, a pixel electrode 14, a scanning driving circuit 15, a clock signal line CLK, and a low-level signal line Vss. The first substrate 11 has a display region 111 and a non-display region 112. The first substrate 11 is made of alkali-free borosilicate glass with excellent mechanical properties, heat resistance and chemical resistance. The plurality of scan lines 12 and the plurality of data lines 13 are disposed on a side of the first substrate 11 adjacent to the second substrate 2. The plurality of scanning lines 12 are disposed parallel to each other, and the plurality of data lines 13 are disposed parallel to each other. The plurality of scanning lines 12 and the plurality of data lines 13 intersect vertically and horizontally to define a plurality of pixel regions 17, and pixel electrodes 14 are arranged in the pixel regions 17. The scan driving circuit 15 is disposed in the display region 111 of the first substrate 11, connected to the scan lines 12, and configured to output gate scan signals. The low-level signal line Vss is for supplying a low-level signal, and the low-level signal line Vss is disposed apart from the data lines 13 along the extending direction of the data lines 13. The clock signal line CLK is used to supply a clock signal, and the voltage of the low-level signal line Vss and the clock signal line CLK are opposite in phase. The clock signal line CLK is disposed at an interval from the data line 13 along the extending direction of the data line 13.
In the embodiment of the present application, the row direction of the pixel region 17 is parallel to the scanning line 12. That is, each row of the pixel regions 17 includes a plurality of pixel regions 17 therein, and the plurality of pixel regions 17 of each row are sequentially arranged in a direction parallel to the scanning lines 12. Each pixel region 17 includes at least one pixel electrode 14. That is, there may be one pixel electrode 14 in one pixel region 17 or there may be a plurality of pixel electrodes 14, for example, in a dual gate driving circuit, there are two pixel electrodes 14 in one pixel region 17, and the two pixel electrodes 14 may be disposed at intervals along the extending direction of the data line 13 or the scan line 12, which is not limited herein. In this embodiment, a description will be given mainly taking an embodiment in which one pixel electrode 14 is included in one pixel region 17.
Referring to fig. 3, fig. 3 is a schematic diagram of a cascade structure of a scan driving circuit according to an embodiment of the present disclosure.
The scan driving circuit 15 is disposed on a side of the first substrate 1 close to the second substrate 2, and is connected to the scan lines 12, the clock signal lines CLK, and the low-level signal lines Vss, respectively. The orthographic projection of the black matrix layer 23 on the first substrate 1 covers the scanning drive circuit 15 so as not to affect the transmission of light from the opening area. The scan driving circuit 15 includes a plurality of scan driving units 150 cascaded, an Input signal (Input) of each stage of the scan driving unit 150 is an output signal (Ouput) of a previous stage of the scan driving unit 150, and a Reset signal (Reset) of each stage of the scan driving unit 150 is an output signal of a next stage of the scan driving unit 150. For the first stage scan driving unit 150, since there is no previous stage scan driving unit 150, a frame start signal (not shown) is used as an input signal. For the last stage scan driving unit 150, since no next stage scan driving unit 150 provides the reset signal, a redundant scan driving unit (not shown) may be additionally designed, which provides the reset signal to the last row.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a first embodiment of a scan driving unit in a driving substrate according to the present application.
Each of the scan driving units 150 includes a charging unit 151, a reset unit 152, an output unit 153, and at least one capacitor C. The charging unit 151 is configured to receive an output signal of the previous stage scan driving unit 150 and charge the capacitor C. The reset unit 152 receives an output signal of the next-stage scan driving unit 150, and discharges the capacitor C, thereby resetting the current-stage scan driving unit 150. The output unit 153 is used for outputting gate scanning signals to the scanning lines 12. The charging unit 151, the reset unit 152, and the output unit 153 each include a thin film transistor. That is, each of the scan driving units 150 includes a plurality of thin film transistors and at least one capacitor C.
The same scan driving unit 150 is disposed in at least two rows of pixel regions 17 and can simultaneously output at least one row of gate scan signals. That is, a plurality of thin film transistors are dispersedly disposed in at least two rows of the pixel regions 17, and the output unit 153 is connected to at least one scan line 12.
The following description will be given taking an example in which the single scan driving unit 150 includes four thin film transistors and one capacitor C.
Scanning driving sheetThe cell 150 includes a first thin film transistor T 1 A second thin film transistor T 2 A third thin film transistor T 3 A fourth thin film transistor T 4 And a capacitor C, a first thin film transistor T 1 A second thin film transistor T as a charging unit 151 2 A third thin film transistor T as an output unit 153 3 And a fourth thin film transistor T 4 Is a reset unit 152.
A first thin film transistor T 1 Gate electrode of and the first thin film transistor T 1 Is connected to the n-1(n is an integer of 1 or more) th row scanning line 12, that is, to the gate scanning signal output terminal of the previous stage, and the first thin film transistor T 1 Respectively with the fourth thin film transistor T 4 And a second thin film transistor T 2 Is connected to the gate of (a). A second thin film transistor T 2 Is connected to a clock signal line CLK to receive a clock signal, a second thin film transistor T 2 Is connected to the scanning line 12 of the nth row to output the gate scanning signal of the scanning line 12 of the nth row. Third thin film transistor T 3 And a fourth thin film transistor T 4 The gate electrodes of the first and second thin film transistors are respectively connected with the (n + 1) th scanning line 12 and the third thin film transistor T 3 Is connected to the scanning line 12 of the nth row. Third thin film transistor T 3 And a fourth thin film transistor T 4 Are connected to the low-level signal lines Vss, respectively. The capacitor C is connected to the second thin film transistor T 2 And a second thin film transistor T 2 Is connected to the drain of (1). In this embodiment, the first thin film transistor T is in the same scan driving unit 150 1 Gate electrode of the first thin film transistor, and the second thin film transistor T 2 And the third thin film transistor T 3 Respectively connected to different scanning lines 12, and a third thin film transistor T 3 And a fourth thin film transistor T 4 The grid of the first TFT is connected to the same scan line 12, and the third TFT T 3 Source electrode of and the second thin film transistor T 2 Are connected to the same scan line 12.
In the present embodiment, the scan driving unit 150 outputs only the gate scan signal of the scan line 12 of the nth row. A first thin film transistor T 1 A second thin film transistor T 2 And a third thin film transistor T 3 The pixel regions 17 in the nth row, i.e., the charging unit 151 and the reset unit 152, are located in the pixel regions 17 in another row. A second thin film transistor T 2 The pixel regions 17 located at the n +1 th row, that is, the output units 153 are located in the pixel regions 17 of one row. The single scan driving unit 150 is disposed in the two rows of pixel regions 17 such that the space occupied by the single scan driving unit 150 in the single row of pixel regions 17 is reduced by more than half, thereby facilitating an increase in the pixel aperture ratio. Third thin film transistor T 3 And a fourth thin film transistor T 4 Pixel regions 17 in the same column, first thin film transistors T 1 A second thin film transistor T 2 And a third thin film transistor T 3 In pixel regions 17 of different columns. That is, the single scan driving unit 150 is disposed in the plurality of columns of pixel regions 17, so that the space occupied by the single scan driving unit 150 in the single column of pixel regions 17 is reduced, thereby contributing to an increase in the pixel aperture ratio. Optionally, a first thin film transistor T 1 A second thin film transistor T 2 And a third thin film transistor T 3 Or in different rows of pixel regions 17, and a third TFT T 3 And a fourth thin film transistor T 4 Or may be located in different columns of pixel regions 17. That is, a single scan driving unit 150 may be located in a plurality of rows of pixel regions 17 or a plurality of columns of pixel regions 17, and the thin film transistors in each scan driving unit 150 are distributed in different rows of pixel regions 17 in various ways, so that the space occupied by the scan driving unit 150 in each row of pixel regions 17 is as small as possible.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a second embodiment of a scan driving unit in a driving substrate according to the present application.
In one embodiment, the single scan driving unit 150 may output at least two rows of gate scan signals at the same time. A second thin film transistor T 2 Respectively, to the nth row scan line 12 and the n +1 th row scan line 12 to simultaneously output gate scan signals of the nth row scan line 12 and the n +1 th row scan line 12. Third thin film transistor T 3 And the fourth filmFilm transistor T 4 The gate electrodes of the first and second thin film transistors are respectively connected with the n +2 th scanning line 12 and the third thin film transistor T 3 Is connected to the scanning line 12 of the nth row and the scanning line 12 of the (n + 1) th row, respectively. In the present embodiment, the scan driving unit 150 outputs two rows of gate scan signals simultaneously, and the second thin film transistor T 2 And is located in the pixel region 17 between the nth row scanning line 12 and the (n + 1) th row scanning line 12 so as to be electrically connected to the nth row scanning line 12 and the (n + 1) th row scanning line 12. Optionally, a second thin film transistor T 2 May be connected to more than two scan lines 12 to simultaneously output a plurality of rows of gate scan signals.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a third embodiment of a scan driving unit in a driving substrate according to the present application.
In an embodiment, a single thin film transistor with a large volume is split into a plurality of sub-thin film transistors, and the plurality of sub-thin film transistors are connected in parallel and are dispersedly disposed in at least two rows of pixel regions 17, so as to reduce the space occupied by the single thin film transistor in one row of pixel regions 17 and increase the aperture ratio of the pixel. In this embodiment, the second thin film transistor T 2 Splitting into two sub-thin film transistors. The two sub-thin film transistors are connected in parallel. The two sub-TFTs are respectively the first sub-TFT T 2-1 And a second sub-thin film transistor T 2-2 . First sub-thin film transistor T 2-1 And a second sub-thin film transistor T 2-2 And the drains of the capacitors are respectively connected with the nth row scanning line 12 and also respectively connected with one end of the capacitor C to output the gate scanning signal of the nth row scanning line 12. First sub-thin film transistor T 2-1 And a second sub thin film transistor T 2-2 The grid electrodes of the first and second thin film transistors are respectively connected with the first and second thin film transistors T 1 And the drain electrodes of (1) are also respectively connected with the other end of the capacitor C. First sub-thin film transistor T 2-1 And a second sub-thin film transistor T 2-2 Are respectively connected to the clock signal lines CLK. Third thin film transistor T 3 And a fourth thin film transistor T 4 The gate electrodes of the first and second thin film transistors are respectively connected with the (n + 1) th scanning line 12 and the third thin film transistor T 3 Is connected to the scanning line 12 of the nth row. First sub-thin film transistor T 2-1 And a second sub-thin film transistor T 2-2 In pixel regions 17 of different rows and in pixel regions 17 of the same column. Alternatively, the sub-tfts may be located in the pixel regions 17 in the same row, or in the pixel regions 17 in different columns, and the design is not limited herein. A second thin film transistor T 2 Is a switching thin film transistor in the output unit 153, and the volume of a single switching thin film transistor is larger than that of a single thin film transistor in the charging unit 151 and the reset unit 152. Splitting the switching tfts may reduce the space occupied by individual tfts in a row of pixel areas 17 to a greater extent. Alternatively, the single thin film transistors in the charging unit 151 and the resetting unit 152 may be separated, and the design is not limited herein and is designed according to actual requirements.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a fourth embodiment of a scan driving unit in a driving substrate according to the present application.
In one embodiment, the first sub-TFT T 2-1 And a second sub-thin film transistor T 2-2 Of the same volume, a third thin film transistor T 3 And a fourth thin film transistor T 4 The gate electrodes of the first and second thin film transistors are respectively connected with the n +2 th scanning line 12 and the third thin film transistor T 3 Is connected to the scanning line 12 of the nth row and is connected to one end of the capacitor C. First sub-thin film transistor T 2-1 Is connected with the scanning line 12 of the nth row, and the second sub thin film transistor T 2-2 Is connected to the scan line 12 of the (n + 1) th row. One end of the capacitor C is connected with the first sub-thin film transistor T respectively 2-1 And a second sub-thin film transistor T 2-2 The other end of the capacitor C is connected with only the first sub-thin film transistor T 2-1 Of the substrate. In the present embodiment, the first sub-thin film transistor T 2-1 A second sub-thin film transistor T for outputting a gate scanning signal to the scanning line 12 of the nth row 2-2 The gate scanning signal is output to the n +1 th row scanning line 12. Optionally, one end of the capacitor C is connected to the first sub-thin film transistor T respectively 2-1 And a second sub-thin film transistor T 2-2 The other end of the capacitor C is connected with only the first sub-thin film transistor T 2-1 Of the substrate. Second sub-thin film transistorT 2-2 And the first sub-thin film transistor T 2-1 Is connected with the n-th row scanning line 12 and the first sub thin film transistor T 2-1 And a second sub thin film transistor T 2-2 The scanning lines 12 in the nth row are collectively output gate scanning signals.
In another embodiment, the first sub-thin film transistor T 2-1 And a second sub-thin film transistor T 2-2 Of the first sub-thin film transistor T 2-1 Is larger than the second sub-thin film transistor T 2-2 The volume of (a); first sub-thin film transistor T 2-1 Controlling the charging of the pixels in the nth row to a preset value, and controlling the second sub-thin film transistor T 2-2 And controlling the pixels in the (n + 1) th row to be precharged, wherein the precharged grid voltage can be lower a little, and the electricity is saved.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a fifth embodiment of a scan driving unit in a driving substrate according to the present application.
In one embodiment, the scan driving unit 150 includes six thin film transistors and one capacitor C. Six thin film transistors are respectively the first thin film transistor T 1 A second thin film transistor T 2 A third thin film transistor T 3 A fourth thin film transistor T 4 A fifth thin film transistor T 5 And a sixth thin film transistor T 6 . A first thin film transistor T 1 A second thin film transistor T as a charging unit 151 2 Is an output unit 153, a third thin film transistor T 3 And a fourth thin film transistor T 4 Is a reset unit 152, a fifth thin film transistor T 5 And a sixth thin film transistor T 6 Compared with the scan driving unit 150 including four thin film transistors and one capacitor C, the reset unit 152 of the scan driving unit 150 in this embodiment is increased from one to two, and a clock signal line CLKB is also added, and the voltage phases of the clock signal line CLK and the clock signal line CLKB are opposite. The clock signal line CLK and the clock signal line CLKB are disposed perpendicularly to each other, and the clock signal line CLK is parallel to the low-level signal line Vss. A first thin film transistor T 1 Is connected with the gate and the source and is connected with the scanning line 12 of the n-1 th row, a first thin film transistor T 1 Respectively with the second thin film transistor T 2 And a sixth thin film transistor T 6 Is also connected with the fourth thin film transistor T 4 Is connected to the source of (a). A second thin film transistor T 2 Is connected with the clock signal line CLK, a second thin film transistor T 2 Is connected to the scanning line 12 of the nth row to output the gate scanning signal of the scanning line 12 of the nth row. Third thin film transistor T 3 Respectively with the fifth thin film transistor T 5 And a sixth thin film transistor T 6 Of the third thin film transistor T 3 Is connected to a low level signal line Vss, and a third thin film transistor T 3 Is connected to the scanning line 12 of the nth row. Fourth thin film transistor T 4 Respectively with the fifth thin film transistor T 5 And a sixth thin film transistor T 6 Of the fourth thin film transistor T 4 Is connected to the low-level signal line Vss. Fifth thin film transistor T 5 And a sixth thin film transistor T 6 Series, fifth thin film transistor T 5 Is connected to the gate and to a clock signal line CLKB. Sixth thin film transistor T 6 Is connected to the low-level signal line Vss. Two ends of the capacitor C are respectively connected with the second thin film transistor T 2 A gate and a drain. In the present embodiment, the first thin film transistor T 1 And a second thin film transistor T 2 A fifth TFT T in the pixel region 17 of the nth row 5 A third thin film transistor T in the pixel region 17 of the (n + 1) th row 3 A fourth thin film transistor T 4 And a sixth thin film transistor T 6 And a pixel region 17 located at the n +2 th row. The scan driving unit 150 is disposed in three different rows of the pixel regions 17. That is, the charging unit 151 and the output unit 153 are located in the pixel region 17 of one row, and the reset unit 152 is located in the pixel region 17 of a different row from the charging unit 151 and the output unit 153, respectively. Alternatively, the reset unit 152, the charging unit 151, and the output unit 153 may be each located in the pixel region 17 of a different row.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a sixth embodiment of a scan driving unit in a driving substrate according to the present application.
In one embodiment, the scan driving unit 150 includes eight thin film transistors and one capacitor C. Eight thin film transistors are respectively the first thin film transistor T 1 A second thin film transistor T 2 A third thin film transistor T 3 A fourth thin film transistor T 4 A fifth thin film transistor T 5 And a sixth thin film transistor T 6 And a seventh thin film transistor T 7 And an eighth thin film transistor T 8 . A first thin film transistor T 1 A second thin film transistor T as a charging unit 151 2 Is an output unit 153, a third thin film transistor T 3 And a seventh thin film transistor T 7 Is a reset unit 152, a fifth thin film transistor T 5 And a sixth thin film transistor T 6 Is a reset unit 152, an eighth thin film transistor T 8 And a fourth thin film transistor T 4 Is a reset unit 152. Compared with the scan driving unit 150 including four thin film transistors and one capacitor C, the reset unit 152 of the scan driving unit 150 in this embodiment is increased from one to three, and a clock signal line CLKB is also added, the voltage phases of the clock signal line CLK and the clock signal line CLKB are opposite, and the clock signal line CLK, the clock signal line CLKB, and the low-level signal line Vss are respectively disposed in parallel to the scan lines 12. A first thin film transistor T 1 Is connected with the gate and the source and is connected with the scanning line 12 of the n-1 th row, a first thin film transistor T 1 Respectively with the third thin film transistor T 3 And a seventh thin film transistor T 7 Is connected to the source of the first thin film transistor T 1 And a second thin film transistor T 2 And a sixth thin film transistor T 6 Is connected to the gate of (a). A second thin film transistor T 2 Is connected with the clock signal line CLK, a second thin film transistor T 2 Is connected to the scanning line 12 of the nth row to output the scanning gate signal of the scanning line 12 of the nth row. Third thin film transistor T 3 And a seventh thin film transistor T 7 Parallel, third thin film transistor T 3 Respectively with the eighth thin film transistor T 8 Gate electrode of and a sixth thin film transistor T 6 Of the third thin film transistor T 3 And the seventh thin film transistor T 7 Is connected to the n +1 th row scanning line 12, and a third thin film transistor T 3 Source electrode of and the seventh thin film transistor T 7 Is connected to the source of (a). Fifth thin film transistor T 5 And a sixth thin film transistor T 6 Series, fifth thin film transistor T 5 Is connected to the gate and the clock signal line CLKB, a fifth thin film transistor T 5 And a sixth thin film transistor T 6 Is connected to the source of (a). Sixth thin film transistor T 6 Gate electrode of and the second thin film transistor T 2 Is connected to the gate of the sixth thin film transistor T 6 Is connected to the low level signal line Vss, and a sixth thin film transistor T 6 Source electrode of and the third thin film transistor T 3 And an eighth thin film transistor T 8 Is connected to the gate of (a). Eighth thin film transistor T 8 And a fourth thin film transistor T 4 Parallel connection, eighth thin film transistor T 8 And a fourth thin film transistor T 4 Is connected to the n-th row scanning line 12, and an eighth thin film transistor T 8 And a fourth thin film transistor T 4 And is connected to the low-level signal line Vss. Fourth thin film transistor T 4 Is connected to the (n + 1) th row scanning line 12. Two ends of the capacitor C are respectively connected with the second thin film transistor T 2 A gate and a drain. In the present embodiment, the first thin film transistor T 1 A second thin film transistor T 2 And a fifth thin film transistor T 5 A third TFT T in the pixel region 17 of the n-th row 3 A fourth thin film transistor T 4 And a sixth thin film transistor T 6 And a seventh thin film transistor T 7 And an eighth thin film transistor T 8 And is located in the (n + 1) th row of pixel regions 17. The scan driving unit 150 is disposed in two different rows of the pixel regions 17.
Referring to fig. 4 and 10, fig. 10 is a schematic structural diagram of another embodiment of a driving substrate provided in the present application.
In an embodiment, the same row of scan lines 12 may be divided into multiple segments for driving, and each segment of scan line 12 may also be driven by one or two scan driving units 150, so as to reduce the load of driving. In the present embodiment, all the scanning lines 12 are divided into two parts along the extending direction of the scanning lines 12, the segmented positions of each row of the scanning lines 12 are the same, one scanning driving unit 150 is arranged in each row of the pixel regions 17 in each part of the scanning lines 12, the scanning driving units 150 are dispersed in two rows of the pixel regions 17, and the row pitches and the column pitches of all the pixel electrodes 14 are the same. Each of the scanning lines 12 includes a clock signal line CLK and a low-level signal line Vss. Alternatively, the segment positions of the scanning lines 12 may be different, the number of segments of the scanning lines 12 may be different, and the number of scan driving units 150 of each scanning line 12 may be different. The design is not limited to the above and is designed according to actual conditions.
The application provides a drive base plate, and the drive base plate includes substrate, many scanning lines, many data lines and scanning drive circuit. The substrate is provided with a display area; a plurality of scanning lines and a plurality of data lines are arranged on the substrate; the plurality of scanning lines and the plurality of data lines are crossed in a crisscross mode to define a plurality of pixel regions; and the pixel region is located in the display region; the row directions of the pixel regions are parallel to the scanning lines; the scanning driving circuit is arranged in the display area of the substrate and comprises a plurality of cascaded scanning driving units; the same scanning driving unit is arranged in at least two rows of pixel areas and can output at least one row of grid scanning signals. According to the pixel opening ratio is improved by dispersedly arranging the single scanning driving unit in the display area in the multi-row pixel area, so that the space occupied by the scanning driving unit in the single-row pixel area is reduced.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings are included in the scope of the present disclosure.
Claims (10)
1. A driving substrate for a liquid crystal display panel, comprising:
a substrate having a display area;
a plurality of scan lines and a plurality of data lines disposed on the substrate; the plurality of scanning lines and the plurality of data lines are crossed in a crisscross mode to define a plurality of pixel regions; and the pixel region is located in the display region; wherein the row direction of the plurality of pixel regions is parallel to the scanning line;
the scanning driving circuit is arranged in a display area of the substrate and comprises a plurality of cascaded scanning driving units;
the scanning driving unit is arranged in the pixel regions of at least two rows and can output at least one row of grid scanning signals.
2. The driving substrate according to claim 1, wherein the scanning driving unit includes a charging unit, a reset unit, and an output unit; the output unit is located in one or two rows of the pixel regions, and the charging unit and the reset unit are located in the other row of the pixel regions; or the output unit, the charging unit and the reset unit are respectively located in one row of the pixel regions.
3. The driving substrate according to claim 1, wherein the scanning driving unit includes a plurality of thin film transistors dispersedly disposed in two or three rows of the pixel regions.
4. The driving substrate according to claim 2, wherein the output unit comprises switching thin film transistors, and a single switching thin film transistor comprises a plurality of sub thin film transistors, and the plurality of sub thin film transistors are connected in parallel and distributed in at least two rows of the pixel regions.
5. The driving substrate according to claim 2, wherein the output unit includes a switching thin film transistor connected to the plurality of scan lines such that the scan driving unit outputs the plurality of rows of the gate scan signals at the same time.
6. The driving substrate according to claim 2, wherein the scan driving unit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a capacitor C;
the source electrode of the first thin film transistor is connected with the drain electrode of the first thin film transistor and is connected with the output end of the grid scanning signal of the previous stage, and the drain electrode of the first thin film transistor is respectively connected with the source electrode of the fourth thin film transistor and the grid electrode of the second thin film transistor;
a source electrode of the second thin film transistor is connected with a clock signal, and a drain electrode of the second thin film transistor is connected with at least one scanning line to output at least one row of the grid scanning signals;
the grid electrodes of the third thin film transistor and the fourth thin film transistor are connected with the same scanning line, and the source electrode of the third thin film transistor is connected with the same scanning line as the drain electrode of the second thin film transistor; the drain electrode of the third thin film transistor and the drain electrode of the fourth thin film transistor are respectively connected with a low-level signal;
the capacitor is respectively connected with the grid electrode of the second thin film transistor and the drain electrode of the second thin film transistor;
the grid electrode of the first thin film transistor, the drain electrode of the second thin film transistor and the grid electrode of the third thin film transistor are respectively connected with different scanning lines.
7. The driving substrate according to claim 6, wherein a drain of the second thin film transistor is connected to the scan line of an nth row and the scan line of an n +1 th row, respectively, to simultaneously output the gate scan signal of the nth row and the gate scan signal of the n +1 th row; the grid electrodes of the third thin film transistor and the fourth thin film transistor are respectively connected with the scanning line of the (n + 2) th row; n is an integer of 1 or more.
8. The driving substrate according to claim 6, further comprising a clock signal line for supplying the clock signal and a low-level signal line for supplying the low-level signal, wherein the clock signal line is disposed apart from the data line in an extending direction of the data line, and the clock signal line is connected to a source of the second thin film transistor; the low-level signal line is arranged at an interval with the data line along the extending direction of the data line, and the low-level signal line is respectively connected with the drain electrode of the third thin film transistor and the drain electrode of the fourth thin film transistor.
9. The driving substrate of claim 1, wherein the same scan driving unit is disposed in at least two rows of the pixel regions.
10. A display panel, comprising:
a first substrate; the first substrate is the driving substrate of any one of claims 1 to 9;
a second substrate disposed opposite to the first substrate;
and the liquid crystal layer is arranged between the first substrate and the second substrate.
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