CN104934005A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN104934005A CN104934005A CN201510379531.0A CN201510379531A CN104934005A CN 104934005 A CN104934005 A CN 104934005A CN 201510379531 A CN201510379531 A CN 201510379531A CN 104934005 A CN104934005 A CN 104934005A
- Authority
- CN
- China
- Prior art keywords
- pole
- grid line
- transistor
- connects
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a display panel and a display device, belongs to the display technology field, and helps to solve the problem that the frame of a conventional display panel is wide. The display panel comprises a display area and surrounding areas. The display area includes multiple grid lines and multiple data lines, the grid lines and the data lines crossing each other. The grid lines and the data lines cross each other to define multiple pixel units. At least one grid line includes at least two grid line segments that are disconnected from each other, and each grid line segment correspondingly controls at least one pixel unit. The display area is divided into at least two sub-display areas according to the disconnection positions of the grid line segments. A shift register unit connected to the grid line segments is arranged in at least one sub-display area, and is used for providing grid scan signals to the grid line segments connected to the shift register unit. At least part of the shift register units are arranged in the display area, so the frame of the display panel is narrow.
Description
Technical field
The invention belongs to display technique field, be specifically related to a kind of display panel and display device.
Background technology
TFT-LCD (Thin Film Transistor-Liquid Crystal Display, thin-film transistor LCD device) ultimate principle that realizes a frame picture display is driven by grid (gate) to carry out gating to the square wave of every one-row pixels input one fixed width successively from top to bottom, then drives the signal needed for every one-row pixels to export from top to bottom successively by source electrode (source).Normally gate driver circuit and source electrode drive circuit pass through COF (Chip On Film to the display device of a kind of like this structure of current manufacture, cover brilliant film) or COG (Chip On Glass, chip is directly fixed on glass) technique makes on glass panels, but when resolution is higher, the output of gate driver circuit and source electrode drive circuit is all more, the length of driving circuit also will increase, and this will be unfavorable for pressure welding (Bonding) technique of module driving circuit.
In order to overcome above problem, the manufacture of existing display device adopts the design of GOA (GateDrive On Array) circuit, compare existing COF or COG technique, it has not only saved cost, and the design for aesthetic of panel both sides symmetry can be accomplished, also can save the Bonding region of gate driver circuit and peripheral wiring space simultaneously, thus achieve the design of the narrow frame of display device, improve production capacity and the yield of display device.But along with the resolution of display panel and the increase of size, the load of each GOA also increases thereupon, the size of the thin film transistor (TFT) (TFT) of each shift register that is in GOA circuit is also larger, therefore cause the charging of pixel more difficult, the frame of corresponding display panel is wider.
Summary of the invention
Technical matters to be solved by this invention comprises, and there is above-mentioned problem for existing display panel, provides a kind of frame is narrower, display effect is homogeneous display panel and display device.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display panel, comprise viewing area and neighboring area, described viewing area comprises many grid lines arranged in a crossed manner and a plurality of data lines, described grid line and described data line intersection limit multiple pixel cell, wherein, grid line described at least one comprises at least two the grid line sections disconnecting and arranging, described in each, grid line section correspondence controls at least one pixel cell, described viewing area is divided at least two sub-viewing areas according to the open position of described grid line section, the shift register cell be connected with described grid line section is provided with in sub-viewing area described at least one, described shift register cell is used for providing gated sweep signal for connected described grid line section.
Preferably, grid line described in every bar includes at least two the grid line sections disconnecting and arranging, and the described grid line section being positioned at same a line is at least connected with a described shift register cell.
Further preferably, the open position of the grid line section in grid line described in each row is identical, the each described grid line section being arranged in same sub-viewing area connects different shift register cells respectively, and drive grid line section described in same sub-viewing area each described in shift register cell level be linked togather.
Further preferably, described in each in grid line described in every a line, grid line section all connects independent shift register cell, and be arranged in same sub-viewing area each described in shift register cell level be linked togather.
Further preferably, described viewing area comprises three sub-viewing areas, and grid line described in each is divided into three grid line sections, and sub-viewing area described in each comprises the same grid line section of all grid lines.
Further preferably, grid line described in every bar comprises the identical multiple grid line sections of length, the described grid line section being positioned at same sub-viewing area connects different shift register cells respectively, and the described shift register cell level being positioned at same sub-viewing area is linked togather.
Preferably, described shift register cell connects many signal line, and described signal wire and described data line be arranged in parallel.
Preferably, described shift register cell comprises 9 switch elements and a memory capacitance, and described grid line section correspondence controls 9 pixel cells, and pixel cell described in each is provided with a switch element, and described memory capacitance is arranged on wherein in a pixel cell.
Further preferably, described 9 switch elements are that the first transistor of correspondence is to the 9th transistor; Wherein,
First pole of described the first transistor connects it and controls pole and signal input part, and the second pole connects the first end of memory capacitance;
First pole of described transistor seconds connects the second pole of the first transistor, and the second pole connects low power end, controls pole and connects reset signal end;
First pole of described third transistor connects clock signal input terminal, and the second pole connects the second end and the signal output part of memory capacitance, controls the first end that pole connects memory capacitance;
First pole of described 4th transistor connects the second end and the signal output part of memory capacitance, and the second pole connects low power end, controls the second pole that pole connects the 5th transistor;
First pole of described 5th transistor connects high voltage end, and the second pole connects the first pole of the 6th transistor and the 7th transistor, controls the second pole that pole connects the 9th transistor;
First pole of described 6th transistor connects the control pole of the 4th transistor, and the second pole connects low power end, controls the first end that pole connects memory capacitance;
First pole of described 7th transistor connects the control pole of the 4th transistor, and the second pole connects low power end, controls the first end that pole connects memory capacitance;
First pole of described 8th transistor connects the second pole of the 9th transistor, and the second pole connects low power end, controls the control pole that pole connects the 6th transistor;
First pole of described 9th transistor connects it and controls pole and high voltage end, and the second pole connects the control pole of the 5th transistor.
Wherein, clock signal terminal is parallel to data line setting, signal input part is grid line, described the first transistor lays respectively at the pixel cell between nine articles of data lines to the 9th transistor, concrete, 9th transistor is between the first data line and the second data line, 8th transistor is between the second data line and the 3rd data line, 5th transistor is between the 3rd data line and the 4th data line, 6th transistor is between the 4th data line and the 5th data line, 7th transistor is between the 5th data line and the 6th data line, 4th transistor is between the 6th data line and the 7th data line, the first transistor is between the 7th data line and the 8th data line, third transistor is between the 8th data line and the 9th data line, transistor seconds is positioned at the opposite side of the 9th data line away from the 8th data line, especially, the first pole of described the first transistor is connected lastrow grid line, i.e. signal input part with its control pole, second pole of described third transistor is connected one's own profession grid line with the first pole of the 4th transistor, i.e. signal output part, the grid of described transistor seconds connects next line grid line, described memory capacitance is arranged between the 8th data line and the 9th data line.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display device, and it comprises above-mentioned display panel.
The present invention has following beneficial effect:
Due in display panel of the present invention, the shift register cell be connected with described grid line section is provided with in sub-viewing area described at least one, that is shift register cell is arranged in the viewing area of display panel at least partly, therefore be understandable that, the number of the shift register cell of the neighboring area of the more existing display panel of shift register cell of this display panel neighboring area is less, therefore the position reasonably arranging remaining shift register cell can be passed through, to make the frame of display panel narrower; And in the present invention at least part of grid line is divided into multiple grid line section, the more existing load be connected with grid line of the load be connected with grid line section, load obviously reduces, thus the driving force of shift register cell can be improved, also just alleviate the problem of pressure drop of grid line, and then it is more even that display panel is shown.
Because display device of the present invention comprises above-mentioned display panel, therefore its display effect is better, and frame is narrower.
Accompanying drawing explanation
Fig. 1 is the structural representation of the display panel of embodiments of the invention 1,2;
Fig. 2 is the schematic diagram of a kind of preferred structure of the display panel of embodiments of the invention 2;
Fig. 3 is the circuit diagram of the shift register cell of display panel in embodiments of the invention 1-5.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1:
The present embodiment provides a kind of display panel, comprise viewing area and neighboring area, described viewing area comprises many grid lines arranged in a crossed manner and a plurality of data lines, described grid line and described data line intersection limit multiple pixel cell, wherein, grid line described at least one comprises at least two the grid line sections disconnecting and arranging, described in each, grid line section correspondence controls at least one pixel cell, described viewing area is divided at least two sub-viewing areas according to the open position of described grid line section, the shift register cell be connected with described grid line section is provided with in sub-viewing area described at least one, described shift register cell is used for providing gated sweep signal for connected described grid line section.
Due in the display panel of the present embodiment, the shift register cell be connected with described grid line section is provided with in sub-viewing area described at least one, that is shift register cell is arranged in the viewing area of display panel at least partly, therefore be understandable that, the number of the shift register cell of the neighboring area of the more existing display panel of shift register cell of this display panel neighboring area is less, therefore the position reasonably arranging remaining shift register cell can be passed through, to make the frame of display panel narrower; And in the present embodiment at least part of grid line is divided into multiple grid line section, the more existing load be connected with grid line of the load be connected with grid line section, load obviously reduces, thus the driving force of shift register cell can be improved, also just alleviate the problem of pressure drop of grid line, and then it is more even that display panel is shown.
Wherein, grid line described in every bar includes at least two the grid line sections disconnecting and arranging, and the described grid line section being positioned at same a line is at least connected with a described shift register cell.That is, the grid line section being positioned at same a line can be driven by a shift register cell, also can be that each grid line Duan Jun is driven by independent shift register cell.Concrete in conjunction with following embodiment, to further illustrate the display panel of embodiment 1.
Embodiment 2:
As shown in Figure 1, the present embodiment provides a kind of display panel, and it comprises M bar grid line arranged in a crossed manner and N bar data line, and G (i) is wherein arbitrary grid line, and has 1≤i≤M; M is integer, and S (j) is arbitrary data line wherein, and has 1≤j≤N; N is integer.The intersection of all grid lines G (i) and all data lines S (j) limits multiple pixel cell A, and the open position in grid line G (i) described in each row is identical, often will be divided into multiple grid line section g by row grid line G (i); According to the open position of every row grid line G (i), the viewing area of display panel is divided into multiple interval and sub-viewing area Q is set; Each grid line section g connects an independently shift register cell GOA, and described shift register cell GOA is used for providing gated sweep signal for connected grid line section g.Wherein, drive each shift register cell GOA level in same sub-viewing area Q to be linked togather, form a gate driver circuit.
Each grid line section g is in the present embodiment by a shift register cell GOA, that is each shift register cell GOA is only for driving a grid line section g, this shift register cell GOA is comparatively for driving the shift register cell GOA of whole piece grid line G (i), and the size of the thin film transistor (TFT) needed for it is without the need to very large.It should be noted that, although shift register cell GOA to be arranged on pixel cell A region, also namely viewing area will affect the aperture opening ratio of display panel, cause the reduction of display brightness, but because each grid line section g is driven by an independent shift register cell GOA, therefore the display brightness of whole display panel evenly reduces, there will not be the problem that display is uneven, then can be increased with the brightness promoting display panel by the brightness of backlight for display brightness.
Concrete, to comprise six grid line G (1) ~ G (6), the display panel of nine data line S (1) ~ S (9) is example; Wherein, preferably, every a line grid line G (i) has three grid line section g, the width of the corresponding sub-viewing area Q of width of a grid line section g, and each sub-viewing area Q is in perpendicular column-shaped, and each sub-viewing area Q interval in the row direction.Each perpendicular row employing gate driver circuit controls, and now contributes to the control of gate driver circuit, makes display more homogeneous.
Preferably, each described gate driver circuit also comprises for each described shift register cell GOA provides many signal line of signal, and many described signal wires and described data line S (j) be arranged in parallel.Wherein, many signal line can comprise: signal input part INPUT signal inlead when introducing signal, clock signal input terminal CLK signal inlead when introducing signal, high voltage end VGH signal inlead etc. when introducing signal.
Wherein, as shown in Figure 2, the shift register cell GOA that a grid line section g in grid line G (i) connects just is illustrated in Fig. 2, shift register cell GOA in the present embodiment comprises 9 switch elements (M1-M9 namely shown in figure) and a memory capacitance C1, described grid line section correspondence controls 9 pixel cells, pixel cell A described in each is provided with a switch element, and described memory capacitance is arranged on wherein in a pixel cell A.
Concrete, clock signal clk is parallel to be arranged with data line S (9), signal input part INPUT is grid line G (i-1), described the first transistor M1 to the 9th transistor M9 lays respectively at the pixel cell between nine articles of data line S (1) ~ S (9), concrete, 9th transistor M9 is positioned between the first data line S (1) and the second data line S (2), 8th transistor position M8 is positioned between the second data line S (2) and the 3rd data line S (3), 5th transistor M5 is positioned between the 3rd data line S (3) and the 4th data line S (4), 6th transistor M6 is positioned between the 4th data line S (4) and the 5th data line S (5), 7th transistor M7 is positioned between the 5th data line S (5) and the 6th data line S (6), 4th transistor M4 is positioned between the 6th data line S (6) and the 7th data line S (7), the first transistor M1 is positioned between the 7th data line S (7) and the 8th data line S (8), third transistor M3 is positioned between the 8th data line S (8) and the 9th data line S (9), transistor seconds M2 is positioned at the opposite side of the 9th data line S (9) away from the 8th data line S (8), especially, first pole of described the first transistor M1 is connected lastrow grid line G (i-1), i.e. signal input part with its control pole, second pole of described third transistor M3 is connected one's own profession grid line G (i) with first pole of the 4th transistor M4, i.e. signal output part, the grid of transistor seconds M2 connects next line grid line G (i+1), described memory capacitance C1 is arranged between the 8th data line S (8) and the 9th data line S (9).
This kind of set-up mode can make each the switch element in each shift register GOA be evenly distributed in different pixel cell A, to make the shading position of display panel more even, namely make the opening of display panel more even, and then the brightness of the picture that display panel is shown is homogeneous.
Wherein, as shown in Figure 3,9 switch elements comprising of shift register cell GOA in the present embodiment respectively corresponding the first transistor M1 to the 9th transistor M9; Wherein, first pole of described the first transistor M1 connects it and controls pole and signal input part INPUT, and the second pole connects the first end of memory capacitance C1; First pole of described transistor seconds M2 connects second pole of the first transistor M1, and the second pole connects low power end VGL, controls pole and connects reset signal end RESET; First pole of described third transistor M3 connects clock signal input terminal CLK, and the second pole connects the second end and the signal output part OUTPUT of memory capacitance C1, controls the first end that pole connects memory capacitance C1; First pole of described 4th transistor M4 connects the second end and the signal output part OUTPUT of memory capacitance C1, and the second pole connects low power end VGL, controls the second pole that pole connects the 5th transistor M5; First pole of described 5th transistor M5 connects high voltage end VGH, and the second pole connects first pole of the 6th transistor M6 and the 7th transistor M7, controls the second pole that pole connects the 9th transistor M9; First pole of described 6th transistor M6 connects the control pole of the 4th transistor M4, and the second pole connects low power end VGL, controls the first end that pole connects memory capacitance C1; First pole of described 7th transistor M7 connects the control pole of the 4th transistor M4, and the second pole connects low power end VGL, controls the first end that pole connects memory capacitance C1; First pole of described 8th transistor M8 connects second pole of the 9th transistor M9, and the second pole connects low power end VGL, controls the control pole that pole connects the 6th transistor M6; First pole of described 9th transistor M9 connects it and controls pole and high voltage end VGH, and the second pole connects the control pole of the 5th transistor M5.The shift register cell GOA of certain the present embodiment is also in the layout of above-mentioned a kind of situation, as long as comprise load module, export pull-up module, the shift register cell GOA of reseting module is all passable.
Wherein, in every a line pixel cell A, described shift register cell GOA is positioned at the opposite side of connected described grid line section g.Why so arrange be because, grid line section g is connected with the pixel-driving circuit for driving pixel cell A, and shift register cell GOA is arranged on the opposite side of grid line section g, namely be arranged on the opposite side of pixel-driving circuit, thus make the more even of the light tight areal distribution of display panel, thus make display panel more homogeneous when showing.
Because in the display panel of the present embodiment, shift register cell GOA arranges pixel cell A region, namely be arranged on the viewing area of display panel, more existing display panel shift register cell GOA being arranged neighboring area, the frame of the display panel of the present embodiment is narrower; And in the present embodiment every bar grid line G (i) is divided into multiple grid line section g, the more existing load be connected with grid line G (i) of the load be connected with grid line section g, load obviously reduces, thus the driving force of shift register cell GOA can be improved, also just alleviate the problem of pressure drop of grid line G (i), and then it is more even that display panel is shown.
Embodiment 3:
The present embodiment provides a kind of display panel equally, the structure of this display panel is similar to the structure of the display panel in embodiment 2, difference is, in the display panel of the present embodiment, the grid line section g being positioned at same a line connects same shift register cell GOA, and that is a shift register cell GOA is used for providing gated sweep signal for a line grid line section g.
In the present embodiment, because the grid line section g being positioned at same a line connects same shift register cell GOA, now only need to increase multiple signal output part OUTPUT on each shift register cell GOA, technique is simple, and shift register cell GOA arranged pixel cell A region, namely be arranged on the viewing area of display panel, more existing display panel shift register cell GOA being arranged neighboring area, the frame of the display panel of the present embodiment is narrower.Other structures of display panel are identical with embodiment 2 in the present embodiment, are not described in detail at this.
Embodiment 4:
The present embodiment provides a kind of display panel equally, and it comprises M bar grid line arranged in a crossed manner and N bar data line, and G (i) is wherein arbitrary grid line, and has 1≤i≤M, S (j) to be arbitrary data line wherein, and has 1≤j≤N.The intersection of all grid lines G (i) and all data lines S (j) limits multiple pixel cell A, often will be divided into multiple grid line section g by row grid line G (i), and length of grid line section g is identical described in each, according to the open position of every row grid line G (i), the viewing area of display panel is divided into multiple interval and sub-viewing area Q is set; Each grid line section g connects an independently shift register cell GOA, and described shift register cell GOA is used for providing gated sweep signal for connected grid line section g.Wherein, drive each shift register cell GOA level in same sub-viewing area Q to be linked togather, form a gate driver circuit.
Because the length of each grid line section g is in an embodiment identical, but can not ensure that the open position of each row grid line G (i) is identical, therefore be understandable that, the arrangement of the sub-viewing area Q on this display panel is likely just irregular figure, but however, each shift register cell GOA is only for driving a grid line section g, this shift register cell GOA is comparatively for driving the shift register cell GOA of whole piece grid line G (M), and the size of the thin film transistor (TFT) needed for it is without the need to very large.It should be noted that, although shift register cell GOA to be arranged on pixel cell A region, also namely viewing area will affect the aperture opening ratio of display panel, cause the reduction of display brightness, but because each grid line section g is driven by an independent shift register cell GOA, therefore the display brightness of whole display panel evenly reduces, there will not be the problem that display is uneven, then can be increased with the brightness promoting display panel by the brightness of backlight for display brightness.
The structure of shift register cell in the present embodiment display panel, and miscellaneous part is identical with 2 with embodiment 1, is not described in detail at this.
Embodiment 5:
The present embodiment provides a kind of display panel equally, the structure of this display panel is similar to the structure of the display panel in embodiment 4, that is the length of each grid line section g is identical, difference is, in the display panel of the present embodiment, the grid line section g being positioned at same a line connects same shift register cell GOA, and that is a shift register cell GOA is used for providing gated sweep signal for a line grid line section g.
In the present embodiment, because the grid line section g being positioned at same a line connects same shift register cell GOA, now only need to increase multiple signal output part OUTPUT on each shift register cell GOA, technique is simple, and shift register cell GOA arranged pixel cell A region, namely be arranged on the viewing area of display panel, more existing display panel shift register cell GOA being arranged neighboring area, the frame of the display panel of the present embodiment is narrower.Other structures of display panel are identical with embodiment 4 in the present embodiment, are not described in detail at this.
Embodiment 6:
The present embodiment provides a kind of display device, and it comprises above-mentioned display panel.Therefore the display effect of the display panel of the present embodiment is better.
This display device can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (10)
1. a display panel, comprise viewing area and neighboring area, described viewing area comprises many grid lines arranged in a crossed manner and a plurality of data lines, described grid line and described data line intersection limit multiple pixel cell, it is characterized in that, grid line described at least one comprises at least two the grid line sections disconnecting and arranging, described in each, grid line section correspondence controls at least one pixel cell, described viewing area is divided at least two sub-viewing areas according to the open position of described grid line section, the shift register cell be connected with described grid line section is provided with in sub-viewing area described at least one, described shift register cell is used for providing gated sweep signal for connected described grid line section.
2. display panel according to claim 1, is characterized in that, grid line described in every bar includes at least two the grid line sections disconnecting and arranging, and the described grid line section being positioned at same a line is at least connected with a described shift register cell.
3. display panel according to claim 2, it is characterized in that, the open position of the grid line section in grid line described in each row is identical, the each described grid line section being arranged in same sub-viewing area connects different shift register cells respectively, and drive grid line section described in same sub-viewing area each described in shift register cell level be linked togather.
4. display panel according to claim 3, is characterized in that, described in each in grid line described in every a line, grid line section all connects independent shift register cell, and be arranged in same sub-viewing area each described in shift register cell level be linked togather.
5. display panel according to claim 3, is characterized in that, described viewing area comprises three sub-viewing areas, and grid line described in each is divided into three grid line sections, and sub-viewing area described in each comprises the same grid line section of all grid lines.
6. display panel according to claim 2, it is characterized in that, grid line described in every bar comprises the identical multiple grid line sections of length, the described grid line section being positioned at same sub-viewing area connects different shift register cells respectively, and the described shift register cell level being positioned at same sub-viewing area is linked togather.
7. the display panel according to any one of claim 1-6, is characterized in that, described shift register cell connects many signal line, and described signal wire and described data line be arranged in parallel.
8. the display panel according to any one of claim 1-6, it is characterized in that, described shift register cell comprises 9 switch elements and a memory capacitance, described switch element correspondence controls 9 pixel cells, pixel cell described in each is provided with a switch element, and described memory capacitance is arranged on wherein in a pixel cell.
9. display panel according to claim 8, is characterized in that, described 9 switch elements are that the first transistor of correspondence is to the 9th transistor; Wherein,
First pole of described the first transistor connects it and controls pole and signal input part, and the second pole connects the first end of memory capacitance;
First pole of described transistor seconds connects the second pole of the first transistor, and the second pole connects low power end, controls pole and connects reset signal end;
First pole of described third transistor connects clock signal input terminal, and the second pole connects the second end and the signal output part of memory capacitance, controls the first end that pole connects memory capacitance;
First pole of described 4th transistor connects the second end and the signal output part of memory capacitance, and the second pole connects low power end, controls the second pole that pole connects the 5th transistor;
First pole of described 5th transistor connects high voltage end, and the second pole connects the first pole of the 6th transistor and the 7th transistor, controls the second pole that pole connects the 9th transistor;
First pole of described 6th transistor connects the control pole of the 4th transistor, and the second pole connects low power end, controls the first end that pole connects memory capacitance;
First pole of described 7th transistor connects the control pole of the 4th transistor, and the second pole connects low power end, controls the first end that pole connects memory capacitance;
First pole of described 8th transistor connects the second pole of the 9th transistor, and the second pole connects low power end, controls the control pole that pole connects the 6th transistor;
First pole of described 9th transistor connects it and controls pole and high voltage end, and the second pole connects the control pole of the 5th transistor.
10. a display device, is characterized in that, described display device comprises the display panel according to any one of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510379531.0A CN104934005B (en) | 2015-07-01 | 2015-07-01 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510379531.0A CN104934005B (en) | 2015-07-01 | 2015-07-01 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104934005A true CN104934005A (en) | 2015-09-23 |
| CN104934005B CN104934005B (en) | 2017-05-17 |
Family
ID=54121149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510379531.0A Expired - Fee Related CN104934005B (en) | 2015-07-01 | 2015-07-01 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104934005B (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139806A (en) * | 2015-10-21 | 2015-12-09 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN105427791A (en) * | 2016-01-04 | 2016-03-23 | 京东方科技集团股份有限公司 | Array substrate and display apparatus |
| CN105575318A (en) * | 2016-03-18 | 2016-05-11 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| CN105739208A (en) * | 2016-05-13 | 2016-07-06 | 京东方科技集团股份有限公司 | Display device and driving device |
| CN106023944A (en) * | 2016-08-03 | 2016-10-12 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN106097968A (en) * | 2016-08-26 | 2016-11-09 | 京东方科技集团股份有限公司 | Display floater and display device |
| CN106873273A (en) * | 2017-02-23 | 2017-06-20 | 京东方科技集团股份有限公司 | Array base palte and its subregion driving method, display module and display device |
| CN106898324A (en) * | 2017-04-25 | 2017-06-27 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN106952607A (en) * | 2017-05-25 | 2017-07-14 | 京东方科技集团股份有限公司 | Display base plate, display panel and display device |
| CN107045850A (en) * | 2017-04-05 | 2017-08-15 | 京东方科技集团股份有限公司 | Array base palte, display panel and display device |
| CN107145021A (en) * | 2017-05-12 | 2017-09-08 | 友达光电股份有限公司 | Display panel |
| CN107452343A (en) * | 2016-06-01 | 2017-12-08 | 三星显示有限公司 | Display device |
| CN110265454A (en) * | 2019-06-25 | 2019-09-20 | 上海天马微电子有限公司 | A kind of display panel, its production method and display device |
| WO2021103012A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, pixel driving method, and display panel |
| CN113129835A (en) * | 2019-12-31 | 2021-07-16 | 乐金显示有限公司 | Display panel and display device using the same |
| WO2021196272A1 (en) * | 2020-03-31 | 2021-10-07 | 深圳市华星光电半导体显示技术有限公司 | Display panel of gate driver on array type |
| WO2021208119A1 (en) * | 2020-04-13 | 2021-10-21 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114664245A (en) * | 2022-05-25 | 2022-06-24 | 惠科股份有限公司 | Driving substrate and display panel thereof |
| WO2022183343A1 (en) * | 2021-03-01 | 2022-09-09 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN115079477A (en) * | 2022-05-25 | 2022-09-20 | 重庆惠科金渝光电科技有限公司 | Driving substrate and display panel thereof |
-
2015
- 2015-07-01 CN CN201510379531.0A patent/CN104934005B/en not_active Expired - Fee Related
Cited By (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139806B (en) * | 2015-10-21 | 2018-05-01 | 京东方科技集团股份有限公司 | Array base palte, display panel and display device |
| CN105139806A (en) * | 2015-10-21 | 2015-12-09 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| US10263056B2 (en) | 2015-10-21 | 2019-04-16 | Boe Technology Group Co., Ltd. | Array substrate, display panel and display device |
| CN105427791B (en) * | 2016-01-04 | 2018-09-11 | 京东方科技集团股份有限公司 | A kind of array substrate and display device |
| CN105427791A (en) * | 2016-01-04 | 2016-03-23 | 京东方科技集团股份有限公司 | Array substrate and display apparatus |
| CN105575318A (en) * | 2016-03-18 | 2016-05-11 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| CN105575318B (en) * | 2016-03-18 | 2019-02-26 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN105739208A (en) * | 2016-05-13 | 2016-07-06 | 京东方科技集团股份有限公司 | Display device and driving device |
| CN107452343A (en) * | 2016-06-01 | 2017-12-08 | 三星显示有限公司 | Display device |
| CN106023944A (en) * | 2016-08-03 | 2016-10-12 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN106023944B (en) * | 2016-08-03 | 2019-03-15 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN106097968A (en) * | 2016-08-26 | 2016-11-09 | 京东方科技集团股份有限公司 | Display floater and display device |
| CN106873273B (en) * | 2017-02-23 | 2021-01-29 | 京东方科技集团股份有限公司 | Array substrate, partition driving method thereof, display module and display device |
| CN106873273A (en) * | 2017-02-23 | 2017-06-20 | 京东方科技集团股份有限公司 | Array base palte and its subregion driving method, display module and display device |
| CN107045850A (en) * | 2017-04-05 | 2017-08-15 | 京东方科技集团股份有限公司 | Array base palte, display panel and display device |
| WO2018196471A1 (en) * | 2017-04-25 | 2018-11-01 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN106898324B (en) * | 2017-04-25 | 2019-09-17 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN106898324A (en) * | 2017-04-25 | 2017-06-27 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN107145021A (en) * | 2017-05-12 | 2017-09-08 | 友达光电股份有限公司 | Display panel |
| CN106952607A (en) * | 2017-05-25 | 2017-07-14 | 京东方科技集团股份有限公司 | Display base plate, display panel and display device |
| CN106952607B (en) * | 2017-05-25 | 2020-04-17 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
| CN110265454A (en) * | 2019-06-25 | 2019-09-20 | 上海天马微电子有限公司 | A kind of display panel, its production method and display device |
| US11876100B2 (en) | 2019-11-29 | 2024-01-16 | Boe Technology Group Co., Ltd. | Array substrate and method of manufacturing the same, pixel driving method, and display panel |
| WO2021103012A1 (en) * | 2019-11-29 | 2021-06-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, pixel driving method, and display panel |
| CN113196371A (en) * | 2019-11-29 | 2021-07-30 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof, pixel driving method and display panel |
| CN113129835A (en) * | 2019-12-31 | 2021-07-16 | 乐金显示有限公司 | Display panel and display device using the same |
| WO2021196272A1 (en) * | 2020-03-31 | 2021-10-07 | 深圳市华星光电半导体显示技术有限公司 | Display panel of gate driver on array type |
| US11361695B2 (en) | 2020-03-31 | 2022-06-14 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate-driver-on-array type display panel |
| WO2021208119A1 (en) * | 2020-04-13 | 2021-10-21 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| US11869410B2 (en) | 2020-04-13 | 2024-01-09 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
| WO2022183343A1 (en) * | 2021-03-01 | 2022-09-09 | 京东方科技集团股份有限公司 | Display panel and display device |
| GB2609826A (en) * | 2021-03-01 | 2023-02-15 | Boe Technology Group Co Ltd | Display panel and display device |
| US11798487B2 (en) | 2021-03-01 | 2023-10-24 | Hefei Boe Joint Technology Co., Ltd. | Display panel and display device |
| CN115079477A (en) * | 2022-05-25 | 2022-09-20 | 重庆惠科金渝光电科技有限公司 | Driving substrate and display panel thereof |
| CN114664245A (en) * | 2022-05-25 | 2022-06-24 | 惠科股份有限公司 | Driving substrate and display panel thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104934005B (en) | 2017-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104934005A (en) | Display panel and display device | |
| CN104835476B (en) | Shift register cell, gate driving circuit and its driving method, array base palte | |
| CN109637477B (en) | Display panel and display device | |
| CN103578433B (en) | A kind of gate driver circuit, method and liquid crystal display | |
| US7038653B2 (en) | Shift resister and liquid crystal display having the same | |
| US11308834B2 (en) | GOA display panel | |
| KR102208397B1 (en) | Gate driver of display device | |
| CN104732939A (en) | Shifting register, grid drive circuit, display device and grid drive method | |
| CN104464603A (en) | Display panel and display device | |
| KR101904277B1 (en) | Iquid crystal display apparatus | |
| CN103680636A (en) | Shifting register unit, gate driving circuit and display device | |
| CN105469764A (en) | Array substrate, liquid crystal display panel and electronic equipment | |
| CN108873530B (en) | Array substrate, display panel and display device | |
| CN111883074A (en) | Grid driving circuit, display module and display device | |
| CN109523970A (en) | Display module and display device | |
| CN105047155A (en) | Liquid crystal display apparatus and GOA scanning circuit | |
| CN102314845A (en) | Gating drive circuit and liquid crystal indicator with gating drive circuit | |
| CN105489178A (en) | Grid drive structure, display panel and display device | |
| CN107300794B (en) | Liquid crystal display panel driving circuit and liquid crystal display panel | |
| US11862064B2 (en) | Array substrate and display panel with gate driver on array circuit in display area | |
| CN110687731A (en) | Display panel, driving method and display device | |
| CN204348297U (en) | A kind of display panel and display device | |
| US10176779B2 (en) | Display apparatus | |
| CN101673526B (en) | Liquid crystal display device and related drive method | |
| CN104424876A (en) | GOA unit, GOA circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170517 |