CN105427791B - A kind of array substrate and display device - Google Patents

A kind of array substrate and display device Download PDF

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Publication number
CN105427791B
CN105427791B CN201610006594.6A CN201610006594A CN105427791B CN 105427791 B CN105427791 B CN 105427791B CN 201610006594 A CN201610006594 A CN 201610006594A CN 105427791 B CN105427791 B CN 105427791B
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China
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unit
input terminal
signal input
output
drop
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CN201610006594.6A
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Chinese (zh)
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CN105427791A (en
Inventor
姚之晓
田明
王俊伟
刘家荣
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to CN201610006594.6A priority Critical patent/CN105427791B/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • G09G3/2077Display of intermediate tones by a combination of two or more gradation control methods
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0421Structural details of the set of electrodes
    • G09G2300/0426Layout of electrodes and connections

Abstract

The invention discloses a kind of array substrate and display devices, are related to display technology field, can realize a kind of array substrate and display device of more narrow frame.The array substrate includes display area, and the gate driving circuit being arranged around the display area, the gate driving circuit includes multiple mutually cascade GOA units, the GOA unit includes output module and capacitance, one pole plate of the capacitance is connect with the control terminal of the output module, another pole plate of the capacitance is connect with the output end of the output module, and two pole plates of the capacitance are at least two conducting wires in the display area and being oppositely arranged.Array substrate in the present invention is applied in display device.

Description

A kind of array substrate and display device

Technical field

The present invention relates to display technology field more particularly to a kind of array substrates and display device.

Background technology

Display device includes array substrate and gate driving circuit, in order to reduce the production cost of display device, production capacity and Gate driving circuit is integrated in the one of the display area of array substrate by power consumption, generally use GOA (Gate On Array) technology On side.

Specifically, gate driving circuit includes multiple mutually cascade GOA units, the output module of each GOA unit Output end is connect with a grid line, to control the opening and closing of the grid line.In general, GOA unit further includes a capacitance, electricity Two pole plates held are connect with the source electrode and drain electrode of transistor respectively.In order to ensure that the output end of the output module of GOA unit connects The grid line connect can be opened fully, so that the pixel in display area is fully charged, capacitance that the output module of GOA unit includes Occupied area should be larger, and then causes the area of GOA unit larger.

Invention content

The purpose of the present invention is to provide a kind of array substrate and display devices, can realize a kind of array of more narrow frame Substrate and display device.

In order to achieve the above objectives, the present invention provides a kind of array substrate, adopts the following technical scheme that:

The array substrate includes display area, and the gate driving circuit being arranged around the display area, described Gate driving circuit includes multiple mutually cascade GOA units, and the GOA unit includes output module and capacitance, the capacitance A pole plate connect with the control terminal of the output module, the output of another pole plate and the output module of the capacitance Two pole plates of end connection, the capacitance are at least two conducting wires in the display area and being oppositely arranged.

Further, the present invention also provides a kind of display device, which includes array substrate as described above.

A kind of array substrate as described above of present invention offer and display device, due to the GOA unit in the array substrate In two pole plates of capacitance be in display area and at least two conducting wires for being oppositely arranged so that in GOA unit The big capacitance of area be located in display area, reduce GOA unit area occupied around display area, and then can Realize a kind of array substrate and display device of more narrow frame.

Description of the drawings

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, embodiment will be described below Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description be only the present invention some Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these Figure obtains other attached drawings.

Fig. 1 is the schematic diagram one of the array substrate in the embodiment of the present invention;

Fig. 2 is the circuit diagram one of the GOA unit in the embodiment of the present invention;

Fig. 3 is the circuit diagram two of the GOA unit in the embodiment of the present invention;

Fig. 4 is the schematic cross-section one of the capacitance in the embodiment of the present invention;

Fig. 5 is the schematic cross-section two of the capacitance in the embodiment of the present invention;

Fig. 6 is the schematic diagram two of the array substrate in the embodiment of the present invention;

Fig. 7 is the circuit diagram of the repetitive unit in the embodiment of the present invention;

Fig. 8 is the sequence diagram of the GOA unit shown in Fig. 2 in the embodiment of the present invention.

Reference sign:

1-grid line;2-electrode wires;3-pixel electrodes;

4-data lines;5-thin film transistor (TFT)s;6-initial signal input lines;

7-reset signal input lines;10-output modules;20-input units;

30-pull-up units;40-the first drop-down unit;50-the second drop-down unit;

60-third drop-down units.

Specific implementation mode

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation describes, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts Example, shall fall within the protection scope of the present invention.

As shown in fig. 1~fig. 5, array substrate provided in an embodiment of the present invention includes display area, and is arranged in viewing area Gate driving circuit around domain, gate driving circuit include multiple mutually cascade GOA units, and the GOA unit includes defeated Go out module 10 and capacitance C, a pole plate of capacitance C is connect with the control terminal of output module 10, another pole plate of capacitance C with it is defeated Go out output end (Gate n output are expressed as in the figure) connection of module 10, two pole plates of capacitance C are in display area And at least two conducting wires being oppositely arranged reduce so that the big capacitance C of area in GOA unit is located in display area GOA unit area occupied around display area, and then it is advantageously implemented the narrow frame design of display device.It is preferred that Ground, at least two conducting wires overlap, i.e. at least two conducting wires along being cascading on the direction of array substrate, So that array substrate has larger aperture opening ratio, at the same mode is arranged such can also make between each conducting wire have it is maximum just To area, and then it can also effectively promote the capacitance of capacitance C.

Illustratively, when two pole plates of capacitance C are two conducting wires in display area and overlapped, capacitance The structure of C is as shown in figure 4, when two pole plates of capacitance C are three conducting wires in display area and overlapped, capacitance The structure of C is as shown in Figure 5 (interstitital texture indicates conducting wire in Fig. 5), wherein positioned at the conducting wire of the top and leading positioned at bottom Line electrical connection is used as a pole plate, is located at intermediate conducting wire as another pole plate, at this point, capacitance C is equal to positioned at the top Conducting wire and the capacitance C1 that is formed positioned at intermediate conducting wire, with the electricity that is formed of conducting wire positioned at intermediate conducting wire and positioned at bottom Hold the shunt capacitance of C2 compositions.Based on the above content, those skilled in the art can easily obtain the other structures of capacitance C, this Inventive embodiments no longer repeat one by one.

Further, as shown in fig. 6, the array substrate in the embodiment of the present invention further includes being arranged in parallel in display area A plurality of grid line 1, the output end of the output module 10 of each GOA unit is connect at least one grid line 1, to control the grid line 1 opening and closing.Since grid line 1 is located in display area, and must connect with the output end of the output module 10 of GOA unit It connects, therefore, above-mentioned at least one grid line 1 can be used as a pole plate of the capacitance C in a GOA unit, correspondingly, it is only necessary to The a plurality of electrode wires 2 that setting is overlapped with grid line 1 in the display area of array substrate, make at least one electrode wires, 2 conduct Another pole plate of capacitance C, you can constitute the capacitance C in GOA unit, as above setting can effectively simplify the structure of array substrate And manufacturing process.Electrode wires 2 can be plain conductor, transparent conductors etc..

Wherein, a pole plate of the grid line 1 as the capacitance C in a GOA unit, a strip electrode line 2 is as capacitance C Another pole plate when, the structure of capacitance C is as shown in figure 4, a pole of the grid line 1 as the capacitance C in a GOA unit Plate, when another pole plate as capacitance C of two strip electrode lines 2, the structure of capacitance C is as shown in figure 5, in order to obtain better capacitance Value, two pole plates may be designed to apart from structure that is very short, and insulating between two substrates of guarantee, for being formed in same layer structure Capacitance, two substrates are in close proximity, but insulator is provided between substrate, for being formed in the capacitance of levels, two bases Very little can be arranged to obtain in the distance between plate, but is unlikely to be connected, and insulator is provided between two substrates.In above Hold, those skilled in the art can easily obtain the other structures of capacitance C, and the embodiment of the present invention no longer repeats one by one.

It is possible to further by changing the facing area of grid line 1 and electrode wires 2, the thickness of insulating layer between the two The size of capacitance C is adjusted with the dielectric constant of insulating layer.The inventors of the present application found that in order to make grid line 1 and electrode Possess big facing area between line 2, when so that the capacitance C in GOA unit is larger, the width of electrode wires 2 should be than grid line 1 Greatly, so that it can completely cover grid line 1, therefore in the embodiment of the present invention preferably, the material of above-mentioned electrode wires 2 is transparent Conductive material will not reduce the aperture opening ratio of array substrate so that when the width of electrode wires 2 is bigger than the width of grid line 1.It is preferred that Ground, electrode wires 2 can be arranged with 3 same layer of pixel electrode being arranged in display area and material identical, so that electrode wires 2 and picture Plain electrode 3 can be formed in a patterning processes, helped to simplify the structure of array substrate, reduced being fabricated to for array substrate This.Illustratively, the material of electrode wires 2 and pixel electrode 3 is tin indium oxide (ITO).

As shown in fig. 6, being additionally provided in the display area of array substrate and 1 vertically disposed multiple data lines 4 of grid line, grid Line 1 and data line 4 define multiple pixel units, wherein are provided with thin film transistor (TFT) 5 and pixel electrode in each pixel unit 3, thin film transistor (TFT) 5 includes source electrode, drain electrode, grid and active layer, and the source electrode of thin film transistor (TFT) 5 connect with data line 4, drain and Pixel electrode 3 connects.When grid of the grid line 1 directly as thin film transistor (TFT) 5, i.e., active layer, source electrode and drain electrode located immediately at When the top of grid line 1, preferred electrode line 2 has a bending at 5 position of thin film transistor (TFT) in the embodiment of the present invention, with around excessively thin Film transistor 5, and then the parasitic capacitance between electrode wires 2 and source electrode or drain electrode can be reduced, reduce the power consumption of display device.

In addition, the GOA unit in the embodiment of the present invention further includes the drive module for controlling output module output, In, drive module and output module can may be contained within the side (left side or right side) of display area as shown in Figure 3, can also It is set to the both sides of display area being oppositely arranged as shown in Figure 2, i.e. output module is arranged in the side of display area, drives mould The other side opposite with output module is arranged outside display area in block.It should be noted that with drive module packet in Fig. 2 and Fig. 3 For including input unit 20, pull-up unit 30, the first drop-down unit 40, the second drop-down unit 50 and third drop-down unit 60.It is right The structure of connection relation and each module between both the above set-up mode, drive module, output module and capacitance C is equal It is identical.

Further, in order to enable the area that the circuit around the display area occupies reduces, ensure outside display area The area occupied equity of side so that the display device for using the array substrate in the present invention obtains better design space, tool There is a more preferably aesthetics, in the embodiment of the present invention preferably, as shown in figs. 1,2 and 6, the output mould that each GOA unit includes Block 10 is arranged in the side of display area, the drive module setting other side opposite with output module 10 outside display area, with Keep the frame of display device narrower.

It should be noted that for the gate driving circuit of different structure, other modules that GOA unit includes can not Together, those skilled in the art can select according to actual needs.Illustratively, as shown in Figures 2 and 3, the present invention is implemented GOA unit in example includes output module 10, capacitance C and drive module, and drive module includes input unit 20, pull-up unit 30, the first drop-down unit 40, the second drop-down unit 50 and third drop-down unit 60.

Wherein, a pole plate of capacitance C is connect with the control terminal of output module 10, another pole plate and the output of capacitance C The output end of module 10 connects;The input terminal of output module 10 connects a clock signal input terminal, the input of input unit 20 End and control terminal are all connected with initial signal input terminal (for inputting initial signal Input), the output end connection of input unit 20 First node PU;The input terminal and control terminal of pull-up unit 30 are all connected with another clock signal input terminal, pull-up unit 30 Output end connects second node PD;The input terminal of first drop-down unit 40 connects first node PU, and the of the first drop-down unit 40 One control terminal connects reset signal input terminal RESET, the second control terminal connection second node PD of the first drop-down unit 40, and first The output end connection closed signal input part of drop-down unit 40 (for inputting shutdown signal VOFF);Second drop-down unit 50 it is defeated Enter end connection second node PD, the control terminal of the second drop-down unit 50 connects first node PU, the output of the second drop-down unit 50 Hold connection closed signal input part;The output end of the input terminal connection output module 10 of third drop-down unit 60, third drop-down are single First control terminal of member 60 connects second node PD, and the second control terminal of third drop-down unit 60 connects reset signal input terminal (for inputting reset signal RESET), the output end connection closed signal input part of third drop-down unit 60.

Wherein, output module 10 is used for 1 output drive signal of grid line, and capacitance C is used to maintain the signal of output module 10 Output, input unit 20 for making first node PU be in unblocked level, for making second node PD be in open by pull-up unit 30 Level is opened, the first drop-down unit 40 closes level for making first node PU be in, and the second drop-down unit 50 is for making the second section Point PD, which is in, closes level, and third drop-down unit 60 is used to make the output of output module 10 in closing level.It needs to illustrate , above-mentioned unblocked level refers to making the level that its module controlled, unit or element are opened, closes level and refer to making Its module controlled, unit or element close the level opened.For example, when element is N-type transistor, corresponding unlatching Level is high level, and corresponding closing level is low level.

On the basis of the concrete structure of GOA unit as shown in Figure 2, in the embodiment of the present invention preferably, in GOA unit Connecting line between the control terminal and first node PU of output module 10 is a strip electrode line 2, the output end of output module 10 with Connecting line between the input terminal of third drop-down unit 60 is a grid line 1, with while the capacitance C in being constituted GOA unit, Simplify the structure of GOA unit.

Further, as shown in Figure 6 and Figure 7, gate driving circuit further includes the first clock signal input terminal (for inputting First clock signal clk 1) and second clock signal input part (for inputting second clock signal CLK2), the first clock signal The opposite in phase of CLK1 and second clock signal CLK2, in gate driving circuit, adjacent two GOA units are as a repetition Unit, wherein the input terminal of the output module 10 in first GOA unit in each repetitive unit connects the first clock signal Input terminal, the input terminal and control terminal of pull-up unit 30 are all connected with second clock signal input part, defeated in second GOA unit The input terminal connection second clock signal input part for going out module 10, when the input terminal and control terminal of pull-up unit 30 are all connected with first Clock signal input part.

At this point, each drive in the output module 10 and second GOA unit in first GOA unit in repetitive unit Dynamic model block and the first clock signal input terminal are arranged at the side (such as left side positioned at display area) of display area, Output module 10 in second GOA unit and the drive module in first GOA unit and second clock signal input part It is arranged at the other side (such as right side positioned at display area) outside display area.

In addition, as shown in Figure 6 and Figure 7, the gate driving circuit in the embodiment of the present invention further includes from n-th grade of GOA unit In the initial signal input line 6 extended of the one end that is connect with the output end of output module 10 of grid line 1, initial signal input line The initial signal input terminal of 6 (n+1)th grade of GOA unit of connection, gate driving circuit further includes from the grid in (n+1)th grade of GOA unit The reset signal input line 7 that one end that line 1 is connect with the output end of output module 10 is extended, reset signal input line 7 connect The reset signal input terminal of n-th of GOA unit, wherein n be more than or equal to 1, and less than GOA unit sum positive integer, thus So that the signal transmission between adjacent two-stage GOA unit is quick.For first order GOA unit, initial signal input terminal Initial signal STV is connected, for afterbody GOA unit, reset signal input terminal connects reset signal STD.

Optionally, the concrete structure of two GOA units in the repetitive unit in the embodiment of the present invention is as shown in fig. 7, weight The difference of the concrete structure of two GOA units in multiple unit is only that the first clock signal input terminal and second clock signal are defeated Enter end to exchange, the embodiment of the present invention only describes the concrete structure of a GOA unit.

As shown in fig. 7, the GOA unit is n-th grade of GOA unit, wherein n is more than or equal to 1 and less than GOA unit sum Positive integer, the output module 10 of n-th grade of GOA unit includes the first transistor M1, and input unit 20 includes second transistor M2, Pull-up unit 30 include third transistor M3, the first drop-down unit 40 include the 4th transistor M4 and the 5th transistor M5, second Drop-down unit 50 includes the 6th transistor M6, and third drop-down unit 60 includes the 7th transistor M7 and the 8th transistor M8.

Wherein, the grid of the M1 of the first transistor connects first node PU, and source electrode connects the first clock signal input terminal, leakage Pole connects the source electrode of the 7th transistor M7 and the 8th transistor M8;The source electrode and grid of second transistor M2 is all connected with initial signal (for n-th grade of GOA unit, initial signal input terminal is the defeated of the output module 10 of (n-1)th grade of GOA unit to input terminal Outlet Gate n-1 output, n are the positive integer more than or equal to 1 and less than GOA unit sum), drain electrode connection first node PU;The source electrode and grid of third transistor M3 is all connected with second clock signal input part, drain electrode connection second node PD;4th is brilliant The source electrode of body pipe M4 connects first node PU, and drain connection closed signal input part, and grid connects second node PD;5th crystal The source electrode of pipe M5 connects first node PU, and drain connection closed signal input part, and grid connects reset signal input terminal (for the For n grades of GOA units, initial signal input terminal is the output end Gate n+1 of the output module 10 of (n+1)th grade of GOA unit Output, n are the positive integer more than or equal to 1 and less than GOA unit sum);The source electrode of 6th transistor M6 connects second node PD, drain connection closed signal input part, and grid connects first node PU;The source electrode of 7th transistor M7 connects the first transistor The drain electrode of M1, drain connection closed signal input part, and grid connects second node PD;The source electrode connection first of 8th transistor M8 The drain electrode of transistor M1, drain connection closed signal input part, and grid connects reset signal input terminal.

Optionally, the transistor in the GOA unit in the embodiment of the present invention is N-type transistor or P-type transistor.

The course of work of GOA unit with above structure (with all transistors is as shown in Figure 8 N-type crystal in Fig. 8 Pipe, the shutdown signal VOFF of shutdown signal input terminal input is for low level), specifically,

In the t1 periods, the first clock signal clk 1 is low level, and second clock signal CLK2 is high level, initial signal Input is high level, and reset signal RESET is low level, the first transistor M1, second transistor M2, third transistor M3 and 6th transistor M6 is in open state, and first node PU is high level, and second node PD is compared with low level, the 4th transistor M4 and the 7th transistor M7 is in semi-open state, and the 5th transistor M5 and the 8th transistor M8 are in closed state, should The output end Gate n output of the output module of GOA unit export low level.

In the t2 periods, the first clock signal clk 1 is high level, and second clock signal CLK2 is low level, initial signal Input is low level, and reset signal RESET is low level, and the first transistor M1, second transistor M2 and the 6th transistor M6 are equal In open state, first node PU is high level, and second node PD is low level, third transistor M3, the 4th transistor M4, 5th transistor M5, the 7th transistor M7 and the 8th transistor M8 are in closed state, the output module of the GOA unit it is defeated Outlet Gate n output export high level.

In the t3 periods, the first clock signal clk 1 is low level, and second clock signal CLK2 is high level, initial signal Input is low level, and reset signal RESET is high level, third transistor M3, the 4th transistor M4, the 5th transistor M5, the Seven transistor M7 and the 8th transistor M8 are in open state, and first node PU is low level, and second node PD is high level, The first transistor M1, second transistor M2 and the 6th transistor M6 are in closed state, the output module of the GOA unit it is defeated Outlet Gate n output export low level.

The present invention provides a kind of array substrate as described above, due to the capacitance C's in the GOA unit in the array substrate Two pole plates are at least two conducting wires in display area and being oppositely arranged, so that area in GOA unit is big Capacitance is located in display area, reduces GOA unit area occupied around display area, and then can realize one kind more The array substrate and display device of narrow frame.

Further, the present invention also provides a kind of display device, which includes array substrate as described above. Since the display device includes array substrate as described above, which has identical with above-mentioned display base plate Advantageous effect is no longer repeated herein.The display device can be:Liquid crystal display panel, Electronic Paper, organic light emitting display panel, Any production with display function such as mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator Product or component.

The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims (9)

1. a kind of array substrate, which is characterized in that including display area, and the gate driving that is arranged around the display area Circuit, the gate driving circuit include that multiple mutually cascade GOA unit, the GOA units include output module and capacitance, One pole plate of the capacitance is connect with the control terminal of the output module, another pole plate of the capacitance and the output mould The output end of block connects, and two pole plates of the capacitance are that at least two in the display area and be oppositely arranged lead Line;
At least two conducting wires overlap;
It further include a plurality of grid line being arranged in parallel in the display area, and a plurality of electrode overlapped with the grid line One pole plate of line, the capacitance in the GOA unit is at least one grid line, another pole plate of capacitance is at least one electrode Line;
The GOA unit further includes the drive module for controlling the output module output, and the output module is arranged in institute State the side of display area, the drive module setting other side opposite with the output module outside the display area.
2. array substrate according to claim 1, which is characterized in that the electrode wires are transparent conductors.
3. array substrate according to claim 2, which is characterized in that be additionally provided with pixel electrode, electrode in display area Line is arranged with pixel electrode same layer and material identical.
4. array substrate according to claim 1, which is characterized in that the drive module includes input unit, pull-up list Member, the first drop-down unit, the second drop-down unit and third drop-down unit, wherein the input terminal of the output module connects one Clock signal input terminal, the input terminal and control terminal of the input unit are all connected with initial signal input terminal, the input unit Output end connect first node;The input terminal and control terminal of the pull-up unit are all connected with another clock signal input terminal, The output end of the pull-up unit connects second node;The input terminal of first drop-down unit connects the first node, institute State the first control terminal connection reset signal input terminal of the first drop-down unit, the second control terminal connection of first drop-down unit The second node, the output end connection closed signal input part of first drop-down unit;Second drop-down unit it is defeated Enter end and connect the second node, the control terminal of second drop-down unit connects the first node, and second drop-down is single The output end of member connects the shutdown signal input terminal;The input terminal of the third drop-down unit connects the defeated of the output module First control terminal of outlet, the third drop-down unit connects the second node, the second control of the third drop-down unit End connects the reset signal input terminal, and the output end of the third drop-down unit connects the shutdown signal input terminal.
5. array substrate according to claim 4, which is characterized in that the control of the output module in the GOA unit Connecting line between end processed and the first node is the electrode wires, the output end of the output module and the third Connecting line between the input terminal of drop-down unit is a grid line, to constitute the capacitance in the GOA unit.
6. array substrate according to claim 5, which is characterized in that the gate driving circuit further includes the first clock letter Number input terminal and second clock signal input part, the first clock signal and described second on first clock signal input terminal The opposite in phase of second clock signal on clock signal input terminal, in the gate driving circuit, adjacent two GOA units As a repetitive unit, wherein the input of the output module in first GOA unit in each repetitive unit End connects first clock signal input terminal, and the input terminal and control terminal of the pull-up unit are all connected with the second clock letter The input terminal of number input terminal, the output module in second GOA unit connects the second clock signal input part, described The input terminal and control terminal of pull-up unit are all connected with first clock signal input terminal.
7. array substrate according to claim 6, which is characterized in that first GOA in each repetitive unit is mono- The output module in member and the drive module in second GOA unit and first clock signal input terminal It is arranged at the side of the display area, the institute in the output module and first GOA unit in second GOA unit It states drive module and the second clock signal input part is arranged at the other side outside the display area.
8. array substrate according to claim 7, which is characterized in that the gate driving circuit further includes from n-th of institute The initial signal input line that one end that the grid line in GOA unit is connect with the output end of the output module is extended is stated, The initial signal input line connects the initial signal input terminal of (n+1)th GOA unit;The gate driving circuit Further include extending from one end that the grid line in (n+1)th GOA unit is connect with the output end of the output module Reset signal input line, the reset signal input line connects the reset signal input terminal of n-th of GOA unit, Wherein, n be more than or equal to 1, and less than GOA unit sum positive integer.
9. a kind of display device, which is characterized in that including such as claim 1~8 any one of them array substrate.
CN201610006594.6A 2016-01-04 2016-01-04 A kind of array substrate and display device CN105427791B (en)

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CN202363089U (en) * 2011-12-19 2012-08-01 京东方科技集团股份有限公司 Shift register and array substrate grid drive circuit
CN104934005A (en) * 2015-07-01 2015-09-23 京东方科技集团股份有限公司 Display panel and display device

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