KR100801416B1 - Circuit for sharing gate line and data line of Thin Film Transistor-Liquid Crystal Display panel and driving method for the same - Google Patents

Abstract

According to the present invention, in driving four adjacent pixels by using one gate line and one data line, a gate line of a liquid crystal display device that does not require a separate signal line for controlling transistors included in each pixel, and A data line sharing circuit and a driving method thereof are provided.

The gate line and data line sharing circuit of the liquid crystal display according to the present invention is provided on a specific gate line without the need for a separate signal line for controlling the transistor in controlling four pixels provided adjacent to the specific gate line. The four transistors can be effectively controlled by using the transistors and the two gate lines adjacent to the specific gate line.

Description

Circuit for sharing gate line and data line of Thin Film Transistor-Liquid Crystal Display panel and driving method for the same}

1 is a circuit diagram of a general liquid crystal display device according to the prior art.

2 is a circuit diagram of a data line sharing circuit of a liquid crystal display device according to the prior art.

3 is a circuit diagram of a gate line and a data line sharing circuit of a liquid crystal display according to the prior art.

4 is a circuit diagram of a gate line and a data line sharing circuit of the liquid crystal display according to the present invention.

5 is a partially enlarged view of FIG. 4.

FIG. 6 is a timing diagram for describing the circuit operation of FIG. 5. FIG.

7 is a reference diagram for illustrating an opening ratio of a gate line and a data line sharing circuit of a liquid crystal display according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate line and a data line sharing circuit of a liquid crystal display and a driving method thereof, and more particularly, to drive four adjacent pixels using one gate line and one data line. The present invention relates to a gate line and a data line sharing circuit of a liquid crystal display device in which a separate signal line for controlling a transistor provided in the transistor is not required, and a driving method thereof.

As the information society develops, the demand for display devices is also increasing in various forms.In response to this, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELDs), and vacuum fluorescent displays (VFDs) have recently been developed. Various kinds of flat panel display devices have been studied, and some are used as display devices in various devices.

Among them, LCD is the most used for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption, and it is used to receive and display broadcast signal in addition to mobile type such as monitor of notebook computer. Various developments such as TV and computer monitors. Recently, a liquid crystal display (TFT-LCD) using a thin film transistor (TFT) has been widely used for a display of a notebook computer.

On the other hand, in an active matrix liquid crystal display using a thin film transistor, a thin film transistor is mounted on each pixel, and each thin film transistor has a structure connected to a gate line and a data line. That is, as illustrated in FIG. 1, a plurality of gate lines and data lines are vertically crossed to define a plurality of pixel regions, and a thin film transistor is provided in each pixel region.

As such, the active matrix liquid crystal display includes gate lines and data lines equal to the number of pixels in a horizontal array or the number of pixels in a vertical array, and the gate lines and data lines are made of an expensive conductive material. In manufacturing the display device, the material cost of the gate line and the data line occupies a considerable portion in comparison with the total manufacturing cost. Accordingly, there is a limit in reducing the manufacturing cost of the liquid crystal display device.

As part of the research to solve this problem, as shown in FIG. 2, two adjacent pixels (first and second pixels or third and fourth pixels) are driven using one data line. So-called data line sharing driving method has been proposed. Such a data line sharing driving method requires only half the data lines as compared to the conventional liquid crystal display device, thereby significantly reducing the manufacturing cost of the liquid crystal display device.

Furthermore, a method of sharing not only data lines but also gate lines has recently been proposed. Referring to FIG. 3, four adjacent pixels may be driven using one gate line and one data line. In detail, the gate signal is applied to a transistor provided in each of four adjacent pixels through one gate line to control on / off of each pixel.

However, the gate line and data line sharing structures as described above have two transistors in each pixel and one pixel is turned on / off by a combination of signals applied to each of the two transistors. The line alone cannot apply various gate signals that can selectively turn on / off four pixels. Accordingly, in order to control two transistors included in each pixel, an additional signal line (A of FIG. 3) must be provided in addition to the one gate line.

As described above, the conventional gate line and data line sharing structure can effectively control driving of four adjacent pixels using one gate line and one data line, but a separate signal line A is required. Accordingly, there is a problem that the effect of reducing the manufacturing cost is halved.

The present invention has been made to solve the above problems, and in driving four adjacent pixels using one gate line and one data line, a separate signal for controlling the transistors provided in each pixel It is an object of the present invention to provide a gate line and data line sharing circuit of a liquid crystal display device in which no line is required.

In the liquid crystal display according to the present invention, a plurality of unit pixel regions are defined by a plurality of gate lines and data lines that are vertically intersected with each other. A gate line and a data line sharing circuit of a liquid crystal display having a structure in which four pixels are provided in a pixel region and two transistors are arranged in each pixel, wherein one gate line (n-th gate line) and one data are provided. The lines intersect and are divided into four areas, such as the upper left area, the upper right area, the lower left area, the lower right area, and the like. Four pixels are positioned, and each pixel includes a first transistor TFT and a second transistor TFT. A ninth transistor TFT is provided on the gate, and a gate of the first TFT of the first pixel is connected to a drain of the ninth TFT provided on the n-th gate line, and a second TFT of the first pixel is formed. A gate is connected to the n-th gate line, a gate of the first TFT of the second pixel is connected to the n-th gate line, and a gate of the second TFT of the second pixel is the n-1 gate line. The gate of the first TFT of the third pixel is connected to the n + 1 gate line, the gate of the second TFT of the third pixel is connected to the n-1 gate line, and the fourth The gates of the first and second TFTs of the pixel are connected to the n-th gate line.

Preferably, the first and second TFTs and the ninth TFTs of the respective pixels are composed of n-type transistors or p-type transistors.

In the method of driving a gate line and a data line sharing circuit of a liquid crystal display according to the present invention, both the first pixel and the second pixel are applied during one line time, which is a time for applying a data signal to two pixels adjacent to the data line. A signal is applied to the n-th, n-th, and n-th gate lines to turn on.

Preferably, when the first and second TFTs and the ninth TFTs of the first to fourth pixels are composed of p-type transistors, a signal is supplied to the n-th, n-th and n-th gate lines. Applying, in the first half of the first line time, by applying a low signal to each of the n-th, n-th and n-th +1 gate lines to turn on all of the first to fourth pixels In the second half of the first line time, the first, third, and third pixels are turned off by applying low, low, and high signals to the n−1, n, and n + 1 gate lines, respectively. The second and fourth pixels are turned on, and in the second half of the second line time, low, high, and low signals are applied to the n-1, n, and n + 1 gate lines, respectively, so that the first And the second pixel is turned off, the third and fourth pixels are turned on, and at the second half of the second line time, the n-1, nth and n + 1 gate lines are provided. The first to third pixels are turned off and the fourth pixels are turned on by applying low, high and high signals, respectively.

Preferably, when the high signal is applied to the n-th gate line, all of the first to fourth pixels are turned off.

According to a feature of the present invention, in controlling four pixels provided adjacent to a specific gate line, the transistor provided on the specific gate line and the specific gate line without the need for a separate signal line for controlling the transistor are provided. By using two gate lines, four pixels can be effectively controlled.

Hereinafter, a gate line and a data line sharing circuit of the liquid crystal display according to the present invention will be described in detail with reference to the drawings. 4 is a circuit diagram of a gate line and a data line sharing circuit of the liquid crystal display according to the present invention, FIG. 5 is a partially enlarged view of FIG. 4, and FIG. 6 is a timing diagram for explaining the circuit operation of FIG. 5.

First, as shown in FIG. 4, the gate line and the data line sharing circuit of the liquid crystal display according to the present invention are arranged in a plurality of gate lines GL ₁ , GL ₂ , GL ₃ ,. , GL _n ) and a plurality of data lines DL ₁ , DL ₂ , DL ₃ ,... DL _n arranged at regular intervals in the horizontal direction.

The gate lines and the data lines vertically cross each other, and a plurality of unit pixel regions are defined by the gate lines and the data lines that cross vertically. Four pixels are provided in the unit pixel area, and each pixel is connected to a switching element to be selectively turned on / off by an operation of the switching element. The switching element connected to each of the four pixels is composed of two transistors (a first TFT (TFT1) and a second TFT (TFT2)), and each transistor is selectively turned on / off by receiving a signal from the gate line. Is off.

On the other hand, a plurality of transistors (the ninth TFT (TFT9)) are provided on each gate line at a predetermined interval, and the ninth TFT is arranged in one shape per unit pixel region so that the first pixel of the unit pixel region is provided. Is connected with the first TFT of.

The gate line and data line sharing circuit of the liquid crystal display according to the present invention is characterized in that four pixels can be controlled through one gate line and one data line, which is simply one data line and four pixels. This may mean that the data signal is applied to one gate line, and one gate line applies the gate signal to four pixels. However, in the case of the data signal, the gate line and the data line sharing circuit according to the present invention apply the data signal to four pixels through one data line, but in the case of the gate signal, four gate lines are substantially used. The gate signal is applied to the pixel.

Applying a gate signal to four pixels using three gate lines may violate the object and feature of the present invention, which is to apply the gate signal to four pixels through one gate line. However, the shared circuit according to the present invention uses first and third gate lines adjacent to the second gate line when applying a gate signal to four pixels adjacent to the second gate line, and uses the third gate line. When a gate signal is applied to four adjacent pixels, each gate line applies a gate signal to four pixels adjacent to each gate line, for example, by using second and fourth gate lines adjacent to the third gate line. In the case of application, it has a structure using two gate lines adjacent to the corresponding gate line. Accordingly, in view of the overall circuit structure, the gate signal is applied to four pixels through one gate line.

Meanwhile, as described above, in the sharing circuit according to the present invention, three gate lines are required to apply a gate signal to four pixels constituting the unit pixel region. It should be organically connected to two transistors (eight TFTs in total) and a ninth TFT provided in a gate line located in the middle of the three gate lines.

Hereinafter, the connection relationship between the three gate lines and the nine TFTs will be described in detail with reference to FIG. 5. For convenience of description, four pixels (dotted lines in FIG. 4) adjacent to the second gate line among the first, second, and third gate lines will be described.

As shown in FIG. 5, the first, second, and third gate lines and the second data line intersect and are disposed, and the first to fourth pixels are provided at a portion where the second gate line and the second data line intersect. do. Two transistors (first TFT and second TFT) are disposed in each of the four pixels, and a ninth TFT is provided on the second gate line to control four pixels through one gate line and one data line. There are nine transistors in total. The nine transistors may be either n-type or p-type transistors, but the following description will be made based on the p-type transistor.

Under such a structure, the gate of the first TFT of the first pixel is connected to the drain of the ninth TFT provided on the second gate line, and the gate of the second TFT of the first pixel is connected to the first gate line. Connected. The gate of the first TFT of the second pixel is connected to a second gate line, and the gate of the second TFT of the second pixel is connected to the first gate line. The gate of the first TFT of the third pixel is connected with the third gate line, and the gate of the second TFT of the third pixel is connected with the first gate line. Finally, the gates of the first TFT and the second TFT of the fourth pixel are connected to the first gate line.

Meanwhile, referring to the connection relationship with each transistor of the data line, the first TFTs of the first to fourth pixels are connected to the second data line to switch the data signal applied from the data line.

An operation of a gate line and a data line sharing circuit of the liquid crystal display according to the present invention having the circuit configuration as described above will be described with reference to the timing diagram of FIG. 6.

First, two line times are required to supply data to the first to fourth pixels. Data is sequentially supplied to the first and second pixels through a first line time, and data is sequentially supplied to the third and fourth pixels through a second line time. The first line time may be divided into a first half where data is supplied to the first pixel and a second half where data is supplied to the second pixel, and the second line time may also be divided into a first half where data is supplied to the third pixel. And a second half in which data is supplied to the fourth pixel. Meanwhile, in order to supply data to the first to fourth pixels through the first and second line times, timing diagrams for the gate lines as shown in FIG. 6 are required.

The timing diagram of FIG. 6 is as follows.

First, when a low signal is applied to each of the first, second and third gate lines during the first half of the first line time, the first and second transistors of the first to fourth pixels and the second gate are applied. The ninth TFTs provided on the line are all turned on so that all of the first to fourth pixels are turned on.

Since all of the first to fourth pixels are turned on, data may be supplied to all of the four pixels through the second data line, but the first half of the first line time may be provided only to the first pixel. Since the data is the time to be supplied, the data supplied from the second data line is stored in the capacitor of the first pixel.

Subsequently, low, low and high signals are applied to the first, second and third gate lines during the second half of the first line time. Accordingly, the first TFT of the first pixel is off, the second TFT is on, the first and second TFTs of the second pixel are all on, and the third pixel is of the third pixel. The first TFT is off, the second TFT is on, and both the first TFT and the second TFT of the fourth pixel are on. As a result of these operations, the first and third pixels are off and the second and fourth pixels are on.

The second and fourth pixels are turned on, but since the second half of the first line time is a time for supplying data only to the second pixel, the data supplied from the second data line is supplied to the capacitor of the second pixel. Stored.

Next, low, high and low signals are applied to the first, second and third gate lines, respectively, in the first half of the second line time. Accordingly, the first TFT of the first pixel is turned off, the second TFT is turned on, the first TFT of the second pixel is turned off, the second TFT is turned on, and the first and third TFTs of the third and fourth pixels are made. Both TFTs are on. As a result, the first and second pixels are off and the third and fourth pixels are on. At this time, the third and fourth pixels are turned on, but since the first half of the second line time is the time for which data is supplied only to the third pixel, the data supplied from the second data line is the third pixel. Is stored in the capacitor.

Finally, low, high and high signals are applied to the first, second and third gate lines, respectively, in the second half of the second line time. Accordingly, the first TFT of the first pixel is off, the second TFT is on, the first TFT of the second pixel is off, the second TFT is on, the first TFT of the third pixel is off, the second The TFT is on, and both the first TFT and the second TFT of the fourth pixel are on.

By the operation of the transistor, the first to third pixels are turned off and only the fourth pixel is turned on, and the data signal supplied by the second data line is stored in the fourth pixel.

Referring to the operation of the sharing circuit according to the present invention, it can be seen that two pixels sharing one data line are turned on for one line time. That is, the first and second pixels are turned on at the first line time, and the third and fourth pixels are turned on at the second line time. As the two pixels are turned on in one line time, more than half of the line time can be used for any one pixel. For example, when the line time is 2 seconds and the voltages applied to the first pixel and the second pixel are 3V and 4V, respectively, 3V is applied to the first pixel through the first half of the first line time. Since the data signal of is precharged in the second pixel, only a 1V signal needs to be stored in the second pixel in the second half of the first line time. In other words, it means that 3V is pre-charged during the first half of the first line time, so that the data storage time of the second half can be shortened, so that the first half time of the first line time is reduced to the entire line time. More than half of them will be available.

Meanwhile, as shown in FIG. 5, when the first gate line is turned off as the second TFTs of the first to fourth pixels are connected to the first gate line, all four pixels are turned off. As such, since the four pixels are turned off at the same time, the voltage difference ΔVp between the pixels is small, thereby making it possible to improve the image quality imbalance between pixels.

The above circuit operation has been described with reference to the second gate line, but the same result is obtained when applying the reference to any gate line of the shared circuit according to the present invention.

For reference, the shared circuit according to the present invention does not have to worry about lowering the aperture ratio because additional conducting wires are required to apply a gate signal to each transistor, but it is remarkably compared with a structure in which a separate signal line A is added. The aperture ratio can be improved. 7 is a layout showing the aperture ratio of the sharing circuit according to the present invention.

The gate line and data line sharing circuit of the liquid crystal display according to the present invention have the following effects.

In controlling four pixels provided adjacent to a specific gate line, a transistor (ninth TFT) provided on a specific gate line and two adjacent to a specific gate line without the need for a separate signal line for controlling the transistor The gate lines can be used to effectively control four pixels.

Through such a structure, the gate line and the data line can be halved, thereby significantly reducing the manufacturing cost of the liquid crystal display and improving the aperture ratio.

In addition, as the two pixels are turned on during one line time, the precharging effect is doubled, and the charging time of any one pixel can be used for more than half of the entire line time. In addition, when the transistor included in each pixel is composed of a p-type TFT using a low temperature poly-silicon process, a mask can be reduced and manufacturing costs can be further lowered.

Claims (5)

A liquid crystal having a structure in which a plurality of unit pixel regions are defined by a plurality of gate lines and data lines that are vertically intersected with each other, four pixels are provided in each unit pixel region, and two transistors are disposed in each pixel. In the gate line and data line sharing circuit of a display device, One gate line (n-th gate line) and one data line intersect and are divided into four regions, such as an upper left region, an upper right region, a lower left region, and a lower right region. The upper left region, the upper right region, the lower left region, and the lower region respectively. A first pixel, a second pixel, a third pixel, and a fourth pixel are positioned at Each pixel includes a first transistor TFT and a second transistor TFT, and a ninth transistor TFT is provided on the gate line. A gate of the first TFT of the first pixel is connected to a drain of a ninth TFT provided on the n-th gate line, and a gate of the second TFT of the first pixel is connected to an n-1 gate line , A gate of the first TFT of the second pixel is connected to the n-th gate line, a gate of the second TFT of the second pixel is connected to the n-th gate line, A gate of the first TFT of the third pixel is connected with an n + 1 gate line, a gate of the second TFT of the third pixel is connected with the n-1 gate line, A gate of the first TFT and the second TFT of the fourth pixel is connected to the n-th gate line; And the first and second TFTs and the ninth TFTs of the pixels are n-type transistors or p-type transistors. delete A driving method of a gate line and a data line sharing circuit of the liquid crystal display device according to claim 1, The n-th, n-th, and nth to turn on both the first pixel and the second pixel during one line time, which is a time for applying a data signal to two pixels adjacent to the data line; A method for driving a gate line and a data line sharing circuit of a liquid crystal display device, characterized in that a signal is applied to a +1 gate line. 4. The gate driving circuit according to claim 3, wherein when the first and second TFTs and the ninth TFTs of the first to fourth pixels are composed of p-type transistors, Applying a signal is, In the first half of the first line time, a low signal is applied to each of the n-th, n-th and n-th gate lines to turn on all of the first to fourth pixels, In the second half of the first line time, low, low, and high signals are applied to the n−1, n, and n + 1 gate lines, respectively, so that the first and third pixels are turned off, and The second and fourth pixels are turned on, In the second half of the second line time, low, high, and low signals are applied to the n-1, n, and n + 1 gate lines, respectively, so that the first and second pixels are turned off and the third is turned off. And the fourth pixel is turned on, In the second half of the second line time, low, high, and high signals are applied to the n-1, nth, and n + 1 gate lines, respectively, so that the first to third pixels are turned off, and the fourth pixels are turned off. A method of driving a gate line and a data line sharing circuit of a liquid crystal display device, characterized in being turned on. 5. The driving of the gate line and data line sharing circuits of the liquid crystal display device according to claim 4, wherein when the high signal is applied to the n-th gate line, the first to fourth pixels are all turned off. Way.

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