CN112965306A - Display panel and display device - Google Patents
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- CN112965306A CN112965306A CN202110223825.XA CN202110223825A CN112965306A CN 112965306 A CN112965306 A CN 112965306A CN 202110223825 A CN202110223825 A CN 202110223825A CN 112965306 A CN112965306 A CN 112965306A
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- 230000005540 biological transmission Effects 0.000 claims abstract description 57
- 239000003086 colorant Substances 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 13
- 239000010409 thin film Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 241001270131 Agaricus moelleri Species 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
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Abstract
The application discloses display panel and display device is divided into display area and non-display area, display panel includes: a plurality of data lines, a plurality of scan lines, a plurality of base pixels, and a plurality of data transmission signal lines; a plurality of scanning lines and a plurality of data lines are crossed to form a plurality of pixel regions, basic pixels at least comprise basic pixels with three different colors, each basic pixel is arranged corresponding to one pixel region, and the same basic pixel with the same color is correspondingly arranged on the same data line; a plurality of data transmission signal lines are arranged in the non-display area and used for transmitting data signals for the data lines; the number of the data transmission signal lines is equal to one half of the number of the data lines; among the data lines corresponding to the basic pixels of the same color, two adjacent data lines are connected to the same data transmission signal line, so that the cost of the display panel is reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
Because thin film transistor liquid crystal displays (TFT-LCDs) have the advantages of low radiation, small size, low energy consumption and the like, the TFT-LCDs are widely applied to various electronic information products. At present, the demand of large-size displays (according to 50 inches, 58 inches, 65 inches, 75 inches and the like) is increasing in the market, and the display effect is pursuing the definition of 2K (FHD), 4K (UD) and 8K.
Although the display already supports the decoding of 2K, 4K and 8K digital signals, the resolution of the digital signals actually used is still below 2K due to the limitation of network transmission and the limitation of the resolution of digital signal resources, so that display screens smaller than 4K and 8K are basically used in daily life, and the 4K and 8K displays are expensive at present, and how to reduce the cost of the 4K and 8K display screens becomes a problem to be solved urgently.
Disclosure of Invention
The application aims to provide a display panel and a display device so as to reduce the cost of the display panel.
The application discloses display panel is divided into display area and non-display area, display panel includes: a plurality of data lines, a plurality of scan lines, a plurality of base pixels, and a plurality of data transmission signal lines; a plurality of scanning lines and a plurality of data lines are crossed to form a plurality of pixel regions, a plurality of basic pixels at least comprise basic pixels with three different colors, each basic pixel is arranged corresponding to one pixel region, and the same basic pixel with the same color is correspondingly arranged on the same data line; a plurality of data transmission signal lines are arranged in the non-display area and used for transmitting data signals for the data lines; the number of the data transmission signal lines is equal to one half of the number of the data lines; at least two adjacent data lines in the plurality of data lines corresponding to the basic pixels with the same color are connected to the same data transmission signal line.
Optionally, the display panel further comprises a plurality of data selectors; at least two adjacent data lines in the plurality of data lines corresponding to the basic pixels of the same color are connected to the same data transmission signal line through one data selector.
Optionally, each of the data selectors respectively includes a first active switch and a second active switch; the output ends of the first active switch and the second active switch are respectively connected to two adjacent data lines, and the input ends of the first active switch and the second active switch are connected to the same data transmission signal line.
Optionally, the display panel further includes: a plurality of scanning transmission signal lines and a plurality of scanning switching circuits; the scanning transmission signal lines provide scanning signals for the scanning lines, and the number of the scanning transmission signal lines is equal to one half of the number of the scanning lines; a plurality of scan switching circuits; at least two adjacent scanning lines are connected to one scanning transmission signal line through one scanning switching circuit.
Optionally, the scan switching circuit includes a third active switch and a fourth active switch; the output ends of the third active switch and the fourth active switch are respectively connected to two adjacent scanning lines, and the input ends of the third active switch and the fourth active switch are connected to the same scanning transmission signal line; the control end of the third active switch is used for inputting a first clock signal; the control end of the fourth active switch is used for inputting a second clock signal.
Optionally, the scan switching circuit further includes a first voltage boost circuit and a second voltage boost circuit; the output end of the third active switch is connected to the corresponding scanning line through the first booster circuit; the output end of the fourth active switch is connected to the corresponding scanning line through the second booster circuit.
Optionally, the first voltage boost circuit includes: the output end of the third active switch is connected to the control end of the fifth active switch, the output end of the fifth active switch is connected to the corresponding scanning line, the input end of the fifth active switch is used for inputting a third clock signal, and two ends of the first capacitor are respectively connected to the control end of the fifth active switch and the output end of the fifth active switch; the second boost circuit includes: the output end of the fourth active switch is connected to the control end of the sixth active switch, the output end of the sixth active switch is connected to the corresponding scanning line, the input end of the sixth active switch is used for inputting a fourth clock signal, and two ends of the second capacitor are respectively connected to the control end of the sixth active switch and the output end of the sixth active switch.
Optionally, the scan switching circuit further includes a first reset circuit and a second reset circuit; the first reset circuit is connected with the first boosting circuit in parallel; the second reset circuit is connected in parallel with the second boost circuit.
Optionally, the first reset circuit includes: a seventh active switch and an eighth active switch, an output of the seventh active switch and an output of the eighth active switch being connected to a Vss signal, a control terminal of the seventh active switch and a control terminal of the eighth active switch being connected to a first reset signal, an input of the seventh active switch being connected to an output of the third active switch, an input of the eighth active switch being connected to an output of the fifth active switch; the second reset circuit includes: a ninth active switch and a tenth active switch, an output of the ninth active switch and an output of the tenth active switch being connected to the Vss signal, a control terminal of the ninth active switch and a control terminal of the tenth active switch being connected to a second reset signal, an input of the ninth active switch being connected to an output of the fourth active switch, an input of the tenth active switch being connected to an output of the sixth active switch.
The application discloses display device, including foretell display panel and for display panel provides the backlight unit of light source.
Compared with the scheme that the ultra-high-definition display screen displays the low-definition pictures, the data transmission signal line is connected with the data line corresponding to the two adjacent rows of basic pixels with the same color, the data transmission signal line provides the same data voltage, so that the gray scales of the data voltages of the two adjacent rows of basic pixels in the same color basic pixel are consistent, the adjacent basic pixels have the same gray scale, the ultra-high-definition display screen can display the low-definition pictures, the number of the corresponding data transmission signal lines is reduced to half of that of the data lines, the number of the corresponding data chips is reduced to half, and further the cost is saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a display device provided in an embodiment of the present application;
fig. 2 is a schematic diagram of a display panel provided in an embodiment of the present application;
fig. 3 is a schematic diagram of another display panel provided by an embodiment of the present application;
FIG. 4 is a schematic view of section A of FIG. 3 of the present application;
FIG. 5 is a timing diagram of control terminals of a first active switch and a second active switch according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a switching circuit provided by an embodiment of the present application;
FIG. 7 is a schematic diagram of another switching circuit provided by an embodiment of the present application;
FIG. 8 is a timing diagram of the G1 output for the high resolution display case provided by the embodiments of the present application;
FIG. 9 is a timing diagram of the G2 output for the high resolution display case provided by the embodiments of the present application;
fig. 10 is a timing diagram of the G1 and G2 outputs in the case of low resolution display provided by embodiments of the present application.
Wherein, 1, a display device; 10. a display panel; 30. a backlight module; 100. an array substrate; 110. a data line; 114. a data selector; 114a, a first active switch; 114b, a second active switch; 120. scanning a line; 121. a scan switching circuit; 1211. a third active switch; 1212. a fourth active switch; 122. a first booster circuit; 1221. a fifth active switch; 1222. a first capacitor; 123. a second boost circuit; 1231. a sixth active switch; 1232. a second capacitor; 124. a first reset circuit; 1241. a seventh active switch; 1242. an eighth active switch; 125. a second reset circuit; 1251. a ninth active switch; 1252. a tenth active switch; 130. a data transmission signal line; 140. scanning a transmission data line; 200. a color film substrate; 210. a base pixel.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1, as an embodiment of the present application, a display device is disclosed, which includes a display panel 10 and a backlight module 30 for providing a backlight source for the display panel 10.
According to fig. 2, a schematic view of a display panel 10 is shown, said display panel 10 comprising: a plurality of data lines 110, a plurality of scan lines 120, a plurality of base pixels 210, and a plurality of data transmission signal lines 130. The data lines 110 and the scan lines 120 are arranged to intersect to form a plurality of pixel regions, one pixel region is arranged between two adjacent data lines 110 and two adjacent scan lines 120, and each pixel region is correspondingly provided with one basic pixel 210. The corresponding basic pixels 210 on each data line 110 are basic pixels 210 of the same color, and the display panel 10 at least includes basic pixels 210 of three different colors; for example, one of the embodiments may be: a row of basic pixels 210 corresponding to the first data line 111 is a red pixel R, a row of basic pixels 210 corresponding to the second data line 112 is a green pixel G, a row of basic pixels 210 corresponding to the third data line 113 is a blue pixel B, and RGB are sequentially arranged in the direction of the scanning line 120, each R pixel or G pixel or B pixel is disposed corresponding to one data line 110, and the corresponding data line provides a pixel voltage for the basic pixels. It should be noted that the basic pixel 210 in fig. 2 may be formed on the array substrate of the display panel 10, or may be formed on the color filter substrate of the display panel 10, and fig. 2 is only a schematic diagram, and it cannot be described that the basic pixel 210 of the present application is only located on the array substrate provided with the scan line 120 and the data line 110; and the arrangement order of the three basic pixels on the corresponding first column data line 110 to the third column data line 110 may be RGB, GBR, BRG, etc., and the arrangement order is not limited herein.
As shown in fig. 3, another display panel 10 is provided, the display panel 10 including: a plurality of data lines 110, a plurality of scan lines 120, a plurality of base pixels 210, and a plurality of data transmission signal lines 130. A plurality of data lines 110 and a plurality of scanning lines 120 are arranged in a crossing manner to form a plurality of pixel regions, one pixel region corresponds between two adjacent data lines 110 and two adjacent scanning lines 120, and each pixel region is correspondingly provided with one basic pixel 210; the corresponding basic pixels 210 on each data line 110 are basic pixels 210 of the same color, and the display panel 10 at least includes basic pixels 210 of three different colors; among the data lines 110 corresponding to the basic pixels 210 of the same color, at least two adjacent data lines 110 are connected to the same data transmission signal line 130. Two adjacent data lines 110 refer to two adjacent data lines connecting the same color basic pixels 210.
Compared with the scheme that the ultra-high-definition display screen displays the low-definition picture, the data transmission signal line 130 is connected with the data lines 110 corresponding to the two adjacent columns of the basic pixels 210 with the same color, the data transmission signal line 130 provides the same data voltage, so that in the basic pixels 210 with the same color, the gray scales of the data voltages of the basic pixels 210 in the two adjacent columns are consistent, the adjacent basic pixels 210 have the same gray scale, the ultra-high-definition display screen can display the low-definition picture, the number of the corresponding data transmission signal lines 130 is reduced to be the same as that of the data lines 110, the number of the corresponding data chips can be reduced by half, and the cost is saved.
Also when the UD to FHD functionality is to be implemented, the exemplary scheme is to turn on two adjacent rows G1 and G2 simultaneously, then the adjacent red pixels to the same data signal, the adjacent green pixels to the same data signal, and the adjacent blue pixels to the same data signal. Three adjacent basic pixels 210RGB constitute one pixel, so the UD conversion FHD means that 4(2 × 2) pixels adjacent to each other up, down, left and right give the same signal to visually realize the function of FHD conversion. Compared with the conventional FHD display, the conversion function has high cost which is twice as much as the required data chips of the general FHD, and the data chip corresponding to the UD is more expensive than the data chip of the conventional FHD; in the method, the expensive data chip is halved, the scanning chip is unchanged, two adjacent lines are opened simultaneously, the same data signal is given by two lines of pixels, and then the UD display panel 10 with low cost is realized. The present invention is also applicable to a display panel 10 with a higher resolution such as 8K.
Of course, as shown in fig. 4 and 5, the display panel 10 of the present application may also need to implement a function of UD conversion FHD, and the corresponding display panel 10 further includes a plurality of data selectors 114, two adjacent data lines 110 in the plurality of data lines 110 corresponding to the base pixels 210 of the same color are connected to the same data transmission signal line 130 through the data selectors 114, and the data selectors 114 in this embodiment may implement a time period t1, such that one data line 110 is connected to the data transmission signal line 130, and during a time period t2, another data line 110 is connected to the data transmission signal line 130; it is thus possible to realize that different data signals are supplied to the two data lines 110 respectively at different periods of the data transmission signal line 130, whereby the display of UD can also be realized.
As fig. 4 shows the schematic diagram of a in fig. 3, the data selector 114 comprises a first active switch 114a and a second active switch 114 b; the output terminals of the first active switch 114a and the second active switch 114b are respectively connected to two adjacent data lines 110, and the input terminals of the first active switch 114a and the second active switch 114b are connected to the same data transmission signal line 130. The control end of the first active switch 114a and the control end of the second active switch 114b are respectively connected to different time division control lines, and in a time period t1, the first active switch 114a is turned on, so that the data line 110 to which the first active switch 114a is correspondingly connected is communicated with the data transmission signal line 130; at time t2, the second active switch 114b is turned on, so that the data line 110 correspondingly connected to the second active switch 114b is connected to the data transmission signal line 130, and when FHD display is required, the first active switch 114a and the second active switch 114b are selectively turned on at the same time; the corresponding time division control line can be provided by a timing controller of the display panel 10, and it should be noted that the active switch, that is, the thin film transistor, is a common structure in the display panel 10, and in the process, under the condition that the scan line 120 layer and the data line 110 layer are formed, the thin film transistor for display in the display panel 10 is also etched, so the design of adding the thin film transistor between the data line 110 and the data transmission signal line 130 in the present application does not bring the increase of the process cost, and the process identical to that of the thin film transistor for display does not bring the problem in the process. In addition, the first active switch 114a and the second active switch 114b in this embodiment are provided in plural numbers, and the number corresponds to the number of the data lines.
Specifically, the control terminal of the first active switch 114a is connected to the signal T1, and the control terminal of the second active switch 114b is connected to the signal T2, wherein the first active switch 114a and the second active switch 114b are thin film transistors. The data signals on the data transmission signal lines 130 are divided into two groups, when the scan lines 120 receive signals, the T1 signal connected to the first active switch 114a is turned on as a high voltage signal, the T2 signal connected to the second active switch 114b is turned off as a low voltage signal, and the first group of data signals on the data transmission signal lines 130 are input to the data lines 110 correspondingly connected to the first active switch 114a in the display panel 10. Wherein the T1 on time and the T2 off time are both 0.5H (1H is the time that one scan line 120 is on, i.e., the row on time); then, a low-voltage T1 signal is input to the first active switch 114a to turn off the first active switch 114a, a high-voltage T2 signal is input to the second active switch 114b to turn on the second active switch 114b, and a second set of data signals on the data transmission signal line 130 are input to the data line 110 connected to the first active switch 114a in the display panel 10. The waveforms of T1 and T2 are shown in FIG. 5, with the two waveforms staggered so that T1 and T2 alternate on and off.
In order to further save the cost of the display panel 10, the above-mentioned data selector 114 is also applicable to the scan lines 120, and specifically, as shown in fig. 6, the display panel 10 further includes a plurality of scan transmission signal lines 140 and a plurality of scan switching circuits 121, the scan transmission signal lines 140 provide scan signals for the scan lines 120, and the number of the scan transmission signal lines 140 is equal to one half of the number of the scan lines 120; two adjacent scanning lines 120 are connected to one scanning transmission signal line 140 through one scanning switching circuit 121; the scan switching circuit 121 mentioned in this embodiment may be formed by the data selector 114, for example, two adjacent scan lines 120 are respectively controlled by two active switches to switch on the two scan lines 120 sequentially or simultaneously.
As shown in fig. 6, the present application further provides another embodiment of a scan switching circuit 121 of a scan line 120, where the scan switching circuit 121 includes: a third active switch 1211, a fourth active switch 1212, a first boost circuit 122 and a second boost circuit 123; the input terminals of the third active switch 1211 and the fourth active switch 1212 are connected to one of the scan transmission signal lines 140; the output terminal of the third active switch 1211 is connected to the scan line G1 through the first boost circuit 122; the output end of the fourth active switch 1212 is connected to the scan line G2 through the second voltage boosting circuit 123; the control terminal of the third active switch 1211 is connected to a first clock signal, and the control terminal of the fourth active switch 1212 is connected to a second clock signal. In the present application, in the connection manner of one scanning transmission signal line 140 to two scanning lines 120, when the third active switch 1211 and the fourth active switch 1212 are separately turned on, the time for scanning the scanning signal on the scanning transmission signal line 140 is divided into two times and is respectively provided to the two scanning lines 120, wherein, in the time period of t3, one scanning line 120 is turned on, and in the time period of t4, the second scanning line 120 is turned on. For the scheme that two scanning lines 120 are opened simultaneously, the time for opening each scanning line 120 is shortened to half of the original time, and the voltage of the scanning signal of the scanning line 120 is boosted through the boosting circuit in the corresponding scheme, so that the display active switch corresponding to the scanning line 120 can react quickly, and the situation that the load on the scanning line 120 makes the voltage value of the scanning signal insufficient and the display active switch can be opened only in a buffering time is prevented.
Specifically, the first boost circuit 122 includes: a fifth active switch 1221 and a first capacitor, wherein an output terminal of the third active switch 1211 is connected to the control terminal of the fifth active switch 1221, an output terminal of the fifth active switch 1221 is connected to the corresponding scan line G1, an input terminal of the fifth active switch 1221 is connected to a third clock signal, and two terminals of the first capacitor are respectively connected to the control terminal of the fifth active switch 1221 and the output terminal of the fifth active switch 1221; the second boost circuit 123 includes: an output end of the fourth active switch 1212 is connected to the control end of the sixth active switch 1231, an output end of the sixth active switch 1231 is connected to the corresponding scan line G2, an input end of the sixth active switch 1231 is connected to a fourth clock signal, and two ends of the second capacitor are respectively connected to the control end of the sixth active switch 1231 and the output end of the sixth active switch 1231. In the scheme, the third active switch 1211 controls the fifth active switch 1221 to be turned on, and when the fifth active switch 1221 is turned on, the third clock signal is output to the corresponding scan line G1; the sixth active switch 1231 is controlled to be turned on by the fourth active switch 1212, and when the sixth active switch 1231 is turned on, the fourth clock signal is output to the corresponding scan line G2.
In another embodiment, as shown in fig. 7, the scan switching circuit 121 further includes a first reset circuit 124 and a second reset circuit 125; the first reset circuit 124 is connected in parallel with the first boost circuit 122; the second reset circuit 125 is connected in parallel with the second boost circuit 123. The first reset circuit 124 includes: a seventh active switch 1241 and an eighth active switch 1242, an output terminal of the seventh active switch 1241 and an output terminal of the eighth active switch 1242 being connected to a Vss signal, a control terminal of the seventh active switch 1241 and a control terminal of the eighth active switch 1242 being connected to a first reset signal, an input terminal of the seventh active switch 1241 being connected to an output terminal of the third active switch 1211, and an input terminal of the eighth active switch 1242 being connected to an output terminal of the fifth active switch 1221. The second reset circuit 125 includes: ninth and tenth active switches 1251 and 1252, an output of the ninth and tenth active switches 1251 and 1252 being connected to the Vss signal, a control terminal of the ninth and tenth active switches 1251 and 1252 being connected to a second reset signal, an input terminal of the ninth active switch 1251 being connected to an output terminal of the fourth active switch 1212, and an input terminal of the tenth active switch 1252 being connected to an output terminal of the sixth active switch 1231. By releasing the voltage on the scan line 120 after the scan period for each row of each frame is finished. That is, the first reset signal in this embodiment is turned on when the third active switch 1211 and the fifth active switch 1221 are turned on from the on state to the off state, so that the seventh active switch 1241 and the eighth active switch 1242 are turned on to communicate with the Vss signal, and the residual charge in the scan switching circuit 121 is cleared, which will not affect the normal turn-on of the scan line 120 of the next frame. It should be noted that the Vss signal, the first reset signal and the second reset signal of the present application may be provided by a timing control chip.
The present application further discloses a specific embodiment, which discloses a display panel 10, wherein the display panel 10 includes a plurality of data lines 110, a plurality of scan lines 120, a plurality of basic pixels 210, a plurality of data transmission signal lines 130, a plurality of scan transmission signal lines 140, and a scan switching circuit 121. Wherein, as shown in fig. 7, a schematic diagram of a scan switching circuit 121 is shown, the scan switching circuit 121 includes: a third active switch 1211, a fourth active switch 1212, a fifth active switch 1221, a sixth active switch 1231, a seventh active switch 1241, an eighth active switch 1242, a ninth active switch 1251, a tenth active switch 1252, a first capacitor, and a second capacitor; the input terminals of the third active switch 1211 and the fourth active switch 1212 are connected to one of the scan transmission signal lines 140; an output terminal of the third active switch 1211 is connected to a control terminal of the fifth active switch 1221; the output end of the fifth active switch 1221 is connected to the corresponding scan line G1; an output terminal of the fourth active switch 1212 is connected to a control terminal of the sixth active switch 1231, an output terminal of the sixth active switch 1231 is connected to the corresponding scan line G2, a control terminal of the seventh active switch 1241 and a control terminal of the eighth active switch 1242 are connected to a first reset signal, an input terminal of the seventh active switch 1241 is connected to an output terminal of the third active switch 1211, and an input terminal of the eighth active switch 1242 is connected to an output terminal of the fifth active switch 1221; a control terminal of the ninth active switch 1251 and a control terminal of the tenth active switch 1252 are connected to a second reset signal, an input terminal of the ninth active switch 1251 is connected to an output terminal of the fourth active switch 1212, and an input terminal of the tenth active switch 1252 is connected to an output terminal of the sixth active switch 1231. Two ends of the first capacitor are respectively connected to the control end of the fifth active switch 1221 and the output end of the fifth active switch 1221; two ends of the second capacitor are respectively connected to the control end of the sixth active switch 1231 and the output end of the sixth active switch 1231;
wherein a control terminal of the third active switch 1211 is connected to a first clock signal, and a control terminal of the fourth active switch 1212 is connected to a second clock signal; the input terminal of the fifth active switch 1221 is connected to a third clock signal, and the input terminal of the sixth active switch 1231 is connected to a fourth clock signal; the outputs of the seventh active switch 1241 and the eighth active switch 1242 are connected to a Vss signal to which the outputs of the ninth active switch 1251 and the tenth active switch 1252 are connected.
The progressive scanning of G1 and G2 under the high resolution condition and the simultaneous scanning of G1 and G2 under the low resolution condition can be respectively realized by controlling the timing sequence of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal. For high resolution, the timing diagram of the output G1 is shown in fig. 8, where the peaks are all high, the valleys are all low, and the horizontal lines indicate that low is always output. CK1 is the waveform of the first clock signal, CK2 is the waveform of the second clock signal, CK3 is the waveform of the third clock signal, CK4 is the waveform of the fourth clock signal, Reset1 is the waveform of the first Reset data signal, Reset2 is the waveform of the second Reset data signal, and gate _ in is the signal output from the scan transfer signal line 140. The timing chart of the output G2 is shown in fig. 9, where the gate _ in is shifted backward by 1H relatively (where H is the time that one row of the scan lines 120 is on, i.e., the row on time), so that G2 is input to the next row after G1 by one H. In the case of low resolution, gate _ in is input, and G1 and G2 are output simultaneously with the timing shown in fig. 10.
The technical solution of the present application can be widely applied to various display panels, and the above solution can be applied to TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, MVA (Multi-Domain Vertical Alignment) display panels, of course, other types of display panels, and OLED (Organic Light-Emitting Diode) display panels.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A display panel divided into a display area and a non-display area, comprising:
a plurality of data lines;
a plurality of scan lines crossing the plurality of data lines to form a plurality of pixel regions;
the plurality of basic pixels at least comprise basic pixels of three different colors, each basic pixel is arranged corresponding to one pixel region, and the basic pixels of the same color are correspondingly arranged on the same data line; and
a plurality of data transmission signal lines disposed in the non-display area for transmitting data signals to the data lines; the number of the data transmission signal lines is equal to one half of the number of the data lines;
at least two adjacent data lines in the plurality of data lines corresponding to the basic pixels of the same color are connected to the same data transmission signal line.
2. The display panel of claim 1, wherein the display panel further comprises a plurality of data selectors;
at least two adjacent data lines in the plurality of data lines corresponding to the basic pixels of the same color are connected to the same data transmission signal line through one data selector.
3. The display panel of claim 2, wherein each of the data selectors comprises a first active switch and a second active switch, respectively;
the output ends of the first active switch and the second active switch are respectively connected to two adjacent data lines, and the input ends of the first active switch and the second active switch are connected to the same data transmission signal line.
4. The display panel according to claim 1, characterized in that the display panel further comprises:
a plurality of scanning transmission signal lines for providing scanning signals for the scanning lines, wherein the number of the scanning transmission signal lines is equal to one half of the number of the scanning lines; and
a plurality of scan switching circuits;
at least two adjacent scanning lines are connected to one scanning transmission signal line through one scanning switching circuit.
5. The display panel according to claim 4, wherein the scan switching circuit includes a third active switch and a fourth active switch;
the output ends of the third active switch and the fourth active switch are respectively connected to two adjacent scanning lines, and the input ends of the third active switch and the fourth active switch are connected to the same scanning transmission signal line;
the control end of the third active switch is used for inputting a first clock signal; the control end of the fourth active switch is used for inputting a second clock signal.
6. The display panel according to claim 5, wherein the scan switching circuit further comprises a first voltage boosting circuit and a second voltage boosting circuit;
the output end of the third active switch is connected to the corresponding scanning line through the first booster circuit;
the output end of the fourth active switch is connected to the corresponding scanning line through the second booster circuit.
7. The display panel according to claim 6, wherein the first boost circuit comprises a fifth active switch and a first capacitor;
the output end of the third active switch is connected to the control end of the fifth active switch, the output end of the fifth active switch is connected to the corresponding scanning line, and the input end of the fifth active switch is used for inputting a third clock signal;
two ends of the first capacitor are respectively connected to the control end of the fifth active switch and the output end of the fifth active switch;
the second boost circuit comprises a sixth active switch and a second capacitor;
the output end of the fourth active switch is connected to the control end of the sixth active switch, the output end of the sixth active switch is connected to the corresponding scanning line, and the input end of the sixth active switch is used for inputting a fourth clock signal;
and two ends of the second capacitor are respectively connected to the control end of the sixth active switch and the output end of the sixth active switch.
8. The display panel according to claim 6, wherein the scan switching circuit further comprises a first reset circuit and a second reset circuit;
the first reset circuit is connected with the first boosting circuit in parallel, and the second reset circuit is connected with the second boosting circuit in parallel.
9. The display panel according to claim 8, wherein the first reset circuit comprises a seventh active switch and an eighth active switch, an output terminal of the seventh active switch and an output terminal of the eighth active switch are connected to a Vss signal, a control terminal of the seventh active switch and a control terminal of the eighth active switch are connected to a first reset signal, an input terminal of the seventh active switch is connected to an output terminal of the third active switch, and an input terminal of the eighth active switch is connected to an output terminal of the fifth active switch;
the second reset circuit comprises a ninth active switch and a tenth active switch, wherein the output end of the ninth active switch and the output end of the tenth active switch are connected to the Vss signal, the control end of the ninth active switch and the control end of the tenth active switch are connected to a second reset signal, the input end of the ninth active switch is connected to the output end of the fourth active switch, and the input end of the tenth active switch is connected to the output end of the sixth active switch.
10. A display device comprising the display panel according to any one of claims 1 to 9 and a backlight module for providing a light source to the display panel.
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| CN114530118A (en) * | 2022-02-21 | 2022-05-24 | 广州华星光电半导体显示技术有限公司 | Display panel |
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