CN110136672B

CN110136672B - Display panel, driving method thereof and display device

Info

Publication number: CN110136672B
Application number: CN201910462597.4A
Authority: CN
Inventors: 熊娜娜
Original assignee: Shanghai Tianma AM OLED Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-05-30
Filing date: 2019-05-30
Publication date: 2021-05-14
Anticipated expiration: 2039-05-30
Also published as: CN110136672A

Abstract

The invention discloses a display panel, a driving method thereof and a display device. Therefore, under the condition that the voltage of the input signal is not changed, the range of the voltage input into the display panel is enlarged, particularly the variation range of the high voltage is enlarged, and the requirement of the display panel on the high voltage can be met.

Description

Display panel, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

With the continuous development of science and technology, more and more display devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present. The display device displays an image on a display panel. In general, a voltage is input to a display panel to display an image on the display panel. However, the range of the voltage input to the display panel is limited, and the requirement of the display panel for high voltage cannot be met.

Disclosure of Invention

The embodiment of the invention provides a display panel, a driving method thereof and a display device, which are used for meeting the requirement of the display panel on high voltage.

An embodiment of the present invention provides a display panel, including: the array substrate comprises a plurality of boosting control circuits positioned in a non-display area of the array substrate and a plurality of signal wires positioned on the array substrate; one of the boosting control circuits corresponds to at least one of the signal lines;

the signal input end of the boost control circuit is used for receiving input signals, and the boost control circuit is used for boosting the received voltage of the input signals and then providing the boosted voltage to the corresponding signal line through the signal output end of the boost control circuit.

The embodiment of the invention also provides a driving method of the display panel, wherein the display panel comprises a plurality of sub-pixels arranged in an array; the signal line is electrically connected with the plurality of sub-pixels; the driving method includes: in a driving period, the boost control circuit receives an input signal through the signal input end, boosts the voltage of the received input signal, and provides the boosted voltage to the corresponding signal line through the signal output end, so that the sub-pixel inputs a driving signal;

the driving period includes: an adjustment stage, a reset stage and a boosting stage; wherein the content of the first and second substances,

in the adjusting stage, the adjusting module provides an adjusting signal to the first node under the control of a second control signal;

in the reset phase, the reset module provides a reference signal to the second node under the control of a third control signal;

in the boosting stage, the boosting module supplies the data signal received by the signal input terminal to the first node under the control of a fourth control signal, couples the data signal input to the first node to the second node, and outputs the data signal to the signal line through the signal output terminal to input a driving signal to the subpixel.

The embodiment of the invention also provides a display device which comprises the display panel.

The invention has the following beneficial effects:

according to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the boost control circuit is arranged on the array substrate, so that the voltage of the received input signal is boosted by the boost control circuit and then provided to the corresponding signal line through the signal output end. Therefore, under the condition that the voltage of the input signal is not changed, the range of the voltage input into the display panel is enlarged, particularly the variation range of the high voltage is enlarged, and the requirement of the display panel on the high voltage can be met.

Drawings

Fig. 1a is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 1b is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 1c is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 1d is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a boost control circuit according to an embodiment of the present invention;

FIG. 3a is a timing diagram of a circuit according to an embodiment of the present invention;

FIG. 3b is a timing diagram of another circuit according to an embodiment of the present invention;

fig. 4a is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 4b is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 5 is a timing diagram of another embodiment of the present invention;

fig. 6a is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 6b is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 7 is a timing diagram of another embodiment of the present invention;

fig. 8 is a schematic structural diagram of another boost control circuit according to an embodiment of the present invention;

FIG. 9 is a timing diagram of another embodiment of the present invention;

fig. 10 is a schematic structural diagram of another boost control circuit according to an embodiment of the present invention;

FIG. 11 is a timing diagram of another circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

An embodiment of the present invention provides a display panel, as shown in fig. 1a to 1c, which may include: the display device comprises an array substrate 100, a plurality of boosting control circuits 200 positioned in a non-display area BB of the array substrate 100, and a plurality of signal lines 300 positioned on the array substrate 100; one of the boost control circuits 200 corresponds to at least one signal line 300. The signal input terminal IN of the boost control circuit 200 is used for receiving an input signal, and the boost control circuit 200 is used for boosting the voltage of the received input signal and then supplying the boosted voltage to the corresponding signal line 300 through the signal output terminal OUT of the boost control circuit 200.

According to the display panel provided by the embodiment of the invention, the boost control circuit is arranged on the array substrate, so that the voltage of the received input signal is boosted by the boost control circuit and then provided to the corresponding signal line through the signal output end. Therefore, under the condition that the voltage of the input signal is not changed, the range of the voltage input into the display panel is enlarged, particularly the variation range of the high voltage is enlarged, and the requirement of the display panel on the high voltage can be met.

In practical applications, a voltage signal is generally input to a display panel using at least one of elements such as a driver IC (Integrated Circuit), a PCB (Printed Circuit Board), and an FPC (Flexible Printed Circuit), so that an image is displayed on the display panel. The inventor has found through research that the output voltage range of the mainstream element (such as a driving IC) is generally: for example, 0 to 6v, and the cost of the driving device having a low output voltage range is low in consideration of the above device cost. However, the display panel requires a high voltage (e.g., 0 to 10v) in driving due to some reasons (e.g., caused by the efficiency of the light emitting device or the design of the driving circuit). The main low-cost driving IC has a limited output voltage range, and cannot meet the requirement of the display panel for high voltage. In order to solve the above problems and obtain a driver IC outputting a high voltage (e.g., 0 to 10v) without causing a cost increase, in the display panel according to the embodiment of the present invention, the boost control circuit is disposed on the array substrate, and the main low-cost driver IC may be combined, so that the voltage output by the main low-cost driver IC enters the boost control circuit, is boosted by the boost control circuit and then is input to the signal line, and then is transmitted to the sub-pixel through the signal line, thereby achieving an effect of inputting a high voltage to the display panel. Thus, the driving effect that can be achieved by a high-cost driver IC that outputs a high voltage can be achieved, thereby reducing the cost.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1a to 1c, the display panel may further include: a plurality of pixel units arranged in an array in the display area AA of the array substrate 100. Each pixel unit includes a plurality of sub-pixels 110. And the sub-pixel arrays in the display panel are arranged. Illustratively, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing may be performed by red, green, and blue to realize a color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color display may be realized by performing color mixing of red, green, blue, and white. Of course, in practical applications, the color of the sub-pixel in the pixel unit may be determined according to the practical application environment, and is not limited herein.

Liquid Crystal Display (LCD) panels have features of thin and light profile, power saving, and no radiation, and are widely used. The LCD panel operates on the principle of changing the arrangement of liquid crystal molecules in the liquid crystal layer by changing the voltage difference between two ends of the liquid crystal layer, so as to change the transmittance of the liquid crystal layer and display images. In particular implementations, the display panel may be a liquid crystal display panel. In an embodiment of the present invention, the sub-pixel may include a pixel electrode on the array substrate and a Thin Film Transistor (TFT) electrically connected to the pixel electrode. Of course, the array substrate is also provided with a gate line for transmitting a gate scanning signal and a data line for transmitting a data signal. In this way, a gate scanning signal is input to the TFT through the gate line to control the TFT to be turned on, so that a data signal transmitted through the data line is input to the pixel electrode, a voltage is input to the pixel electrode, and the liquid crystal molecules are driven to rotate to display an image.

In a specific implementation, the display panel may be an electroluminescent display panel, and in an embodiment of the present invention, the sub-pixel may include an electroluminescent Diode and a driving circuit for driving the electroluminescent Diode to emit Light. In addition, a gate line for transmitting a gate scanning signal and a data line for transmitting a data signal are also disposed on the array substrate. Therefore, a grid scanning signal is input to the driving circuit through the grid line to control the transistor in the driving circuit to be turned on, so that a data signal transmitted on the data line is input into the driving circuit, and the driving circuit generates current to drive the electroluminescent diode to emit light. Further, the electroluminescent diode may include: at least one of an OLED, a Micro-LED and a QLED. The general driving circuit may include a plurality of transistors such as a driving transistor and a switching transistor, and a storage capacitor, and the specific structure and the operation principle thereof may be the same as those in the prior art, and are not described herein again. The following description will be given taking an example in which the display panel is an electroluminescent display panel.

In particular implementations, the signal line may be electrically connected to a plurality of sub-pixels. For example, as shown in fig. 1a to 1c, the direction from the signal output terminal OUT of the boost control circuit to the display area AA is the first direction F1 (i.e., the direction indicated by the arrow F1), and the signal line 300 may extend along the first direction F1 to the display area AA of the array substrate 100. In the embodiment of the present invention, as shown in fig. 1a to 1c, the signal line 300 may include a data line for transmitting a data signal. Wherein one data line may be electrically connected to a column of sub-pixels correspondingly. Of course, the signal line may also include a signal line for realizing other signal transmission, and is not limited herein. Alternatively, the sub-pixels in the display panel are arranged in an array, and the first direction F1 may be parallel to the column direction or the row direction of the array.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1a to 1c, the non-display area BB of the array substrate 100 may further include: a plurality of first terminals 400; the signal input terminal IN of the boost control circuit 200 is electrically connected to the control unit through the first terminal 400. Illustratively, the first terminal 400 may be a conductive metal block such as a pad or a PIN (PIN) for binding the control unit and the signal input terminal IN of the boost control circuit 200. The control unit may include: at least one of a driver IC, a PCB, and an FPC. At least one of the driver IC, the PCB, and the FPC may be bonded (Bonding) to the first terminal so as to be assembled to the display panel, so that a voltage is input to the display panel, and the display panel may realize an image display function. Illustratively, when the signal line is a data line, the driving IC may be a source driving IC. The source driver ICs will be described in detail below.

In practical implementation, in the embodiment of the present invention, as shown in fig. 1a, one boost control circuit 200 corresponds to one first terminal 400 and one signal line 300. The signal input terminal IN of the boost control circuit 200 is electrically connected to the corresponding first terminal 400, and the boost output terminal OUT is electrically connected to the signal line 300. That is, the first terminal 400 is electrically connected to the signal line 300 through the corresponding boost control circuit 200, and the first terminal 400 is not directly electrically connected to the signal line 300. For example, when the signal line is a data line and the control unit is a source driver IC, the source driver IC may output a data signal to the first terminal 400 to load the data signal on the first terminal 400, and the signal input terminal IN of the boost control circuit 200 receives the data signal as an input signal to boost the voltage of the data signal loaded on the electrically connected first terminal 400 and then provide the boosted voltage to the electrically connected data line through the boost output terminal OUT.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1b and fig. 1c, the non-display area of the array substrate may further include: a plurality of multiplexers 500. One multiplexer 500 may correspond to a plurality of signal lines 300. Illustratively, one multiplexer 500 may be made to correspond to 3 signal lines 300. One multiplexer 500 may correspond to 6 signal lines 300, and the number of signal lines corresponding to one multiplexer 500 may be determined according to the actual application environment, and is not limited herein. The number of first terminals can be reduced by providing the multiplexer 500, and the area of the fan-out area can be reduced. Moreover, the operation and structure of the multiplexer 500 may be substantially the same as those in the prior art, and will not be described herein.

In practical implementation, in the embodiment of the present invention, as shown in fig. 1b, one first terminal 400 corresponds to one boost control circuit 200 and one multiplexer 500. The output terminal of one multiplexer 500 is electrically connected to a plurality of corresponding signal lines, and the signal input terminal IN of the boost control circuit 200 is electrically connected to the first terminal 400, and the signal output terminal OUT is electrically connected to the input terminal of the multiplexer 500. That is, the first terminal 400 is electrically connected to the input terminal of the multiplexer 500 through the corresponding boost control circuit 200, and the first terminal 400 is not directly electrically connected to the input terminal of the multiplexer 500. For example, when the signal line is a data line and the control unit is a source driver IC, the source driver IC may output a data signal to the first terminal 400 to load the data signal on the first terminal 400, and the signal input terminal IN of the boost control circuit 200 receives the data signal as an input signal to boost the voltage of the data signal loaded on the electrically connected first terminal 400 and then provides the boosted voltage to the input terminal of the electrically connected multiplexer 500 through the signal output terminal OUT, so that the received data signal is provided to the data line through the multiplexer 500. Of course, IN other alternative embodiments of the present application, the signal line may also be a power signal line (e.g., a PVEE trace or a PVDD trace), the first terminal 400 is loaded with a power signal, and the signal input terminal IN of the boost control circuit 200 receives the power signal as an input signal, so as to boost the power signal and directly provide the boosted power signal to the signal line. Therefore, the additional arrangement of a multiplexer and wiring for transmitting signals to the multiplexer is not needed, the circuit structure is simplified, the non-display area space is saved, and the realization of a narrow frame is facilitated.

In practical implementation, as shown in fig. 1c, one first terminal 400 corresponds to one multiplexer 500, and one signal line 300 corresponds to one boost control circuit 200 in the embodiment of the present invention. And a signal input terminal IN of the boost control circuit 200 is electrically connected to an output terminal of the multiplexer 500, and a signal output terminal OUT is electrically connected to a signal line. That is, the first terminal 400 is directly electrically connected to the input terminal of the multiplexer 500, and the output terminal of the multiplexer 500 is electrically connected to the signal line through the corresponding boosting control circuit 200, instead of the output terminal of the multiplexer 500 being directly electrically connected to the data line. Illustratively, when the signal line is a data line and the control unit is a source driver IC, the source driver IC may output a data signal to the first terminal 400 to load the data signal on the first terminal 400, the data signal enters the multiplexer 500 to be input to the signal input terminal IN of the boost control circuit 200 through the multiplexer 500, and the signal input terminal IN of the boost control circuit 200 receives the data signal as an input signal to boost the voltage of the received input signal and then provides the boosted voltage to the electrically connected data line through the signal output terminal OUT.

In a specific implementation, in the embodiment of the present invention, the boost control circuit may be disposed between the orthographic projection of the first terminal on the array substrate and the orthographic projection of the multiplexer on the array substrate. Or the positive projection of the boost control circuit on the array substrate is positioned between the positive projection of the multiplexer on the array substrate and the display area, and the boost control circuit is arranged. Of course, in practical applications, the specific position of the boost control circuit on the array substrate may be designed and determined according to practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present invention, as shown in fig. 1a to fig. 2, the boost control circuit 200 may include: an adjustment module 210, a reset module 220, and a boost module 230. The adjusting module 210 is configured to provide the adjusting signal VS to the first node N1 under the control of the second control signal CS 2. The reset module 220 is used for providing a reference signal VREF to the second node N2 under the control of a third control signal CS 3. And the voltage boost module 230 is configured to provide the signal received by the signal input terminal IN to the first node N1 under the control of the fourth control signal CS4, and couple the signal input to the first node N1 to the second node N2 and output the coupled signal through the signal output terminal OUT. That is, the first node N1 is electrically connected to the signal input terminal IN through the boost block 230, and the second node N2 is also electrically connected to the signal output terminal OUT through the boost block 230. The first node N1 and the second node N2 may be coupled by the boost module 230.

In practical implementation, in the embodiment of the present invention, the voltage of the adjusting signal VS is a negative voltage. In practical applications, the voltage of the adjusting signal VS may be determined according to practical application environments, and is not limited herein.

In specific implementation, in the embodiment of the invention, as shown in fig. 1d and fig. 2, the non-display area BB of the array substrate 100 may further include: the signal output circuit 600 is controlled. All the adjusting modules 210 are electrically connected to the control signal output circuit 600, and are configured to receive the second control signal CS 2. And, all the reset modules 220 are electrically connected to the control signal output circuit 600 for receiving the third control signal CS 3. And all the boosting modules 230 are electrically connected with the control signal output circuit 600 for receiving the fourth control signal CS 4. This may output the second control signal CS2 to all the adjusting modules 210, the third control signal CS3 to all the reset modules 220, and the fourth control signal CS4 to all the boosting modules 230 through the control signal output circuit 600. For example, the array substrate 100 may be provided with a control signal output circuit 600, so that the occupied space of the non-display area BB can be reduced. Of course, the array substrate 100 may also be provided with two control signal output circuits 600, the timing of the second control signal CS2 output by the two control signal output circuits 600 is the same, the timing of the third control signal CS3 output by the two control signal output circuits 600 is the same, and the timing of the fourth control signal CS4 output by the two control signal output circuits 600 is the same. This can improve the driving ability of the second control signal CS2, the third control signal CS3, and the fourth control signal CS 4. Further, all the boost control circuits 200 may be integrated, and the two control signal output circuits 600 may be provided on both sides of the integrated circuit, respectively.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1a to fig. 2, the adjusting module 210 may include: a second switch K2; a control terminal of the second switch K2 is configured to receive the second control signal CS2, a first terminal of the second switch K2 is configured to receive the adjustment signal VS, and a second terminal of the second switch K2 is electrically connected to the first node N1. Further, the second switch K2 may provide the adjustment signal VS to the first node N1 when in a conductive state under the control of the second control signal CS 2.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1a to fig. 2, the reset module 220 may include: a third switch K3; a control terminal of the third switch K3 is configured to receive the third control signal CS3, a first terminal of the third switch K3 is configured to receive the reference signal VREF, and a second terminal of the third switch K3 is electrically connected to the second node N2. Further, the third switch K3 may provide the reference signal VREF to the second node N2 when it is in a conductive state under the control of the third control signal CS 3.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1a to fig. 2, the boost module 230 may include: a fourth switch K4, a fifth switch K5, a sixth switch K6 and a coupling capacitor C0. The control terminal of the fourth switch K4 is configured to receive the fourth control signal CS4, the first terminal of the fourth switch K4 is used as the signal input terminal IN, and the second terminal of the fourth switch K4 is electrically connected to the first terminal of the fifth switch K5. A control terminal of the fifth switch K5 is electrically connected to the second node N2, and a second terminal of the fifth switch K5 is electrically connected to the first node N1. A control terminal of the sixth switch K6 is configured to receive the fourth control signal CS4, a first terminal of the sixth switch K6 is electrically connected to the second node N2, and a second terminal of the sixth switch K6 is used as a signal output terminal OUT. And a coupling capacitor C0 electrically connected between the first node N1 and the second node N2. Further, the fourth switch K4 may provide the signal of the signal input terminal IN to the first terminal of the fifth switch K5 when it is IN a turn-on state under the control of the fourth control signal CS 4. The fifth switch K5 may provide a signal input to a first terminal of the fifth switch K5 to the first node N1 when it is in a conductive state under the control of the signal of the second node N2. The sixth switch K6 may turn on the second node N2 and the signal output terminal OUT when it is in a conductive state under the control of the fourth control signal CS 4. And, the coupling capacitor C0 may store voltages input to the first node N1 and the second node N2, and may keep a voltage difference between the first node N1 and the second node N2 stable when the second node is in a floating state to couple a signal input to the first node to the second node.

In specific implementation, in the embodiment of the present invention, the voltage VREF of the reference signal VREF satisfies the following formula: 0V < Vref < Vd + Vth; where Vd represents the voltage of the input signal and Vth represents the threshold voltage of the fifth switch K5. Illustratively, the voltage Vref may be a fixed voltage, which may reduce the driving difficulty of the driving IC. Just in order to satisfy the normal operation of the boost control circuit, Vref cannot be larger than Vd + Vth. Of course, in practical applications, the specific value of the voltage Vref may be determined by design according to practical application environments, and is not limited herein.

The switch in the above embodiments of the present invention may be a Thin Film Transistor (TFT), a Low Temperature Polysilicon (LTPS) Transistor, or a Metal Oxide Semiconductor (MOS) Transistor, and is not limited herein. In a specific implementation, the control terminal of the switch may be a gate, the first terminal of the switch may be a source, and the second terminal of the switch may be a drain, according to the type of the transistor and the input signal; alternatively, the first terminal is used as the drain thereof, and the second terminal is used as the source thereof, which are not specifically distinguished herein.

In specific implementation, in order to reduce the manufacturing process, all the switches may be configured as P-type transistors as shown in fig. 2. Further, the P-type transistor is turned off by a high level signal and turned on by a low level signal. It should be understood that, in the embodiments of the present invention, only the case where the switch is a P-type transistor is described as an example, and the design principle of the case where the switch is an N-type transistor is the same as that of the present invention, and the present invention also falls within the protection scope of the present invention.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of the display panel, including: in the driving period, the boost control circuit receives an input signal through the signal input end, boosts the voltage of the received input signal, and provides the boosted voltage to the corresponding signal line through the signal output end to input a driving signal to the sub-pixel. That is, the boost control circuit may be configured to receive an input signal through the signal input terminal during a driving period, boost a voltage of the received input signal, and supply the boosted voltage to the corresponding signal line through the signal output terminal to input a driving signal to the subpixel. For example, when the signal line includes a data line, the input signal may be a data signal. The boosting control circuit may be configured to receive the data signal through the signal input terminal during the driving period, boost a voltage of the received data signal, and provide the boosted data signal to the corresponding data line through the signal output terminal, so as to provide the boosted data signal to the sub-pixel through the data line, and input the boosted data signal into the sub-pixel as the driving signal.

In practical implementation, in an embodiment of the present invention, the driving period may include: an adjustment stage, a reset stage and a boosting stage; wherein the content of the first and second substances,

in the adjusting stage, the adjusting module provides an adjusting signal to the first node under the control of the second control signal;

in a reset phase, the reset module provides a reference signal to the second node under the control of a third control signal;

in the boosting stage, the boosting module supplies the data signal received by the signal input end to the first node under the control of the fourth control signal, couples the data signal input to the first node to the second node, and outputs the data signal to the signal line through the signal output end to input the driving signal to the sub-pixel.

For example, in practical implementation, in an embodiment of the present invention, as shown in fig. 2 and fig. 3a, the driving period T may include: an adjustment phase t1, a reset phase t2, and a boosting phase t 3; wherein the content of the first and second substances,

the adjusting module 210 may be configured to provide the adjusting signal VS to the first node N1 under the control of the second control signal CS2 during the adjusting phase t 1;

the reset module 220 may be configured to provide the reference signal VREF to the second node N2 under the control of the third control signal CS3 during the reset phase t 2;

the boosting module 230 may be configured to provide the input signal received by the signal input terminal IN to the first node N1 under the control of the fourth control signal CS4 during the boosting period t3, and couple the signal input to the first node to the second node N2, and then output the signal to the signal line through the signal output terminal OUT to input the driving signal to the sub-pixel. For example, when the signal line includes a data line, the input signal may be a data signal. The boosting module 230 is configured to provide the data signal received by the signal input terminal IN to the first node N1 under the control of the fourth control signal CS4 during the boosting period t3, and couple the data signal input to the first node to the second node N2, and then output the data signal to the data line through the signal output terminal OUT to input the driving signal to the sub-pixel.

Further, in the embodiment of the present invention, the voltages of the adjustment signals corresponding to the sub-pixels in the same row and different columns may be the same. This can reduce the driving difficulty of the driver IC. Furthermore, the voltages of the adjustment signals corresponding to each sub-pixel can be the same, so that each boost control module can be electrically connected with the same signal end for outputting the adjustment signal, and therefore the occupied space of a non-display area is reduced, and the driving difficulty of a driving IC is further reduced.

The operation of the boost control circuit will be described with reference to the circuit timing diagram shown in fig. 3a, taking the structure of the boost control circuit shown in fig. 2 as an example. In the driving period T, the adjustment signal VS is a negative voltage signal with a fixed voltage value, and the reference signal VREF is a positive voltage signal with a fixed voltage value.

The drive period T has: an adjustment phase t1, a reset phase t2, and a boost phase t 3.

In the adjustment phase t1, since the third control signal CS3 is a high-level signal, the third switch K3 can be controlled to be turned off. Also, since the fourth control signal CS4 is a high level signal, both the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the second control signal CS2 is a low signal, the second switch K2 can be controlled to be turned on to provide the adjusting signal VS to the first node N1, so that the voltage of the first node N1 is the voltage VS of the adjusting signal VS.

In the reset phase t2, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the fourth control signal CS4 is a high level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the third control signal CS3 is a low-level signal, the third switch K3 can be controlled to be turned on to provide the reference signal VREF to the second node N2, so that the voltage of the second node N2 is the voltage VREF of the reference signal VREF. The voltage difference across the capacitor C0 at this time is: Vref-Vs.

In the boosting period t3, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the third control signal CS3 is a high level signal, the third switch K3 may be controlled to be turned off. Since the fourth control signal CS4 is a low-level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned on. The signal input terminal IN receives an input signal having a voltage Vd, and the turned-on fourth switch K4 may provide the input signal having the voltage Vd to the first terminal of the fifth switch S5. Since the voltage of the second node N2 is Vref, that is, the voltage of the control terminal of the fifth switch S5 is Vref, and 0V < Vref < Vd + Vth, the fifth switch S5 can be turned on according to the combined action of the voltages of the control terminal and the first terminal thereof. The turned-on fifth switch S5 may provide an input signal having a voltage Vd input to a first terminal thereof to the first node N1, so that the voltage of the first node N1 jumps from Vs to Vd. Due to the bootstrap coupling effect of the capacitor C0, in order to keep the voltage difference across the capacitor C0 at Vref-Vs, the voltage of the second node N2 may jump to: vd + Vref-Vs. The turned-on sixth switch K6 may supply the voltage Vd + Vref-Vs to the signal line so that a signal having the voltage Vd + Vref-Vs is transmitted on the signal line. As is apparent from the voltage Vd of the signal input to the signal input terminal IN and the voltage Vd + Vref-Vs input to the signal line, the voltage difference Δ V output from the signal output terminal OUT can be increased by Vref-Vs by the action of the boost control circuit.

It should be noted that, in conjunction with fig. 3a, one driving cycle T may include a single occurrence of the adjusting phase T1, the reset phase T2, and the boosting phase T3. That is, one driving period T has one adjusting phase T1, one reset phase T2, and one boosting phase T3.

Further, the following describes the operation of the display panel provided by the embodiment of the present invention with reference to the structures shown in fig. 1a and fig. 2 and the circuit timing diagram shown in fig. 3 b. As shown in fig. 3b, G1-G3 represent gate scan signals transmitted through gate lines G1-G3 electrically connected to the first to third rows of sub-pixels in a direction S1 opposite to the first direction F1 (i.e., the direction pointed by the arrow S1). DATA represents a DATA signal transmitted on a first terminal. In the driving period T, the adjustment signal VS is a negative voltage signal having a fixed voltage value, and the reference signal VREF is a signal having a fixed voltage value. The signal line 300 is taken as a data line as an example.

In the boosting period t3, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the third control signal CS3 is a high level signal, the third switch K3 may be controlled to be turned off. Since the fourth control signal CS4 is a low-level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned on. In the t31 phase, the DATA signal DATA having the voltage Vd1 is loaded to the first terminal 400, and the turned-on fourth switch K4 may provide the DATA signal DATA having the voltage Vd1 to the first terminal of the fifth switch S5. Since the voltage of the second node N2 is Vref, that is, the voltage of the control terminal of the fifth switch S5 is Vref, and 0V < Vref < Vd1+ Vth, the fifth switch S5 may be turned on according to the combined action of the voltages of the control terminal and the first terminal thereof. The turned-on fifth switch S5 may provide the DATA signal DATA having the voltage Vd1, input to the first terminal thereof, to the first node N1 to make the voltage of the first node N1 jump from Vs to Vd 1. Due to the bootstrap coupling effect of the capacitor C0, in order to keep the voltage difference across the capacitor C0 at Vref-Vs, the voltage of the second node N2 may jump to: vd1+ Vref-Vs. The turned-on sixth switch K6 may supply a voltage Vd1+ Vref-Vs to the data line so that the data signal having the voltage Vd1+ Vref-Vs is transferred on the data line. And, the first row of sub-pixels are turned on under the control of the gate scan signal G1 transmitted on the gate line G1 to input a data signal having a voltage Vd1+ Vref-Vs as a driving signal, thereby driving the row of sub-pixels for light emitting display. As can be seen from the voltage Vd1 applied to the first terminal 400 and the voltage Vd1+ Vref-Vs input to the data line 300, the voltage increase voltage difference Δ V becomes Vref-Vs by the operation of the boost control circuit.

Thereafter, in a period of t32, the DATA signal DATA having the voltage Vd2 is loaded to the first terminal 400, and the turned-on fourth switch K4 may provide the DATA signal DATA having the voltage Vd2 to the first terminal of the fifth switch S5. Since the voltage of the second node N2 is Vref, that is, the voltage of the control terminal of the fifth switch S5 is Vref, and 0V < Vref < Vd2+ Vth, the fifth switch S5 may be turned on according to the combined action of the voltages of the control terminal and the first terminal thereof. The turned-on fifth switch S5 may provide the DATA signal DATA having the voltage Vd2, input to the first terminal thereof, to the first node N1 to make the voltage of the first node N1 jump from Vs to Vd 2. Due to the bootstrap coupling effect of the capacitor C0, in order to keep the voltage difference across the capacitor C0 at Vref-Vs, the voltage of the second node N2 may jump to: vd2+ Vref-Vs. The turned-on sixth switch K6 may supply a voltage Vd2+ Vref-Vs to the data line so that the data signal having the voltage Vd2+ Vref-Vs is transferred on the data line. And, the second row of sub-pixels are turned on under the control of the gate scan signal G2 transmitted on the gate line G2 to input the data signal having the voltage Vd2+ Vref-Vs as the driving signal, thereby driving the row of sub-pixels for light emitting display. As can be seen from the voltage Vd2 applied to the first terminal 400 and the voltage Vd2+ Vref-Vs input to the data line 300, the voltage increase voltage difference Δ V becomes Vref-Vs by the operation of the boost control circuit.

In the t33 phase, the DATA signal DATA having the voltage Vd3 is loaded to the first terminal 400, and the turned-on fourth switch K4 may provide the DATA signal DATA having the voltage Vd3 to the first terminal of the fifth switch S5. Since the voltage of the second node N2 is Vref, that is, the voltage of the control terminal of the fifth switch S5 is Vref, and 0V < Vref < Vd3+ Vth, the fifth switch S5 may be turned on according to the combined action of the voltages of the control terminal and the first terminal thereof. The turned-on fifth switch S5 may provide the DATA signal DATA having the voltage Vd3, input to the first terminal thereof, to the first node N1 to make the voltage of the first node N1 jump from Vs to Vd 3. Due to the bootstrap coupling effect of the capacitor C0, in order to keep the voltage difference across the capacitor C0 at Vref-Vs, the voltage of the second node N2 may jump to: vd3+ Vref-Vs. The turned-on sixth switch K6 may supply a voltage Vd3+ Vref-Vs to the data line so that the data signal having the voltage Vd3+ Vref-Vs is transferred on the data line. And, the third row of sub-pixels are turned on under the control of the gate scan signal G3 transmitted on the gate line G3 to input the data signal having the voltage Vd3+ Vref-Vs as the driving signal, thereby driving the row of sub-pixels for light emitting display. As can be seen from the voltage Vd3 applied to the first terminal 400 and the voltage Vd3+ Vref-Vs input to the data line 300, the voltage increase voltage difference Δ V becomes Vref-Vs by the operation of the boost control circuit.

The process of inputting the boosted driving signals to the sub-pixels in the remaining rows can be analogized according to the stages from t31 to t33, which is not described herein again.

Through the above working process, the voltage VS of the adjustment signal VS is set to a fixed voltage value, so that the variation frequency of the adjustment module can be reduced, and the power consumption can be reduced.

Moreover, the structures of the display panels shown in fig. 1b and fig. 1c are combined with the working process shown in fig. 3b, which can be analogized in turn, and are not described herein again. It should be noted that, when the display panel includes the multiplexer 500, taking 3 data lines corresponding to 1 multiplexer 500 as an example, as shown in fig. 1b, when scanning the first row, the signal loaded on the first terminal 400 is boosted by the boost control circuit 200 and then provided to the multiplexer 500, and the multiplexer 500 sequentially outputs the signals boosted by the boost control circuit 200 to the three data lines, so that the driving signals are sequentially transmitted on the three data lines, and Vs corresponding to the driving signals on the three data lines are the same. When scanning the second row, the signals loaded on the first terminal 400 are boosted by the boost control circuit 200 and then provided to the multiplexer 500, the multiplexer 500 sequentially outputs the signals boosted by the boost control circuit 200 to the three data lines, so that the driving signals are sequentially transmitted on the three data lines, and Vs corresponding to the driving signals on the three data lines are the same. For the same reason, the description is omitted here. Therefore, when each row is scanned, Vs corresponding to the driving signals input to each data line are the same, so that the change frequency of the adjusting module can be reduced, and the power consumption is reduced.

Generally, in the process of scanning an image of one frame by the display panel, the scanning is moved from the upper side to the lower side of the image. After scanning one frame of image, the scanning of a new frame of image is started from the lower side of the image to the upper side of the image. This makes it possible to refer to the time interval between the end of the scanning of the image of the previous frame and the start of the scanning of the image of the next frame as Blanking time (Blanking time). During the blanking period, the data signal for displaying the image is not transmitted. In order to avoid the adjustment phase t1 and the reset phase t2 occupying the time for scanning one frame image, the adjustment phase t1 and the reset phase t2 may be set within the blanking time. Since the data signal needs to be input to the sub-pixel during the time of scanning one frame image, the process of scanning one frame image may be performed in the boosting stage t 3.

In addition, as can be seen from the above operation process, one driving cycle includes a single adjustment phase t1, a reset phase t2, and a boosting phase t 3. In the same boosting period t3, each row of sub-pixels is scanned, for example, a driving signal may be input to the first row of sub-pixels, then a driving signal may be input to the second row of sub-pixels, and then a driving signal may be input to the third row of sub-pixels, so that a driving signal may be input to each row of sub-pixels in sequence. The rest can be analogized in turn, and the description is omitted here.

Fig. 4a and 4b are schematic views of another display panel provided in the embodiment of the present application. Fig. 2 shows a schematic diagram of a boost control circuit, which is a modification of some of the embodiments described above. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In practical implementation, in the embodiment of the present invention, the boost control circuit 200 may be configured to input the driving signals to different sub-pixels for at least two driving periods; wherein, the voltages of the adjusting signals in the same driving period are the same; and the voltage of the adjusting signal in the driving period corresponding to the sub-pixel close to the signal output end is greater than the voltage of the adjusting signal in the driving period corresponding to the sub-pixel far from the signal output end. Illustratively, in the implementation, the data lines are at least electrically connected to drive two sub-pixels to emit light, as shown in fig. 4a and 4b, in the embodiment of the present invention, during the time taken to scan the same frame image, for the same boost control circuit 200, the boost control circuit 200 inputs a drive signal to a first sub-pixel in one drive period, and the boost control circuit 200 inputs a drive signal to a second sub-pixel in another drive period. The first sub-pixel is close to the signal output end OUT, and the second sub-pixel is far away from the signal output end OUT, namely the first sub-pixel is located between the second sub-pixel and the signal output end OUT. Since the first sub-pixel is closer to the signal output end OUT, the voltage drop of signal transmission is smaller. And the second sub-pixel is far away from the signal output end OUT, so that the voltage drop of signal transmission is large. Therefore, by enabling the voltage of the adjustment signal in the driving period corresponding to the first sub-pixel to be greater than the voltage of the adjustment signal in the driving period corresponding to the second sub-pixel, the voltage difference Δ V corresponding to the driving signal input by the second sub-pixel can be greater than the voltage difference Δ V corresponding to the driving signal input by the first sub-pixel, so as to compensate for the loss of the voltage received by the sub-pixel farther from the signal output end OUT, and thus, the voltage value input to each sub-pixel is ensured to be an ideal voltage value as far as possible.

It should be noted that just in order to satisfy the normal operation of the boost control circuit, Vref needs to satisfy the condition: 0V < Vref < Vd + Vth, which makes the voltage variation range of Vref small, resulting in a small degree of voltage adjustability of Vref. And also that the voltage value of Vref is required. So that the voltage of Vref cannot be changed as much as the voltage Vs of the adjustment signal with driving of different pixel rows and pixel columns. Therefore, by changing the voltage Vs, the voltage variation range of Δ V can be made large, and the degree of adjustability of Δ V can be improved.

In particular implementation, in the embodiment of the present invention, as shown in fig. 4a, in the first direction F1, the boost control circuit may be configured to output a driving signal to the sub-pixels on the electrically connected signal lines for at least two adjacent driving periods; wherein, the voltage of the adjusting signal in the last driving period in the adjacent driving periods is larger than the voltage of the adjusting signal in the next driving period. That is, the sub-pixel receiving the driving signal in the previous driving period may serve as the first sub-pixel, and the sub-pixel receiving the driving signal in the next driving period may serve as the second sub-pixel.

In practical implementation, in the embodiment of the invention, as shown in fig. 4a, the second direction F2 may be the same as the first direction F1, and the signal line 300 is electrically connected to the first to mth sub-pixels 110_1 to 110_ M arranged along the second direction F2 (i.e., the direction indicated by the arrow F2); wherein M is not less than 2 and M is an integer; m is more than or equal to 1 and less than or equal to M, and M is an integer. Illustratively, when the signal lines include data lines, M may be the same as the total number of rows of subpixels in the display panel. Further, in the second direction F2, the boost control circuit 200 may be used to provide the mth drive signal to the mth subpixel 110 — m in the mth drive period. The voltages of the driving signals provided to the sub-pixels in different driving periods may be the same or different, and need to be determined according to the voltage of the data signal, which is not limited herein.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4a, the second direction F2 may be the same as the first direction F1, and the voltages of the adjustment signal VS received by the boost control circuit 200 are sequentially decreased from the 1 st to the mth driving cycles. That is, the voltages VS _1 to VS _ M of the adjustment signal VS in the 1 st to M-th driving periods are sequentially decreased. For example, taking M ═ 3 as an example, as shown in fig. 4a and 5, the voltage VS _2 of the adjustment signal VS in the 2 nd driving period T _2 is smaller than the voltage VS _1 of the adjustment signal VS in the 1 st driving period T _1, and the voltage VS _3 of the adjustment signal VS in the 3 rd driving period T _3 is smaller than the voltage VS _2 of the adjustment signal VS in the 2 nd driving period T _ 2. Since the first sub-pixel 110_1 is closest to the signal output terminal OUT, the mth sub-pixel 110_ M is farthest from the signal output terminal OUT, and the second to mth sub-pixels 110_2 to 110_ M-1 are sequentially farther from the signal output terminal OUT, the voltages VS _1 to VS _ M of the adjustment signal VS are sequentially decreased, so that the loss of the voltage received by each sub-pixel can be sequentially compensated, and the voltage value input to each sub-pixel is ensured to be an ideal voltage value as much as possible.

Alternatively, in practical implementation, in the embodiment of the present invention, as shown in fig. 4b, in a direction opposite to the first direction F1 (i.e., the direction indicated by the arrow F2), the boost control circuit 200 may be configured to output the driving signals to the sub-pixels on the electrically connected signal lines for at least two adjacent driving periods; wherein the voltage of the adjustment signal in the previous driving period in the adjacent driving periods is smaller than the voltage of the adjustment signal in the next driving period. That is, the sub-pixel receiving the driving signal in the previous driving period may serve as the second sub-pixel, and the sub-pixel receiving the driving signal in the next driving period may serve as the first sub-pixel.

In practical implementation, as shown in fig. 4b, the second direction F2 may be opposite to the first direction F1, and the signal line 300 is electrically connected to the first to mth sub-pixels 110_1 to 110_ M arranged along the second direction F2 (i.e., the direction indicated by the arrow F2); wherein M is not less than 2 and M is an integer; m is more than or equal to 1 and less than or equal to M, and M is an integer. Illustratively, when the signal lines include data lines, M may be the same as the total number of rows of subpixels in the display panel. Further, in the second direction F2, the boost control circuit 200 may be used to provide the mth drive signal to the mth subpixel 110 — m in the mth drive period. The driving signals provided to the sub-pixels in different driving periods may be the same or different, and need to be determined according to the voltage of the data signal, which is not limited herein.

In practical implementation, in the embodiment of the present invention, as shown in fig. 4b, the second direction F2 may be opposite to the first direction F1, and the voltages of the adjustment signals VS received by the boost control circuit 200 sequentially increase from the 1 st to the mth driving periods. That is, the voltages VS _1 to VS _ M of the adjustment signal VS in the 1 st to M-th driving periods sequentially increase. Illustratively, taking M ═ 3 as an example, the voltage VS _2 of the adjustment signal VS in the 2 nd drive period T _2 is greater than the voltage VS _1 of the adjustment signal VS in the 1 st drive period T _1, and the voltage VS _3 of the adjustment signal VS in the 3 rd drive period T _3 is greater than the voltage VS _2 of the adjustment signal VS in the 2 nd drive period T _ 2. Since the first sub-pixel 110_1 is farthest from the signal output terminal OUT, the mth sub-pixel 110_ M is closest to the signal output terminal OUT, and the second to mth sub-pixels 110_2 to 110_ M-1 are sequentially closer to the signal output terminal OUT, the voltages VS _1 to VS _ M of the adjustment signal VS are sequentially increased, so that the loss of the voltage received by each sub-pixel can be sequentially compensated, and the voltage value input to each sub-pixel is ensured to be an ideal voltage value as much as possible.

Further, in practical implementation, in the embodiment of the present invention, the voltage of the adjustment signal received by the boost control circuit may be sequentially changed by equal difference according to the change of the driving period. Wherein, the difference value Δ Vs between the voltages of the adjusting signals of two adjacent driving periods satisfies the formula:

for example, taking M ═ 3 as an example, as shown in fig. 4a and 5, the voltage difference between the voltages Vs _2 and Vs _1 may be substantially equal to the voltage difference between the voltages Vs _3 and Vs _ 2. And the number of the first and second electrodes,

it should be noted that the description of equality in the present invention means equality within the error range.

Further, in the embodiment of the present invention, the voltages of the adjustment signals corresponding to the sub-pixels in the same row and different columns may be the same. This can reduce the driving difficulty of the driver IC.

The operation of the display panel provided by the embodiment of the present invention will be described with reference to the structure shown in fig. 2 and fig. 4a and the circuit timing diagram shown in fig. 5, taking the second direction F2 as the same as the first direction F1, and taking the case that the voltage of the adjustment signal VS received by the boost control circuit 200 is sequentially decreased from 1 st to M th driving periods. Taking M as 3 as an example, as shown in fig. 5, G1 to G3 represent gate scan signals transmitted through gate lines G1 to G3 electrically connected to the first to third rows of sub-pixels along the first direction F1. DATA represents a DATA signal transmitted on the first terminal 400. In each of the driving periods T _1 to T _3, the reference signal VREF has a fixed voltage value. The adjusting signal VS in the same driving period is a negative voltage signal with a fixed voltage value, and the voltages VS _1 to VS _3 of the adjusting signal VS are sequentially decreased in the first to third driving periods T _1 to T _ 3.

Scanning the first to mth sub-pixel rows line by line along the second direction F2 during one frame of image scanning by the display panel; and performing an m-th driving period while scanning the m-th sub-pixel row, so that the sub-pixels in the m-th sub-pixel row are inputted with the driving signals.

Specifically, when the first subpixel row is scanned, the DATA signal DATA having the voltage Vd1 is applied to the first terminal 400, and the subpixels in the first subpixel row are turned on under the control of the gate scan signal G1 transmitted on the gate line G1. It should be noted that, as shown in fig. 4a, the multiplexer 500 may be electrically connected to 3 data lines, and when scanning the first sub-pixel row, one multiplexer 500 sequentially inputs data signals to the electrically connected 3 data lines, so that the corresponding 3 sub-pixels sequentially input driving signals. The voltages Vd1 corresponding to the 3 sub-pixels may be the same or different, and may be determined according to the actual application environment, which is not limited herein. For the same reason, the description is omitted here.

The 1 st driving period T _1 is performed while the first subpixel row is scanned. In the adjustment phase t1_1, the third switch K3 can be controlled to be turned off because the third control signal CS3 is a high-level signal. Also, since the fourth control signal CS4 is a high level signal, both the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the second control signal CS2 is a low-level signal, the second switch K2 can be controlled to be turned on to provide the adjustment signal Vs with the voltage Vs _1 to the first node N1, so that the voltage of the first node N1 is the voltage Vs _1 of the adjustment signal Vs.

In the reset phase t2_1, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the fourth control signal CS4 is a high level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the third control signal CS3 is a low-level signal, the third switch K3 can be controlled to be turned on to provide the reference signal VREF to the second node N2, so that the voltage of the second node N2 is the voltage VREF of the reference signal VREF. The voltage difference across the capacitor C0 at this time is: Vref-Vs _ 1.

In the boosting phase t3_1, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the third control signal CS3 is a high level signal, the third switch K3 may be controlled to be turned off. Since the fourth control signal CS4 is a low-level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned on. The turned-on fourth switch K4 may provide the DATA signal DATA having the voltage Vd1 to a first terminal of the fifth switch S5. Since the voltage of the second node N2 is Vref, that is, the voltage of the control terminal of the fifth switch S5 is Vref, and 0V < Vref < Vd1+ Vth, the fifth switch S5 may be turned on according to the combined action of the voltages of the control terminal and the first terminal thereof. The turned-on fifth switch S5 may provide the DATA signal DATA having the voltage Vd1 input to the first terminal thereof to the first node N1 to jump the voltage of the first node N1 from Vs _1 to Vd 1. Due to the bootstrap coupling effect of the capacitor C0, in order to keep the voltage difference across the capacitor C0 at Vref-Vs _1, the voltage of the second node N2 may jump to: vd1+ Vref Vs _ 1. The turned-on sixth switch K6 may provide a voltage Vd1+ Vref-Vs _1 to the input terminal of the multiplexer 500, so that a signal having a voltage Vd1+ Vref-Vs _1 is input to the data line through the multiplexer 500, so that a data signal having a voltage Vd1+ Vref-Vs _1 is transmitted on the data line, and thus the data signal having a voltage Vd1+ Vref-Vs _1 is input to the first row of sub-pixels as a driving signal, thereby driving the row of sub-pixels to perform light emitting display. As can be seen from the voltage Vd1 applied to the first terminal 400 and the voltage Vd1+ Vref _ Vs _1 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 1. It should be noted that Vs _1 in the voltage Vd1+ Vref-Vs _1 may be the same.

Thereafter, when the second sub-pixel row is scanned, the DATA signal DATA having the voltage Vd2 is applied to the first terminal 400, and the sub-pixels in the second sub-pixel row are turned on under the control of the gate scan signal G2 transmitted on the gate line G2. And, the 2 nd driving period T _2 is performed while the second sub-pixel row is scanned. In the adjustment phase t1_2, the third switch K3 can be controlled to be turned off because the third control signal CS3 is a high-level signal. Also, since the fourth control signal CS4 is a high level signal, both the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the second control signal CS2 is a low-level signal, the second switch K2 can be controlled to be turned on to provide the adjustment signal Vs having the voltage Vs _2 to the first node N1, so that the voltage of the first node N1 is the voltage Vs _2 of the adjustment signal Vs.

In the reset phase t2_2, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the fourth control signal CS4 is a high level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the third control signal CS3 is a low-level signal, the third switch K3 can be controlled to be turned on to provide the reference signal VREF to the second node N2, so that the voltage of the second node N2 is the voltage VREF of the reference signal VREF. The voltage difference across the capacitor C0 at this time is: Vref-Vs _ 2.

In the boosting period t3_2, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the third control signal CS3 is a high level signal, the third switch K3 may be controlled to be turned off. Since the fourth control signal CS4 is a low-level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned on. The turned-on fourth switch K4 may provide the DATA signal DATA having the voltage Vd2 to a first terminal of the fifth switch S5. Since the voltage of the second node N2 is Vref, that is, the voltage of the control terminal of the fifth switch S5 is Vref, and 0V < Vref < Vd2+ Vth, the fifth switch S5 may be turned on according to the combined action of the voltages of the control terminal and the first terminal thereof. The turned-on fifth switch S5 may provide the DATA signal DATA having the voltage Vd2 input to the first terminal thereof to the first node N1, so that the voltage of the first node N1 jumps from Vs _2 to Vd 2. Due to the bootstrap coupling effect of the capacitor C0, in order to keep the voltage difference across the capacitor C0 at Vref-Vs _2, the voltage of the second node N2 may jump to: vd2+ Vref Vs _ 2. The turned-on sixth switch K6 may provide a voltage Vd2+ Vref-Vs _2 to the data line, so that the data signal with the voltage Vd2+ Vref-Vs _2 is transmitted on the data line, and thus the data signal with the voltage Vd2+ Vref-Vs _2 is input to the second row of sub-pixels as a driving signal, thereby driving the row of sub-pixels to perform light emitting display. As can be seen from the voltage Vd2 applied to the first terminal 400 and the voltage Vd2+ Vref _ Vs _2 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 2. It should be noted that Vs _2 in the voltage Vd2+ Vref-Vs _2 may be the same.

Thereafter, when the third subpixel row is scanned, the DATA signal DATA having the voltage Vd3 is applied to the first terminal 400, and the subpixels in the third subpixel row are turned on under the control of the gate scan signal G3 transmitted on the gate line G3. And, the 3 rd driving period T _3 is performed while the third subpixel row is scanned. In the adjustment phase t1_3, the third switch K3 can be controlled to be turned off because the third control signal CS3 is a high-level signal. Also, since the fourth control signal CS4 is a high level signal, both the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the second control signal CS2 is a low-level signal, the second switch K2 can be controlled to be turned on to provide the adjustment signal Vs with the voltage Vs _3 to the first node N1, so that the voltage of the first node N1 is the voltage Vs _3 of the adjustment signal Vs.

In the reset phase t2_3, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the fourth control signal CS4 is a high level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned off. Since the third control signal CS3 is a low-level signal, the third switch K3 can be controlled to be turned on to provide the reference signal VREF to the second node N2, so that the voltage of the second node N2 is the voltage VREF of the reference signal VREF. The voltage difference across the capacitor C0 at this time is: Vref-Vs _ 3.

In the boosting period t3_3, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the third control signal CS3 is a high level signal, the third switch K3 may be controlled to be turned off. Since the fourth control signal CS4 is a low-level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned on. The turned-on fourth switch K4 may provide the DATA signal DATA having the voltage Vd3 to a first terminal of the fifth switch S5. Since the voltage of the second node N2 is Vref, that is, the voltage of the control terminal of the fifth switch S5 is Vref, and 0V < Vref < Vd3+ Vth, the fifth switch S5 may be turned on according to the combined action of the voltages of the control terminal and the first terminal thereof. The turned-on fifth switch S5 may provide the DATA signal DATA having the voltage Vd3 input to the first terminal thereof to the first node N1 to jump the voltage of the first node N1 from Vs _3 to Vd 3. Due to the bootstrap coupling effect of the capacitor C0, in order to keep the voltage difference across the capacitor C0 at Vref-Vs _3, the voltage of the second node N2 may jump to: vd3+ Vref Vs _ 3. The turned-on sixth switch K6 may provide a voltage Vd3+ Vref-Vs _3 to the data line, so that the data signal with the voltage Vd3+ Vref-Vs _3 is transmitted on the data line, and thus the data signal with the voltage Vd3+ Vref-Vs _3 is input to the second row of sub-pixels as a driving signal, thereby driving the row of sub-pixels to perform light emitting display. As can be seen from the voltage Vd3 applied to the first terminal 400 and the voltage Vd3+ Vref _ Vs _3 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 3. It should be noted that Vs _3 in the voltage Vd3+ Vref-Vs _3 may be the same.

The process of inputting the boosted driving signals to the sub-pixels in the remaining rows may be analogized according to the 1 st to 3 rd driving periods T _1 to T _3, which is not described herein again.

As can be seen from the above operation process, the first driving period T _1 represents an independent driving period, i.e., a single occurrence of the adjusting phase T1_1, the resetting phase T2_1 and the boosting phase T3_1 is taken as the first driving period T _1, and the driving signal is input to the first row of sub-pixels during the boosting phase T3_ 1. The second driving period T _2 represents another independent driving period, i.e., a single occurrence of the adjusting period T1_2, the resetting period T2_2, and the boosting period T3_2 as the second driving period T _2, and the driving signals are input to the subpixels of the second row in the boosting period T3_ 2. The third driving period T _3 represents yet another independent driving period, i.e., a single occurrence of the adjustment phase T1_3, the reset phase T2_3, and the voltage boosting phase T3_3 as the third driving period T _3, and the driving signal is input to the third row subpixel in the voltage boosting phase T3_ 3. The rest can be analogized in turn, and the description is omitted here.

Moreover, when the structure of the display panel is as shown in fig. 1a, the working process of the circuit timing diagram shown in fig. 5 can be analogized according to the above embodiments, and is not described herein again.

With the above embodiment, the voltages VS _1 to VS _3 of the adjustment signal VS are sequentially decreased due to the first to third driving periods T _1 to T _ 3. Therefore, the same boosting control circuit can provide boosting effects of different degrees, so that the boosting control circuit does not need to be independently arranged for each sub-pixel, the process preparation difficulty is reduced, and the pixel aperture opening ratio is improved.

Furthermore, when the signal line is a power signal line (for example, PVEE or PVDD wiring), the same boost control circuit can provide different levels of boost effect, so that it is unnecessary to separately set a boost control circuit for each sub-pixel, thereby reducing the difficulty of process preparation and improving the pixel aperture ratio.

Fig. 4a is a schematic structural diagram of another display panel provided in the embodiment of the present application. Fig. 2 shows a schematic diagram of a boost control circuit, which is a modification of some of the embodiments described above. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

Generally, the data lines are electrically connected with the signal output end of the boost control circuit through the routing of the fan-out area, so that the load of the data lines close to the middle column is smaller than that of the data lines close to the edge columns, thereby causing the signal delay of the data lines close to the middle column to be different from that of the data lines close to the edge columns. In order to improve the phenomenon of different signal delays, the boosting degree required by the sub-pixels of different columns can be different. In practical implementation, in the embodiment of the present invention, the voltage of the adjustment signal corresponding to the sub-pixel close to the middle column in the same row may be greater than the voltage of the adjustment signal corresponding to the sub-pixel closer to the edge column than the middle column. Further, the voltages of the adjustment signals corresponding to the sub-pixels in the direction from the middle column to the edge column in the same row can be sequentially decreased. Wherein the difference can be reduced. Of course, the load difference on the data line may be reduced, and is not limited herein. This makes it possible to make the voltage of the boosted signal transmitted on the data line near the edge column larger than the voltage of the boosted signal transmitted on the data line near the middle column. It should be noted that the sub-pixels of the edge columns may refer to sub-pixels near two ends of the gate line. The sub-pixel of the middle column may refer to a sub-pixel near the middle of the gate line.

The following describes the operation of the display panel provided by the embodiment of the present invention with reference to the structures shown in fig. 2 and fig. 4a and the circuit timing diagram shown in fig. 5. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

During the 1 st driving period T _1, the first sub-pixel row is scanned such that each sub-pixel in the first sub-pixel row is turned on. One multiplexer 500 sequentially inputs data signals to the electrically connected 3 data lines so that the corresponding 3 sub-pixels sequentially input driving signals. In the adjustment phase t1_1, Vs _1 may be changed according to the selective turning-on of the multiplexer 500, so that the voltage Vs _1 of the adjustment signal Vs received by the boost control circuit 200 corresponding to the data line may be sequentially decreased in the direction from the data line of the middle column to the data line of the edge column. In the boosting phase t3_1, the voltage difference Δ V of the signal increase on the data line increases in the direction from the data line of the middle column to the data line of the edge column, which is Vref-Vs _ 1. It should be noted that fig. 5 only shows the change of Vs corresponding to one data line, and the changes of Vs corresponding to other data lines may be analogized, which is not described herein again.

During the 2 nd driving period T _2, the second sub-pixel row is scanned such that each sub-pixel in the second sub-pixel row is turned on. One multiplexer 500 sequentially inputs data signals to the electrically connected 3 data lines so that the corresponding 3 sub-pixels sequentially input driving signals. In the adjustment phase t1_2, Vs _2 may be changed according to the selective turning-on of the multiplexer 500, so that the voltage Vs _2 of the adjustment signal Vs received by the boost control circuit 200 corresponding to the data line may be sequentially decreased in the direction from the data line of the middle column to the data line of the edge column. In the boosting phase t3_2, the voltage difference Δ V of the signal increase on the data line increases in sequence from the data line of the middle column to the data line of the edge column, which is Vref-Vs _ 2.

During the 3 rd driving period T _3, the third sub-pixel row is scanned such that each sub-pixel in the third sub-pixel row is turned on. One multiplexer 500 sequentially inputs data signals to the electrically connected 3 data lines so that the corresponding 3 sub-pixels sequentially input driving signals. In the adjustment phase t1_3, Vs _3 may be changed according to the selective turning-on of the multiplexer 500, so that the voltage Vs _3 of the adjustment signal Vs received by the boost control circuit 200 corresponding to the data line is sequentially decreased in the direction from the data line of the middle column to the data line of the edge column. In the boosting phase t3_3, the voltage difference Δ V of the signal increase on the data line increases in the direction from the data line of the middle column to the data line of the edge column, which is Vref-Vs _ 3.

According to the working process, the same boosting control circuit can provide boosting effects of different degrees to meet different boosting degrees required by sub-pixels in different columns, so that the boosting control circuit does not need to be independently arranged for each sub-pixel, the process preparation difficulty is reduced, and the pixel aperture opening ratio is improved.

Fig. 6a and 6b are schematic views of another display panel provided in the embodiment of the present application. Fig. 2 shows a schematic diagram of a boost control circuit, which is a modification of some of the embodiments described above. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In practical implementation, in the embodiment of the present invention, as shown in fig. 6a and 6b, a column of sub-pixels is divided into first to nth pixel groups 120_ N along a third direction F3, where at least one pixel group includes at least two adjacent sub-pixels; wherein N is not less than 2 and is an integer; n is more than or equal to 1 and less than or equal to N, and N is an integer. Illustratively, when the signal line includes a data line, N may be designed according to the number of sub-pixels in a column in the panel, and is not limited herein. The pixel group may include two sub-pixels, or three sub-pixels, and the number of the sub-pixels in the pixel group may be determined according to the actual application environment, and is not limited herein. For example, each pixel group may include the same number of sub-pixels, which may make the voltage transition of the adjustment signal more uniform.

In practical implementation, as shown in fig. 6a and 6b, in the embodiment of the present invention, the boost control circuit 200 is configured to provide the driving signals to the sub-pixels in the nth pixel group along the third direction F3 in the nth driving period. The voltages of the driving signals provided to different sub-pixels in the same driving period may be the same or different, and the voltages of the driving signals provided to the sub-pixels in different driving periods may be the same or different. Of course, this needs to be determined according to the voltage of the data signal, and is not limited herein.

In practical implementation, in the embodiment of the present invention, as shown in fig. 6a, the third direction F3 may be the same as the first direction F1, and the voltages of the adjustment signal VS received by the boost control circuit 200 are sequentially decreased from the 1 st to the nth driving periods. That is, the voltages VS _1 to VS _ N of the adjustment signal VS in the 1 st to nth driving periods are sequentially decreased. For example, taking N as 3 and each pixel group including two sub-pixels as an example, as shown in fig. 6a and 7, the voltage VS _2 of the adjustment signal VS in the 2 nd driving period T _2 is smaller than the voltage VS _1 of the adjustment signal VS in the 1 st driving period T _1, and the voltage VS _3 of the adjustment signal VS in the 3 rd driving period T _3 is smaller than the voltage VS _2 of the adjustment signal VS in the 2 nd driving period T _ 2. Since the sub-pixels in the first pixel group 120_1 are closest to the signal output terminal OUT, the sub-pixels in the nth pixel group 120_ N are farthest from the signal output terminal OUT, and the second to nth pixel groups 120_2 to 120_ N-1 are sequentially farther from the signal output terminal OUT, the voltages VS _1 to VS _ N of the adjustment signal VS are sequentially decreased, so that the loss of the voltages received by the sub-pixels can be sequentially compensated, and the voltage value input to each sub-pixel is ensured to be an ideal voltage value as much as possible.

Alternatively, in practical implementation, in the embodiment of the present invention, as shown in fig. 6b, the third direction F3 may be opposite to the first direction F1, and the voltages of the adjustment signal VS received by the boost control circuit 200 may be sequentially increased from the 1 st to the nth driving cycles. That is, the voltages VS _1 to VS _ N of the adjustment signal VS in the 1 st to nth driving periods sequentially increase. For example, taking N as 3 and each pixel group including two sub-pixels as an example, as shown in fig. 6b, the voltage VS _2 of the adjustment signal VS in the 2 nd driving period T _2 is greater than the voltage VS _1 of the adjustment signal VS in the 1 st driving period T _1, and the voltage VS _3 of the adjustment signal VS in the 3 rd driving period T _3 is greater than the voltage VS _2 of the adjustment signal VS in the 2 nd driving period T _ 2. Since the sub-pixels in the first pixel group 120_1 are farthest from the signal output terminal OUT, the sub-pixels in the nth pixel group 120_ N are closest to the signal output terminal OUT, and the second to nth pixel groups 120_2 to 120_ N-1 are sequentially closer to the signal output terminal OUT, the loss of the voltage received by each sub-pixel can be sequentially compensated by sequentially increasing the voltages VS _1 to VS _ N of the adjustment signal VS, thereby ensuring that the voltage value input to each sub-pixel is as ideal as possible.

Further, in practical implementation, in the embodiment of the present invention, the voltage of the adjustment signal received by the boost control circuit sequentially changes with equal difference along with the change of the driving period. Wherein, the difference value Δ Vs between the voltages of the adjusting signals of two adjacent driving periods satisfies the formula:

for example, taking N ═ 3 as an example, as shown in fig. 6a and 7, the voltage difference between the voltages Vs _2 and Vs _1 may be substantially equal to the voltage difference between the voltages Vs _3 and Vs _ 2. And the number of the first and second electrodes,

It should be noted that, due to the limitation of the IC that outputs the adjustment signal, the gradient of the change of the voltage Vs of the adjustment signal received by the adjustment module is also in a certain interval, for example, the gradient is 0.1V. As shown in fig. 7, the voltages Vs _1 to Vs _3 of the adjustment signals in the 1 st to 3 rd driving periods T _1 to T _3 can be sequentially lowered by 0.1V. However, in practical applications, the voltage drop difference of the data lines corresponding to the sub-pixels in adjacent rows (for example, two rows and three rows) is not as large as 0.1V, so that the display panel can be combined with the existing driving IC by grouping the sub-pixels in a column to match the boosting effect of the driving signal input by each group of sub-pixels with the voltage drop difference of the data lines corresponding to the sub-pixels, thereby further reducing the cost. The voltages of the adjustment signals corresponding to each group are made the same. Therefore, the change frequency of the adjusting module can be reduced, and the power consumption is reduced.

The operation of the display panel provided by the embodiment of the present invention will be described with reference to the structure shown in fig. 2 and fig. 6a and the circuit timing diagram shown in fig. 7, taking the third direction F3 as the same as the first direction F1, and taking the case that the voltage of the adjustment signal VS received by the boost control circuit 200 is sequentially decreased from the 1 st to the nth driving periods as an example. Taking N as an example, as shown in fig. 7, G1 to G6 represent gate scan signals transmitted through gate lines G1 to G6 electrically connected to the subpixels in the first to sixth rows along the first direction F1. DATA represents a DATA signal transmitted on the first terminal 400. In each of the driving periods T _1 to T _3, the reference signal VREF has a fixed voltage value. The adjusting signal VS in the same driving period is a negative voltage signal with a fixed voltage value, and the voltages VS _1 to VS _3 of the adjusting signal VS are sequentially decreased in the first to third driving periods T _1 to T _ 3.

Sequentially driving first to nth pixel groups 120_1 to 120_ N in a third direction F3 during scanning of one frame of image by the display panel, and performing an nth driving period while driving the nth pixel group; in the nth driving period, each sub-pixel row in the nth pixel group 120_ n is scanned line by line along the third direction F3, and the sub-pixels in each sub-pixel row are input with driving signals.

Specifically, the 1 st driving period T _1 is performed while the first pixel group is scanned. The working processes of the adjusting phase t1_1 and the resetting phase t2_1 may be substantially the same as the working processes of the adjusting phase t1_1 and the resetting phase t2_1 in the above embodiments, and are not described herein again. When the first pixel group is scanned, the DATA signal DATA having the voltage Vd1 is applied to the first terminal 400, and the subpixels in the first subpixel row are turned on under the control of the gate scan signal G1 transmitted on the gate line G1. In the boosting phase t3_1, since the second control signal CS2 is a high-level signal, the second switch K2 can be controlled to be turned off. Since the third control signal CS3 is a high level signal, the third switch K3 may be controlled to be turned off. Since the fourth control signal CS4 is a low-level signal, the fourth switch K4 and the sixth switch K6 may be controlled to be turned on. The turned-on fourth switch K4 may provide the DATA signal DATA having the voltage Vd1 to a first terminal of the fifth switch S5. The fifth switch S5 is made to supply the DATA signal DATA having the voltage Vd1 input to the first terminal thereof to the first node N1, so that the voltage of the first node N1 jumps from Vs _1 to Vd1, and the voltage of the second node N2 may jump to: vd1+ Vref Vs _ 1. The turned-on sixth switch K6 may provide a voltage Vd1+ Vref-Vs _1 to the multiplexer to transfer a data signal having a voltage Vd1+ Vref-Vs _1 to the data line, so that the data signal having a voltage Vd1+ Vref-Vs _1 is input to the first row of sub-pixels as a driving signal to drive the row of sub-pixels for light emitting display. As can be seen from the voltage Vd1 applied to the first terminal 400 and the voltage Vd1+ Vref _ Vs _1 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 1.

Thereafter, the DATA signal DATA having the voltage Vd2 is applied to the first terminal 400, and the subpixels in the second subpixel row are turned on under the control of the gate scan signal G2 transmitted on the gate line G2. This allows the voltage at the second node N2 to jump to: vd2+ Vref Vs _ 1. The turned-on sixth switch K6 may provide a voltage Vd2+ Vref-Vs _1 to the data line, so that the data signal with the voltage Vd2+ Vref-Vs _1 is transmitted on the data line, and thus the data signal with the voltage Vd2+ Vref-Vs _1 is input to the second row of sub-pixels as a driving signal, thereby driving the row of sub-pixels to perform light emitting display. As can be seen from the voltage Vd2 applied to the first terminal 400 and the voltage Vd2+ Vref _ Vs _1 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 1.

When the second pixel group is scanned, the 2 nd driving period T _2 is performed. The working processes of the adjusting phase t1_2 and the resetting phase t2_2 may be substantially the same as the working processes of the adjusting phase t1_2 and the resetting phase t2_2 in the above embodiments, and are not described herein again. When the second pixel group is scanned, the DATA signal DATA having the voltage Vd3 is applied to the first terminal 400, and the subpixels in the third subpixel row are turned on under the control of the gate scan signal G3 transmitted on the gate line G3. During the boost phase t3_2, the voltage of the second node N2 may jump to: vd3+ Vref Vs _ 2. The turned-on sixth switch K6 may provide a voltage Vd3+ Vref-Vs _2 to the data line to transfer a data signal having a voltage Vd3+ Vref-Vs _2 to the data line, so that the data signal having a voltage Vd3+ Vref-Vs _2 is input to the third row of sub-pixels as a driving signal to drive the row of sub-pixels for light emitting display. As can be seen from the voltage Vd3 applied to the first terminal 400 and the voltage Vd3+ Vref _ Vs _2 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 2.

Thereafter, the DATA signal DATA having the voltage Vd4 is applied to the first terminal 400, and the subpixels in the fourth subpixel row are turned on under the control of the gate scan signal G4 transmitted on the gate line G4. This allows the voltage at the second node N2 to jump to: vd4+ Vref Vs _ 2. The turned-on sixth switch K6 may provide a voltage Vd4+ Vref-Vs _2 to the data line to transfer a data signal having a voltage Vd4+ Vref-Vs _2 to the data line, so that the data signal having a voltage Vd4+ Vref-Vs _2 is inputted to the fourth row of sub-pixels as a driving signal to drive the row of sub-pixels for light emitting display. As can be seen from the voltage Vd4 applied to the first terminal 400 and the voltage Vd4+ Vref _ Vs _2 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 2.

When the third pixel group is scanned, a 3 rd driving period T _3 is performed. The working processes of the adjusting phase t1_3 and the resetting phase t2_3 may be substantially the same as the working processes of the adjusting phase t1_3 and the resetting phase t2_3 in the above embodiments, and are not described herein again. And, when scanning the third pixel group, first, the DATA signal DATA having the voltage Vd5 is applied to the first terminal 400, and the subpixels in the fifth subpixel row are turned on under the control of the gate scan signal G5 transmitted on the gate line G5. During the boost phase t3_3, the voltage of the second node N2 may jump to: vd5+ Vref Vs _ 3. The turned-on sixth switch K6 may provide a voltage Vd5+ Vref-Vs _3 to the data line to transfer a data signal having a voltage Vd5+ Vref-Vs _3 to the data line, so that the data signal having a voltage Vd5+ Vref-Vs _3 is inputted to the fifth row of sub-pixels as a driving signal to drive the row of sub-pixels for light emitting display. As can be seen from the voltage Vd5 applied to the first terminal 400 and the voltage Vd5+ Vref _ Vs _3 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 3.

Thereafter, the DATA signal DATA having the voltage Vd6 is applied to the first terminal 400, and the subpixels in the sixth subpixel row are turned on under the control of the gate scan signal G6 transmitted on the gate line G6. This allows the voltage at the second node N2 to jump to: vd6+ Vref Vs _ 3. The turned-on sixth switch K6 may provide a voltage Vd6+ Vref-Vs _3 to the data line, so that the data signal with the voltage Vd6+ Vref-Vs _3 is transmitted on the data line, and thus the data signal with the voltage Vd6+ Vref-Vs _3 is input as a driving signal to the sixth row of sub-pixels, thereby driving the row of sub-pixels to perform light emitting display. As can be seen from the voltage Vd6 applied to the first terminal 400 and the voltage Vd6+ Vref _ Vs _3 input to the data line 300, the voltage difference Δ V can be increased by the action of the boost control circuit to become Vref _ Vs _ 3.

As can be seen from the above operation process, the first driving period T _1 represents an independent driving period, i.e. the adjustment period T1_1, the reset period T2_1 and the boosting period T3_1 occur once as the first driving period T _1, and the driving signal is input to the first row of sub-pixels before the driving signal is input to the second row of sub-pixels during the boosting period T3_ 1. The second driving period T _2 represents another independent driving period, i.e., the adjustment period T1_2, the reset period T2_2, and the boosting period T3_2 occurring once as the second driving period T _2, and the driving signal is input to the third row sub-pixel first and then to the fourth row sub-pixel in the boosting period T3_ 2. The third driving period T _3 represents another independent driving period, i.e., the adjustment period T1_3, the reset period T2_3 and the boosting period T3_3 occurring once are taken as the third driving period T _3, and the driving signal is input to the sub-pixels of the fifth row first and then to the sub-pixels of the sixth row in the boosting period T3_ 3. The rest can be analogized in turn, and the description is omitted here.

In a specific implementation, the voltage of the adjustment signal corresponding to the sub-pixel close to the middle column in the same row may be larger than the voltage of the adjustment signal corresponding to the sub-pixel closer to the edge column. Further, the voltages of the adjustment signals corresponding to the sub-pixels in the direction from the middle column to the edge column in the same row can be sequentially decreased. Wherein the difference can be reduced. Of course, the load difference on the data line may be reduced, and is not limited herein. This makes it possible to make the voltage of the boosted signal transmitted on the data line near the edge column larger than the voltage of the boosted signal transmitted on the data line near the middle column. It should be noted that the sub-pixels of the edge columns may refer to sub-pixels near two ends of the gate line. The sub-pixel of the middle column may refer to a sub-pixel near the middle of the gate line. The above embodiments can be referred to in this embodiment, and are not described herein in detail.

Further, the multiplexer may be made to include a first multiplexer and a second multiplexer. In the row direction along the subpixels, a first multiplexer is near the edge of the display panel (i.e., near the control unit) and a second multiplexer is far from the edge of the display panel (i.e., far from the control unit). In this way, the base voltage or the change gradient or the change range of the adjustment signal VS for the boost control circuit connected to the first multiplexer is smaller than the base voltage or the change gradient or the change range of the adjustment signal VS for the boost control circuit connected to the second multiplexer. The base voltage of the adjustment signal VS may be a maximum value of VS. Of course Vs may vary on the basis of the base voltage depending on the row in which the sub-pixel is driven at that stage.

Fig. 8 is a schematic view of another display panel provided in the embodiment of the present application. It is modified from some of the embodiments described above. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In practical implementation, in the embodiment of the present invention, as shown in fig. 8, the second control signal and the third control signal may be set to be the same signal. This allows the control terminal of the second switch S2 and the control terminal of the third switch S3 to receive the same signal, e.g., both receive the second control signal CS 2. Thus, the control signal output circuit can provide the second control signal CS2 to all the adjusting modules and all the resetting modules respectively by using one signal line, so that the number of signal lines can be reduced, and the occupied space of wiring can be reduced.

Fig. 9 shows a circuit timing chart of the boost control circuit shown in fig. 8. The operation of the adjustment phase and the operation of the reset phase in the driving period T may be performed in the same phase T0. In the period t0, since the fourth control signal CS4 is a high-level signal, the fourth switch K4 and the sixth switch K6 can be controlled to be turned off. Since the second control signal CS2 is a low signal, the second switch K2 can be controlled to be turned on to provide the adjusting signal VS to the first node N1, so that the voltage of the first node N1 is the voltage VS of the adjusting signal VS. Since the second control signal CS2 is a low-level signal, the third switch K3 may be controlled to be turned on to provide the reference signal VREF to the second node N2, so that the voltage of the second node N2 is the voltage VREF of the reference signal VREF. The voltage difference across the capacitor C0 at this time is: Vref-Vs. The operation process of the boosting stage t3 is substantially the same as that of the boosting stage t3 in the above embodiment, and is not described herein again.

It should be noted that, the working process of the display panel in the driving period may refer to the above embodiments, and is not described herein again.

Fig. 10 is a schematic view of another display panel provided in the embodiments of the present application, which is a modification of some embodiments in the embodiments described above. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In general, a display panel (e.g., a display panel of a Micro-LED) requires a higher voltage to be driven in a black state, and may not require a higher voltage to be driven when displaying some pictures (e.g., a highlight picture), so that the display panel may be driven with a lower voltage. Therefore, the main-stream low-cost driving IC can be directly adopted to output voltage to the signal line without a boost control circuit, so that the voltage is transmitted to the sub-pixel through the signal line, the effect of inputting lower voltage to the display panel is realized, and the power consumption is reduced. For example, in a specific implementation, in an embodiment of the present invention, as shown in fig. 10, the display panel may further include: a plurality of first switches K1. One of the boost control circuits 200 corresponds to one of the first switches K1. The control terminal of the first switch K1 is configured to receive the first control signal CS1, the first terminal of the first switch K1 is electrically connected to the signal input terminal IN of the boost control circuit 200, and the second terminal of the first switch K1 is electrically connected to the signal output terminal OUT of the boost control circuit 200. That is, the first switch K1 is actually connected in parallel with the corresponding boost control circuit 200. Further, when the first switch K1 is IN a conductive state under the control of the first control signal CS1, the signal input to the signal input terminal IN of the boost control circuit 200 may be directly supplied to the signal output terminal OUT, so that the signal applied to the first terminal 400 may be directly transmitted to the signal line.

In specific implementation, in order to reduce the manufacturing process, all the switches may be configured as P-type transistors as shown in fig. 10. Further, the P-type transistor is turned off by a high level signal and turned on by a low level signal. It should be understood that, in the embodiments of the present invention, only the case where the switch is a P-type transistor is described as an example, and the design principle of the case where the switch is an N-type transistor is the same as that of the present invention, and the present invention also falls within the protection scope of the present invention.

In practical implementation, in the embodiment of the present invention, taking the first switch K1 as a P-type transistor as an example, in the driving period T in the above embodiment, the first control signal CS1 is always set to a high level signal, so that the first switch K1 is always in an off state, and at this time, the display panel performs the operation process of the driving period T.

In specific implementation, in the embodiment of the present invention, as shown in fig. 10 and fig. 11, the driving method may further include: IN the non-drive period NT, the boost control circuit stops operating, and the first switch K1 supplies the input signal input to the signal input terminal IN to the signal line under the control of the first control signal CS 1.

In specific implementation, in the embodiment of the present invention, when the boosting is not performed, the boosting control circuits may be controlled to stop operating. For example, as shown in fig. 10 and 11, in the non-driving period NT, the second control signal CS2, the third control signal CS3, and the fourth control signal CS4 may be set to be high-level signals all the time, so that the second to sixth switches K2 to K6 are in the off state all the time. And the first control signal CS1 is always set to the low level signal, the first switch K1 is always IN the off state, and the input signal input to the signal input terminal IN of the boost control circuit 200 can be directly supplied to the signal output terminal OUT. Illustratively, as shown in connection with fig. 1a, the signal loaded on the first terminal 400 may be directly output to the data line 300. As shown in fig. 1b, the signal applied to the first terminal 400 can be directly output to the multiplexer 500. As shown in fig. 1c, the signal output from the multiplexer 500 can be directly output to the data line 300.

In practical implementation, in an embodiment of the present invention, when the signal line includes a data line, the driving method may further include the following steps:

receiving a data signal of a picture to be displayed corresponding to a frame to be displayed;

determining whether the picture to be displayed is a highlight picture according to the received data signal;

if not, determining that the frame to be displayed has a driving period;

and if so, determining that the frame to be displayed has a non-driving period.

For example, by determining whether the picture to be displayed is a highlight picture according to the received data signal, when the picture to be displayed is determined to be the highlight picture, it may be determined that the frame to be displayed has a non-driving period, which may cause the display panel to perform the working process of the non-driving period. When the frame to be displayed is determined not to be the highlight frame, the frame to be displayed can be determined to have a driving period, so that the display panel can be enabled to perform the working process of the driving period. Therefore, whether boosting is carried out or not can be selected according to the picture to be displayed by the display panel. It should be noted that, the working process of the display panel in the driving period can refer to the above embodiments, and is not described herein again.

Generally, the gray scale divides the brightness variation between the darkest and brightest into several parts for the convenience of controlling the screen brightness. For example, the displayed image may generally be composed of three colors, red, green, and blue, to form a color image by mixing, wherein each color may exhibit a different brightness level, and the red, green, and blue of different brightness levels may be combined to form different color dots. Gray levels are the gradation levels representing the different brightness from the darkest to the brightest. The more the intermediate levels are, the more exquisite the picture effect can be presented. Currently, a typical display panel may employ a 6-bit (2 to 8 th power of brightness gradation, i.e. having 64 gray scale), a 7-bit (2 to 7 th power of brightness gradation, i.e. having 128 gray scale), a 8-bit (2 to 8 th power of brightness gradation, i.e. having 256 gray scale) panel, a 10-bit (2 to 10 th power of brightness gradation, i.e. having 1024 gray scale) panel, a 12-bit (2 to 12 th power of brightness gradation, i.e. having 4096 gray scale) panel, or a 16-bit (2 to 16 th power of brightness gradation, i.e. having 65536 gray scale) panel to realize image display. In specific implementation, the highlight frame may be a frame corresponding to the highest gray scale. For example, the picture corresponding to 255 gray levels in an 8-bit panel.

Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The principle of the display device to solve the problem is similar to the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated details are not repeated herein.

In specific implementation, in the embodiment of the present invention, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A display panel, comprising: the array substrate comprises a plurality of boosting control circuits positioned in a non-display area of the array substrate and a plurality of signal wires positioned on the array substrate; one of the boosting control circuits corresponds to at least one of the signal lines;

the signal input end of the boost control circuit is used for receiving an input signal, and the boost control circuit is used for boosting the voltage of the received input signal and then providing the boosted voltage to the corresponding signal line through the signal output end of the boost control circuit;

the boost control circuit includes: the device comprises a reset module, an adjusting module and a boosting module;

the adjusting module is used for providing an adjusting signal to the first node under the control of the second control signal;

the reset module is used for providing a reference signal to the second node under the control of a third control signal;

the boost module is used for providing a signal received by the signal input end to the first node under the control of a fourth control signal, and coupling the signal input to the first node to the second node and then outputting the signal through the signal output end;

the display panel comprises a plurality of sub-pixels arranged in an array; the signal line is electrically connected with the plurality of sub-pixels; the boost control circuit is used for receiving an input signal through the signal input end in a driving period, boosting the voltage of the received input signal, and then providing the boosted voltage to the corresponding signal line through the signal output end to enable the sub-pixel to input a driving signal;

the adjusting module is used for providing an adjusting signal to the first node under the control of a second control signal in the adjusting stage;

the reset module is used for providing a reference signal to the second node under the control of a third control signal in the reset stage;

the boosting module is used for providing the input signal received by the signal input end to the first node under the control of a fourth control signal in the boosting stage, coupling the signal input to the first node to the second node, outputting the signal to the signal line through the signal output end, and inputting a driving signal to the sub-pixel.

2. The display panel of claim 1, wherein the non-display region of the array substrate further comprises: a plurality of first terminals; the signal input end of the boost control circuit is electrically connected with the control unit through the first terminal;

the signal input end is electrically connected with the first terminal, and the boosting output end is electrically connected with the signal wire; wherein one of the boost control circuits corresponds to one of the first terminals and one of the signal lines.

3. The display panel of claim 1, wherein the non-display region of the array substrate further comprises: a plurality of first terminals and a plurality of multiplexers;

the signal input end of the boost control circuit is electrically connected with the first terminal, the signal output end of the boost control circuit is electrically connected with the input ends of the multiplexers, and the output end of one multiplexer is correspondingly electrically connected with a plurality of signal wires; one first terminal corresponds to one boosting control circuit and one multiplexer, and a signal input end of the boosting control circuit is electrically connected with the control unit through the first terminal.

4. The display panel of claim 1, wherein the display panel further comprises: a plurality of first terminals and a plurality of multiplexers;

the signal input end of the boost control circuit is electrically connected with the output end of the multiplexer, and the signal output end of the boost control circuit is electrically connected with the signal wire; one first terminal corresponds to one multiplexer, one multiplexer corresponds to a plurality of signal lines, one signal line corresponds to one boosting control circuit, and the input end of the multiplexer is electrically connected with the control unit through the first terminal.

5. The display panel of claim 1, wherein the display panel further comprises: a plurality of first switches;

the control end of the first switch is used for receiving a first control signal, the first end of the first switch is electrically connected with the signal input end of the boost control circuit, and the second end of the first switch is electrically connected with the signal output end of the boost control circuit; wherein one of the boost control circuits corresponds to one of the first switches.

6. The display panel of claim 1, wherein the adjustment module comprises: a second switch; the control end of the second switch is used for receiving the second control signal, the first end of the second switch is used for receiving the adjustment signal, and the second end of the second switch is electrically connected with the first node.

7. The display panel of claim 1, wherein the reset module comprises: a third switch; wherein a control terminal of the third switch is configured to receive the third control signal, a first terminal of the third switch is configured to receive the reference signal, and a second terminal of the third switch is electrically connected to the second node.

8. The display panel of claim 1, wherein the boost module comprises: the fourth switch, the fifth switch, the sixth switch and the coupling capacitor;

the control end of the fourth switch is used for receiving the fourth control signal, the first end of the fourth switch is used as the signal input end, and the second end of the fourth switch is electrically connected with the first end of the fifth switch;

a control end of the fifth switch is electrically connected with the second node, and a second end of the fifth switch is electrically connected with the first node;

the control end of the sixth switch is used for receiving the fourth control signal, the first end of the sixth switch is electrically connected with the second node, and the second end of the sixth switch is used as the signal output end;

the coupling capacitor is electrically connected between the first node and the second node.

9. The display panel according to claim 8, wherein the voltage Vref of the reference signal satisfies a formula: 0V < Vref < Vd + Vth; wherein Vd represents a voltage of the input signal and Vth represents a threshold voltage of the fifth switch.

10. The display panel of claim 1, wherein the second control signal and the third control signal are the same signal.

11. The display panel of claim 1, wherein the non-display region of the array substrate further comprises: a control signal output circuit;

all the adjusting modules are electrically connected with the control signal output circuit and used for receiving the second control signal; all the reset modules are electrically connected with the control signal output circuit and used for receiving the third control signal; and all the boosting modules are electrically connected with the control signal output circuit and used for receiving the fourth control signal.

12. The display panel according to any one of claims 3 or 4, wherein an orthogonal projection of the boost control circuit on the array substrate is located between an orthogonal projection of the first terminal on the array substrate and an orthogonal projection of the multiplexer on the array substrate; alternatively, the first and second electrodes may be,

the orthographic projection of the boosting control circuit on the array substrate is located between the orthographic projection of the multiplexer on the array substrate and the display area.

13. The display panel according to claim 1, wherein the signal line extends to a display area of the array substrate in a first direction; the first direction is a direction from a signal output end of the boost control circuit to the display area;

the boost control circuit is used for enabling different sub-pixels to input driving signals in at least two driving periods; wherein, the voltages of the adjusting signals in the same driving period are the same; and the voltage of the adjusting signal in the driving period corresponding to the sub-pixel close to the signal output end is greater than the voltage of the adjusting signal in the driving period corresponding to the sub-pixel far from the signal output end.

14. The display panel according to claim 13, wherein the signal line is electrically connected to the first to mth sub-pixels arranged in the second direction; wherein M is not less than 2 and M is an integer; m is more than or equal to 1 and less than or equal to M and M is an integer;

in the second direction, the boost control circuit is used for providing an m-th driving signal to the m-th sub-pixel in an m-th driving period;

the second direction is the same as the first direction, and the voltage of the adjusting signal received by the boost control circuit is sequentially reduced from the 1 st to the Mth driving periods;

or, the second direction is opposite to the first direction, and the voltages of the adjustment signals received by the boost control circuit are sequentially increased from 1 st to M-th driving periods.

15. The display panel according to claim 13, wherein a column of sub-pixels is divided into first to nth pixel groups in a third direction, at least one of the pixel groups including at least two adjacent sub-pixels; wherein N is not less than 2 and is an integer; n is more than or equal to 1 and less than or equal to N, and N is an integer;

in the third direction, the boost control circuit is used for providing a driving signal to the sub-pixel in the nth pixel group in the nth driving period;

the third direction is the same as the first direction, and the voltage of the adjusting signal received by the boost control circuit is sequentially reduced from the 1 st to the Nth driving periods;

or, the third direction is opposite to the first direction, and the voltages of the adjustment signals received by the boost control circuit are sequentially increased from the 1 st to the nth driving periods.

16. The display panel according to claim 14 or 15, wherein the voltage of the adjustment signal received by the boost control circuit is sequentially changed in an equal difference with a change in the driving period.

17. The display panel according to any one of claims 13 to 15, wherein the voltages of the adjustment signals corresponding to the sub-pixels in the same row and different columns are the same.

18. A display panel as claimed in any one of claims 13-15 characterized in that the voltage of the adjustment signal for the sub-pixels near the middle column in the same row is larger than the voltage of the adjustment signal for the sub-pixels near the edge column compared to it.

19. A driving method of the display panel according to any one of claims 7 to 15, wherein the display panel includes a plurality of sub-pixels arranged in an array; the signal line is electrically connected with the plurality of sub-pixels; the driving method includes: in a driving period, the boost control circuit receives an input signal through the signal input end, boosts the voltage of the received input signal, and provides the boosted voltage to the corresponding signal line through the signal output end, so that the sub-pixel inputs a driving signal;

in the boosting stage, the boosting module supplies the data signal received by the signal input terminal to the first node under the control of a fourth control signal, couples the data signal input to the first node to the second node, and outputs the data signal to the signal line through the signal output terminal to input a driving signal to the sub-pixel.

20. The driving method according to claim 19, wherein the signal line is electrically connected to the first to mth sub-pixels arranged in the second direction; wherein M is not less than 2 and M is an integer; m is more than or equal to 1 and less than or equal to M and M is an integer;

scanning the first to Mth sub-pixel rows line by line along a second direction; and performing an m-th driving period when scanning the m-th sub-pixel row to input a driving signal to the sub-pixels in the m-th sub-pixel row;

21. The driving method according to claim 19, wherein a column of sub-pixels is divided into first to nth pixel groups in a third direction, each of the pixel groups including at least two adjacent sub-pixels; wherein N is not less than 2 and is an integer; n is more than or equal to 1 and less than or equal to N, and N is an integer;

sequentially driving the first to nth pixel groups along the third direction, and performing an nth driving period while driving the nth pixel group; in the nth driving period, scanning each sub-pixel row in the nth pixel group line by line along the third direction, and enabling the sub-pixels in each sub-pixel row to input driving signals;

22. The driving method according to any one of claims 19 to 21, further comprising: and in a non-driving period, the boosting control circuit stops working, and the first switch supplies the input signal input to the signal input end to the signal line under the control of a first control signal.

23. The driving method according to claim 22, wherein the signal line includes a data line, the driving method further comprising:

if not, determining that the frame to be displayed has a driving period;

and if so, determining that the frame to be displayed has a non-driving period.

24. A display device characterized by comprising the display panel according to any one of claims 1 to 18.