TWI550589B - Driving method of data driver and driving method of display panel - Google Patents

Description

Data drive driving method and display panel driving method

The present invention relates to a data driver applied to a display device for driving a display panel for image display, a driving method of the data driver, and a driving method of the display panel.

Recently, active matrix displays such as liquid crystal display devices and organic light emitting diodes (OLEDs) are widely used in mobile phones (mobile phones, portable phones), notebook PCs, In addition to monitors, the demand for large-screen LCD TVs is also increasing.

Taking a liquid crystal display device as an example, as shown in FIG. 1, the liquid crystal display device 10 has a display panel 100 and a drive circuit 110.

The display panel 100 includes a plurality of scan lines 101 (G1 to Gm) arranged in a first direction (horizontal direction) X and a plurality of data lines arranged in a second direction (vertical direction) Y. 102 (D1-Dn), the scan line 101 is insulated from the data line 102 and forms a pixel matrix Px of a complex matrix arrangement (m×n).

A thin film transistor (TFT) 103, a pixel electrode 104, and a common electrode 105 are provided in each of the pixel units Px. The thin film transistor 103 and the pixel electrode 104 are disposed on An array substrate (not shown) is formed on the glass or semiconductor substrate. The common electrode 105 is disposed on an opposite substrate or a color filter substrate (not shown) opposite to the array substrate, and the liquid crystal layer is interposed between the array substrate and the opposite substrate. The common electrode 105 may also be disposed on the array substrate, and only needs to be insulated from the pixel electrode 104. The pixel electrode 104 and the common electrode 105 constitute a liquid crystal capacitor LC. The liquid crystal capacitor LC is driven by the driving circuit 110 to cause corresponding deflection of the liquid crystal molecules, thereby displaying an image.

Further, the driving circuit 110 includes a power supply circuit 111, a timing controller 112, a scan driver 113, and a data driver 114.

The power supply circuit 111 is for supplying a driving voltage to the timing controller 112, the scan driver 113, the data driver 114, and the display panel 100.

The timing controller 112 is configured to receive the RGB image signal output by the image processing circuit, the system clock signal CLKs, and the synchronization signal S _H/V , and control the operation timing of the scan driver 113 and the data driver 114 according to the signal output control signal. The RGB image signal is also output to the data driver 114.

The scan driver 113 is configured to be electrically connected to the plurality of scan lines 101, and sequentially output corresponding scan signals Sg to the scan lines 101 (G1 G Gm), thereby correspondingly opening the electrical connection with the scan lines 101 (Gj). Thin film transistor 103.

The data driver 114 is configured to be electrically connected to the plurality of data lines 102 for loading the image signal Sg when the scan line 101 (Gj) loads the scan signal Sg and causes the corresponding one of the thin film transistors 103 to be turned on. After processing, the data lines D1-Dn are simultaneously loaded, and a column of pixel electrodes 104 corresponding to the scan line Gj loads the data signal Data. However, when the display panel 100 is driven by the aforementioned driving circuit 110, the display The image displayed on the panel 100 may flicker, and even the display panel 100 may not display an image or may not display the image correctly.

In view of the above, it is necessary to provide a driving method of a data driver that makes the image display better and more stable.

Further, a driving method of a display panel having the above data driver is provided.

A data driver driving method, wherein the data driver is configured to provide a data signal for a plurality of data lines of a display panel, the data driver includes a plurality of data output terminals and a signal output timing control circuit, the plurality of data output terminals and the plurality of data lines One-to-one correspondence, and including a plurality of blocks, each block includes at least one data output end, the driving method includes: providing a frame synchronization signal and a data output synchronization signal to the signal output when displaying the xth frame picture a timing control circuit, the frame synchronization signal has a first potential; the synchronization signal is output according to the data, and the signal output timing control circuit controls the data output end of the same block to simultaneously output the data signal to the corresponding data line, and different blocks The data output end outputs the data signal to the corresponding data line at a delay time according to the first sequence; when the x+1th frame picture is displayed, the frame synchronization signal and a data output synchronization signal are provided to the signal output timing control circuit. The frame synchronization signal has a second potential different from the first potential; Outputting a synchronization signal, the signal output timing control circuit controls the data output end of the same block to simultaneously output the data signal to the corresponding data line, and the data output ends of the different blocks respectively output the data according to the delay time in the second order. Number to the corresponding data line; the first order is different from the second order, x is greater than or equal to 1.

A display panel driving method, the display panel includes a plurality of scan lines, a plurality of data lines vertically intersecting the scan lines, a data driver for providing data signals for the plurality of data lines, and a scan driver for providing scan signals for the plurality of scan lines The complex scan line and the complex data line define a plurality of pixel units, each pixel unit including at least one display element displaying the data signal, the plurality of data lines being divided into a plurality of blocks, each block including at least one piece of data a driving method comprising: providing a frame synchronization signal to the data driver when displaying the xth frame picture, the frame synchronization signal having a first potential, and simultaneously providing a data output synchronization for a scan period of any one of the scan lines Signal to the signal output timing control circuit; output synchronous signal according to the data, the signal output timing control circuit controls the data output end of the same block to simultaneously output the data signal to the corresponding data line, and the data output ends of different blocks follow The first sequence outputs the data signal to the pair with a delay time a data line; when displaying the x+1th frame picture, providing a frame synchronization signal to the data driver, the frame synchronization signal having a second potential different from the first potential, and a scan period corresponding to the arbitrary one of the scan lines Providing a data output synchronization signal to the signal output timing control circuit; outputting a synchronization signal according to the data, the signal output timing control circuit controls the data output end of the same block to simultaneously output the data signal to the corresponding data line, and different areas The data output end of the block outputs the data signal to the corresponding data line according to the delay time in the second order; The first order is different from the second order, and x is greater than or equal to 1.

Compared with the prior art, the data output end of the data driver is divided into multiple blocks, and the time for loading the data signals in any two adjacent frames is different, so that the same block is delayed in different frames to load the data signals at different times. In order to achieve the compensation of loading the data signal time, to prevent the time when the data line corresponding to each block is outputted in each frame of the picture is fixed, so that the time of loading the data signal of one of the blocks is insufficient, and the picture flickers or The image is not displayed correctly.

10, 20‧‧‧ liquid crystal display device

100, 200‧‧‧ display panel

110, 210‧‧‧ drive circuit

X‧‧‧ first direction

101, 201, G1~Gm, Gi‧‧ scan lines

Y‧‧‧second direction

102, 202, D1~Dn‧‧‧ data line

Px‧‧‧ pixel unit

103, 203‧‧‧ film transistor

104, 204‧‧‧ pixel electrodes

105, 205‧‧‧ common electrode

LC‧‧‧Liquid Crystal Capacitor

111, 211‧‧‧ power circuit

112, 212‧‧‧ timing controller

113, 213‧‧‧ scan drive

114, 214‧‧‧ data drive

CLKs‧‧‧ system clock signal

S _H/V ‧‧‧Synchronous signal

Sg‧‧‧ scan signal

Data‧‧‧Information signal to be displayed

Data’‧‧‧Initial Information Signal

STV‧‧‧ scan sync sequence number

STA‧‧‧ data output synchronization signal

STB‧‧‧ frame sync signal

SR‧‧‧ Data Shift Register

DL‧‧‧ data latch

LS‧‧‧potentiometer

DAC‧‧‧Digital/Analog Converter

OP‧‧‧ signal operation amplification follower circuit

SC‧‧‧Switch circuit

TSC‧‧‧ signal output timing control circuit

SW1~SWn‧‧‧Switching elements

PD1~PDn‧‧‧ data output

De1~Dex‧‧‧ delay circuit

Star1~Starx‧‧‧Startup Circuit

SD1‧‧‧First Delay Control Signal

SD2‧‧‧second delay control signal

SD3‧‧‧ third delay control signal

SD4‧‧‧First Delay Control Signal

S101, S103, S105, S107‧‧‧ steps

SS‧‧‧Start signal

1 is a block diagram showing the structure of a liquid crystal display device in the prior art.

2 is a block diagram showing the structure of a liquid crystal display device in a preferred embodiment of the present invention.

3 is a circuit block diagram of the data driver shown in FIG. 2.

4 is a schematic diagram showing the circuit structure of the signal output timing control circuit and the complex switching element in a preferred embodiment as shown in FIG.

FIG. 5 is a timing chart showing the operation of the data driver shown in FIG. 2.

FIG. 6 is a driving flowchart of the display panel and the data driver shown in FIG. 2.

FIG. 7 is a schematic diagram showing the circuit structure of the signal output timing control circuit and the complex switching element in a modified embodiment as shown in FIG. 3.

As for the current active matrix display device, as shown in Fig. 1, in particular, for a large-sized active matrix display device, the cause of occurrence of an abnormality such as flicker during image display has been carefully studied and finally found out. When the data driver 114 loads the data signal Data to all the data lines (D1~Dn), the data signal Data is displayed on the display panel 100. The pixel current generates a peak current (Peak Current) when charging and discharging, and the data driver 114 and the ground end of the display panel 100 each have a parasitic resistance Rp (Parasitic Resistance), whereby the peak current corresponds to the data driver 114. A corresponding peak voltage (Peak Voltage) is generated at the ground terminal, and the peak voltage causes disturbance to the voltage at the ground terminal to generate noise. When the data driver 114 simultaneously loads the data signal Data to all the data lines (D1~Dn), a large noise will be generated on the ground of the data driver 114, and the noise will affect the data signal, thereby causing corresponding The pixel electrode 104 cannot display an image normally and flickers. In addition, the noise may even cause damage to the analog circuit operating in the lower voltage (1.8-3.3 V) in the driving circuit 110, thereby causing the analog circuit to malfunction, so that the liquid crystal display device 10 described in the prior art cannot be used. The phenomenon of displaying images normally.

Please refer to FIG. 2, which is a structural block diagram of a liquid crystal display device 20 according to a preferred embodiment of the present invention. It should be noted that the present embodiment is described by taking the liquid crystal display device 20 as an example. Alternatively, it may be another active matrix display device, such as an OLED display device, and is not limited thereto.

The liquid crystal display device 20 has a display panel 200 and a drive circuit 210.

The display panel 200 includes a plurality of scan lines 201 (G1 Gm) arranged in a first direction X (horizontal direction) and a plurality of data lines arranged in a second direction Y (vertical direction). 202 (D1-Dn), the scan line 201 is insulated from the data line 202 and forms a pixel matrix Px of a complex matrix arrangement (m×n).

A thin film transistor 203 (TFT), a pixel electrode 204, and a common electrode 205 are provided in each of the pixel units Px. The thin film transistor 203 and the pixel electrode 204 are disposed on a glass or a semiconductor substrate to form an array substrate (not shown). The common electrode 205 The liquid crystal layer is interposed between the array substrate and the opposite substrate on a counter substrate or a color filter substrate (not shown) opposite to the array substrate. Of course, the common electrode 205 can be modified. It can be disposed on the array substrate, and only needs to be insulated from the pixel electrode 204. The pixel electrode 204 and the common electrode 205 constitute a liquid crystal capacitor LC. The liquid crystal capacitor LC is driven by the driving circuit 210 to cause corresponding deflection of the liquid crystal molecules, thereby displaying an image.

Further, the driving circuit 210 includes a power supply circuit 211, a timing controller 212, a scan driver 213, and a data driver 214.

The power supply circuit 211 is configured to supply a driving voltage to the timing controller 212, the scan driver 213, the data driver 214, and the display panel 200.

The timing controller 212 is configured to receive an initial data signal Data' (eg, RGB data), a system clock signal CLKs, and a synchronization signal S _H/V output by an image processing circuit (not shown), and output a corresponding scan according to the foregoing signal. The synchronization sequence number STV to the scan driver 213, the data output synchronization signal STA and the frame synchronization signal STB control the synchronization operation timing of the data driver 214, and also outputs the initial data signal Data' to the data driver 214.

The scan driver 213 includes a plurality of scan output terminals Ps, and the plurality of scan output terminals Ps are scan output terminals Ps1 to Psm, respectively, for electrically connecting to the scan lines G1 G Gm in the plurality of scan lines 201, respectively, corresponding to any one of the scans. One of the scan periods Tj of the line Gj outputs a corresponding scan signal Sg to the scan line 201 (G1~Gm), thereby correspondingly opening the thin film transistor 203 electrically connected to the scan line 201 (Gj), wherein j is A positive integer less than m.

The data driver 214 includes a complex data output terminal Pd, and the complex data output terminal Pd package The data output terminals Pd1~Pdn are respectively connected to the plurality of data lines 202 (D1~Dn) for electrical connection. The data driver 214 outputs the synchronization signal STA according to the data. When the scan line signal Sg is loaded for each scan line 201, the data signal Data to be displayed is loaded to the corresponding data line 202, and each frame starts according to the frame synchronization signal STB. Simultaneous display of one frame of image. The data output synchronization signal STA is synchronized with the time when each scan line 201 loads the scan signal Sg.

Please refer to FIG. 3, which is a circuit block diagram of the data driver 214 shown in FIG. 2.

The data driver 214 includes a data processing module 214a, a switch circuit SC, and a signal output timing control circuit TSC. The data processing module 214a is configured to process the initial data signal Data' received from the timing controller 212 to obtain the data signal Data to be displayed. The switch circuit SC is electrically connected to the data processing module 214a and the complex data output terminals Pd1~Pdn, and under the control of the signal output timing control circuit TSC, the data signal Data to be displayed is not simultaneously transmitted to the complex data output. End Pd1~Pdn.

Specifically, the data processing module 214a includes a data shift register (Data Shift Register) SR, a data latch (Data Latch) DL, a potential shifter (Level Shifter) LS, and a digital/analog converter (Data). /Analogy Converter) DAC, signal operation amplification follower circuit OP.

The data shift register SR is used to serially input the initial data signal Data' into the data shift register SR according to the clock signal CLK. After a row of data signals Data is stored, a latch signal STB controls the data latch DL to be turned on, and the data latch DL latches the currently stored data signal Data, and the digital/analog converter DAC Start digital/analog conversion of the data signal Data. Wherein, when the data latch DL completes latching of a column of data signals, the data shift register SR is The data signal Data to be displayed may be received from the timing controller.

Since the digital/analog conversion data signal Data does not have the driving capability, it needs to be amplified and followed by the signal operation amplification follower circuit to drive the large-capacity pixel unit Px. In this embodiment, the signal operation amplification follower circuit OP includes first to n operational amplifiers, and n is a natural number greater than 1, in the present embodiment, n is 1536.

The switch circuit SC includes first to nth switching elements SW1 to SWn, and the n operational amplifiers are connected in a one-to-one correspondence with the n data output terminals Pd1 to Pdn and the data lines D1 to Dn.

The signal output timing control circuit TSC is electrically connected to the switch circuit SC, and is configured to control the switch circuit SC not to be fully turned on at the same time when receiving the signal output synchronization signal STA, so that one of the data signals to be displayed is not completely simultaneously Transfer to the data output terminal Pd1~-Pdn.

Please refer to FIG. 4, which is a schematic diagram of the circuit structure of the signal output timing control circuit TSC and the complex switching elements SW1~SWn in a preferred embodiment as shown in FIG.

The signal output timing control circuit TSC includes four delay circuits De1~De4 and four start circuits Star1~Star4, and the four delay circuits De1~De4 are electrically connected to the four start circuits Star1~Star4, respectively. The complex delay circuits De1 to De4 simultaneously receive the start signal STA, and each delay circuit DE outputs four delay control signals SD having different delay times to the corresponding start circuit Star at intervals of one frame image display.

In this embodiment, the frame synchronization signal has an alternately converted first potential and a second potential, the first potential being different from the second potential, the first potential being a high potential, and the second potential being a low potential. Corresponding to the different potentials of the frame synchronization signal STB, the delay circuit DE Having different delay times, for example, corresponding to the first potential of the frame synchronization signal STB, the delay circuit DE outputs a delay signal having a first delay, corresponding to the second potential of the frame synchronization signal STB, and the delay circuit DE delay output has a second The delayed delay signal, wherein the first potential and the second potential of the frame synchronization signal STB are separated by a time period of one frame of image display. Optionally, when the corresponding frame synchronization signal STB has the second potential, the delay circuit DE can also output the delay signal having the second delay, and when the frame synchronization signal STB has the first potential, the delay circuit DE outputs the first delay. The delay signal is not limited to this. The data output synchronization signal STA is active low, and the delay control signal SD is high.

The four delay circuits De1 to De4 are sequentially defined as a first delay circuit De1, a second delay circuit De2, a third delay circuit De3, and a fourth delay circuit De4 in order of position. Correspondingly, the four start circuits Star1 to Star4 are sequentially defined in the order of position as a first start circuit Star1, a second start circuit Star2, a third start circuit Star3, and a fourth start circuit Star4. The four start circuits Star1~Star4 are electrically connected to the four delay circuits De1~De4, for example, the first delay circuit De1 and the first start circuit Star1, the second delay circuit De2 and the second start circuit Star2, The three delay circuit De3 is electrically connected to the third start circuit Star3, the fourth delay circuit De4 and the fourth start circuit Star4, respectively.

The four start circuits Star1~Star4 are respectively connected to different sets of switching elements SW, and the start circuit Star1~Star4 controls the complex switching element SW to be in an on state according to the received delay control signal SD corresponding to the output complex start signal SS, thereby making the processed After the data signal Data is not output to the data output terminals Pd1~Pdn, the data signal Data will be loaded to the data lines D1~Dn at different times.

In this embodiment, the switching element SW is divided into four groups, wherein the first starting circuit The Star1 is electrically connected to the first group of switching elements SW, such as SW2i+1~SW3i, and the second starting circuit Star2 is electrically connected to the second group of switching elements SW, such as SWi+1~SW2i, and the third starting circuit Star3 and The third group of switching elements SW, such as SW3i+1~SW4i(SWn), are electrically connected, and the fourth starting circuit Star4 is electrically connected to the fourth group of switching elements SW, such as SW1~SWi. Where n = 4i, i is a positive integer greater than one.

Correspondingly, the data line 202 is also divided into four blocks. For example, the data lines D2i+1~D3i electrically connected to the first group of switching elements SW2i+1~SW3i are the first block data lines 202; The data lines Di+1~D2i electrically connected to the group switching elements SWi+1~SW2i are the second block data lines 202; the data lines D3i+1~D4i electrically connected to the third group switching elements SW3i+1~SW4i The third block data line 202; the data lines D1~Di electrically connected to the fourth group of switching elements SW1 SSW are the fourth block data line 202. The number of the data lines 202 and the switching elements SW of each block are equal, and both are i.

Optionally, the number of the plurality of block data lines 202 may also be unequal, for example, the number of the first group of switching elements SW and the first block data line 202 is i-1, and the second group of switching elements SW and the first The number of the block data lines 202 is i+1, and even the number of any one of the switch elements SW and the first block data line 202 may be 1, and is not limited thereto.

More specifically, the first delay circuit De1 is controlled by the high-potential frame synchronization signal STB, and is delayed by the first delay time t1 (see FIG. 5) after receiving the data output synchronization signal STA, and after the delay is completed. The first delay control signal SD1 is output. The first delay circuit De1 is controlled by the low-level frame synchronization signal STB, and is delayed by a fourth delay time t4 (see FIG. 5) after receiving the data output synchronization signal STA, and outputs a fourth delay control after the delay is completed. Signal SD4.

The second delay circuit De2 is controlled by the high-potential frame synchronization signal STB, and starts to delay the second delay time t2 after receiving the data output synchronization signal STA, and is delayed. After the completion of the delay, the second delay control signal SD2 is output. The second delay circuit De2 is controlled by the low-level frame synchronization signal STB, and starts to delay the third delay time t3 after receiving the data output synchronization signal STA, and outputs the third delay control signal SD3 after the delay is completed.

The third delay circuit De3 is controlled by the high-potential frame synchronization signal STB, and starts to delay the third delay time t3 after receiving the data output synchronization signal STA, and outputs the third delay control signal SD3 after the delay is completed. The third delay circuit De3 is controlled by the low-level frame synchronization signal STB, and starts to delay the second delay time t2 after receiving the data output synchronization signal STA, and outputs the second delay control signal SD2 after the delay is completed.

The fourth delay circuit De4 is controlled by the high-potential frame synchronization signal STB, and starts to delay the fourth delay time t4 after receiving the data output synchronization signal STA, and outputs the fourth delay control signal SD4 after the delay is completed. The fourth delay circuit De4 is controlled by the low-level frame synchronization signal STB, and starts to delay the first delay time t1 after receiving the data output synchronization signal STA, and outputs the first delay control signal SD1 after the delay is completed.

The second delay time t2 is greater than the first delay time t1, and the third delay time t3 is greater than the second delay time t2, and the fourth delay time t4 is greater than the third delay time t3. In this embodiment, the first to fourth delay times t1 to t4 are sequentially multiplied. Preferably, the first delay time t1 is 0.5 microseconds (μs).

In other embodiments, the first to fourth delay times t1 to t4 may also increase irregularly. For example, the third delay time t3 is three times the first delay time t1, and the second delay time t2 is the first delay time. Four times, the fourth delay time t4 is twice the first delay time t1, and the first to fourth delay times t1 to t4 are different from each other. Thus, open The off-components SW1~SW4i delay the corresponding delay time after the signal amplification follower circuit OP completes the rotation, and then load the data signal Data to the corresponding data line 202.

In the embodiment, the number of the delay circuit and the start circuit is four. Correspondingly, the data output terminals Pd1~Pdn are also divided into four blocks, and the number of the delay circuit and the start circuit may be two. , three, five, six, etc., not limited to this.

Optionally, the first group of switching elements SW and the corresponding data output terminal PD can also be connected to the second starting circuit Star2, the third starting circuit Star3 or the fourth starting circuit Star4, and output the starting signal SS after different delays. Under control, the corresponding data signal Data is outputted to the corresponding data line 202. Similarly, the switching elements of other groups and the data output terminal PD and the startup circuit Star in the corresponding block may also be adjusted as described above, and are not limited thereto. .

Alternatively, the complex data output terminal PD located in the same block can be connected to the same switching element SW.

Please refer to FIG. 5-6. FIG. 5 is a timing diagram of the operation of the data driver shown in FIG. 3-4, and FIG. 6 is a schematic diagram of the driving process of the data driver. The operation of the data driver 214 will now be described in detail with reference to Figures 3-6. FIG. 5 only outputs a timing chart in which the data lines D1 D Dn load the data signal Data to be displayed when any one of the scan lines Gj loads the scan signal Sg in one scan period Tj. The one scanning period Tj refers to the time when one scanning line Gj is loaded with the scanning signal Sg, and thus, scanning for one frame of image display requires m scanning periods, followed by one frame. As shown, the 1st to mth scan cycle is repeated.

In this embodiment, when the data lines 202 (D1~Dn) corresponding to the four blocks display the xth frame, the resources are loaded in the first, second, third, and fourth first orders, respectively. The data signal Data, and when the x+1th frame is displayed, the data signal Data is loaded in the second order of the fourth, third, second, and first blocks, thereby effectively compensating the data of different blocks. The time difference of the line loading data signal Data prevents the pixel electrode 204 from appearing flicker or error abnormality due to the time difference of the loading of the data signal Data when displaying the picture.

Step S101, when displaying the xth frame picture, providing a frame synchronization signal STB and a data output synchronization signal STA to the signal output timing control circuit TSC. The data output sync signal STA and the frame sync signal STB are output by the timing controller TCON. It can be understood that the data output synchronization signal STA is synchronized with the scanning signal Sg, and the scanning signal Sg is used to turn on the thin film transistor 203 electrically connected to the scanning line Gj. The frame synchronization signal STB has a first potential.

Step S103, according to the data output synchronization signal STA, the signal output timing control circuit TSC controls the data output terminal PD of the same block to simultaneously output the data signal Data to the corresponding data line 202, and the data output terminal PD of different blocks according to the first When the sequence is different, the data signal Data is outputted to the corresponding data line 202.

Specifically, the first delay circuit De1 outputs a first delay control signal SD1 after the first delay time t1 is received at the start time Ts of receiving the data output synchronization signal STA, and the first startup circuit Star1 receives the first delay signal After the delay control signal SD1, the start signal SS is outputted to the corresponding first group of switching elements SW2i+1~SW3i, and the switching elements SW2i+1~SW3i are controlled to be in an on state, whereby the data signal Data is correspondingly loaded to the first Block data output terminals PD2i+1~PD3i and first block data lines D2i+1~D3i.

The second delay circuit De2 outputs a second delay control signal SD2 after the second delay time t2 is received at the start time Ts of receiving the data output synchronization signal STA. After receiving the second delay control signal SD2, the dynamic circuit Star2 outputs the start signal SS to the corresponding second group of switching elements SWi+1~SW2i, and controls the switching elements SWi+1~SW2i to be in an on state. The data signal Data is correspondingly loaded to the second block data output terminals PDi+1~PD2i and the second block data lines Di+1~D2i.

The third delay circuit De3 outputs a third delay control signal SD3 after receiving the third delay time t3 at the start time Ts of the data output synchronization signal STA, and the third start circuit Star3 receives the third delay control. After the signal SD3, the start signal SS is output to the third group of switching elements SW3i+1~SW4i, and the switching elements SW3i+1~SW4i are controlled to be in an on state, whereby the data signal Data is correspondingly loaded to the third block data output. End PD3i+1~PD4i and third block data line D3i+1~D4i.

The fourth delay circuit De4 outputs a fourth delay control signal SD4 after receiving the fourth delay time t4 at the start time Ts of the data output synchronization signal STA, and the fourth startup circuit Star4 receives the fourth delay control. After the signal SD4, the start signal SS is outputted to the first group of switching elements SW1~SWi, and the switching elements SW1~SWi are controlled to be in an on state. Therefore, the data signal Data is correspondingly loaded to the fourth block data output terminal PD1~PDi. And the fourth block data line D1~Di.

At this point, corresponding to the scan line Gj, one of the data signals Data to be displayed is completely loaded to the data lines D1 to Dn. It can be understood that when the scan lines G1 G Gm are sequentially loaded to complete the scan signal Sg, it indicates that the x-th frame display is completed.

Step S105, when displaying the x+1th frame picture, providing the frame synchronization signal STB and the data output synchronization signal STA to the signal output timing control circuit TSC, wherein the frame synchronization signal STB has a second potential, the second potential is different from the first One potential.

Step S107, according to the data output synchronous signal STA, the signal output timing control circuit TSC controls the data output terminal PD of the same block to simultaneously output the data signal Data to the corresponding data line 202, and the data output end PD of different blocks according to the first When the two sequences are different, the data signal Data is outputted to the corresponding data line 202. Wherein, the second order is opposite to the first order.

Specifically, the first delay circuit De1 outputs a fourth delay control signal SD4 after receiving the fourth delay time t4 at the start time Ts of the data output synchronization signal STA, and the first start circuit Star1 receives the first After the four delay control signals SD4, the start signal SS is outputted to the corresponding first group of switching elements SW2i+1~SW3i, and the switching elements SW2i+1~SW3i are controlled to be in an on state, whereby the data signal Data is correspondingly loaded to the first Block data output terminals PD2i+1~PD3i and first block data lines D2i+1~D3i.

The second delay circuit De2 outputs a third delay control signal SD3 after receiving the third delay time t3 at the start time Ts of the data output synchronization signal STA, and the second start circuit Star2 receives the third delay control. After the signal SD3, the start signal SS is outputted to the corresponding second group of switching elements SWi+1~SW2i, and the switching elements SWi+1~SW2i are controlled to be in an on state, whereby the data signal Data is correspondingly loaded into the second block. Data output terminals PDi+1~PD2i and second block data lines Di+1~D2i.

The third delay circuit De3 outputs a second delay control signal SD2 after receiving the second delay time t2 at the start time Ts of the data output synchronization signal STA, and the third start circuit Star3 receives the second delay control. After the signal SD2, the start signal SS is outputted to the third group of switching elements SW3i+1~SW4i, and the switching elements SW3i+1~SW4i are controlled to be in an on state, thereby loading the data signal Data correspondingly. To the third block data output terminal PD3i+1~PD4i and the third block data line D3i+1~D4i.

The fourth delay circuit De4 outputs a first delay control signal SD1 after receiving the first delay time t1 at the start time Ts of the data output synchronization signal STA, and the fourth start circuit Star4 receives the first delay control. After the signal SD1, the start signal SS is outputted to the first group of switching elements SW1~SWi, and the switching elements SW1~SWi are controlled to be in an on state. Therefore, the data signal Data is correspondingly loaded to the fourth block data output terminal PD1~PDi. And the fourth block data line D1~Di.

At this point, corresponding to the scan line Gj, one of the data signals Data to be displayed is completely loaded to the data lines D1 to Dn. It can be understood that when the scan lines G1 G Gm are sequentially loaded to complete the scan signal Sg, the x+1 frame picture display is completed.

It can be understood that, when the x+2th frame is displayed, the data line 202 loads the information number Data in the first order according to the blocks of the data lines D1 to Dn corresponding to the xth frame, and displays the x+3 frame. In the case of the picture, the data line 202 loads the information number Data in the second order in which the data lines D1 to Dn corresponding to the x+1th frame picture are used. The other frame pictures are not repeated here.

Please refer to FIG. 7. FIG. 7 is a circuit diagram of a signal output timing control circuit TSC and a plurality of switching elements SW1 SWSWn according to a modified embodiment of the present invention.

In this embodiment, the signal output timing control circuit TSC has the same structure, and the only difference is the connection mode with the switching elements SW1 SWSWn. In the modified embodiment, each of the plurality of data output terminals PD of each block corresponding to each of the start-up circuits Star is further provided with a data output terminal PD of another block, or a corresponding connection of each start circuit Star Between each of the plurality of data lines 202 of each block A data line 202 with other blocks is provided. The following is an example of the embodiment shown in FIG. 7. As shown in FIG. 7, each group of switching elements SW corresponding to each of the starting circuits Star and the plurality of data output terminals PD of each block are arranged in the following manner. Zone: a pair of adjacent switching elements SW' and a corresponding data output terminal PD, each pair of data output terminals PD after the pair of data output terminals PD together constitute a data output end of the same block, thereby The complex data output terminals PD1-PDn are divided into four blocks.

Specifically, the first group of switching elements connected to the first startup circuit Star1 are SW2k-1, SW2k, SW2k+7, SW2k+8, SW2k+15, SW2k+16, ..., SWn-7, SWn-6, The data output terminal PD of the first block may be PD2k-1, PD2k, PD2k+7, PD2k+8, PD2k+15, PD2k+16, ..., PDn-7, PDn-6, corresponding to the first block. The data lines 202 are D2k-1, D2k, D2k+7, D2k+8, D2k+15, D2k+16, ..., Dn-7, Dn-6. Where k is 1.

The second group of switching elements connected to the second starting circuit Star2 are SW2k+1, SW2k+2, SW2k+9, SW2k+10, SW2k+17, SWk+18, ..., SWn-5, SWn-4, The data output terminal PD of the second block is PD2k+1, PD2k+2, PD2k+9, PD2k+10, PD2k+17, PDk+18, ..., PDn-5, PDn-4; corresponding second region The data lines 202 of the block are D2k+1, D2k+2, D2k+9, D2k+10, D2k+17, Dk+18, ..., Dn-5, Dn-4.

The third group of switching elements connected to the third starting circuit Star3 are SW2k+3, sw2k+4, SW2k+11, SW2k+12, SW2k+19, SWk+20, ..., SWn-3, SWn-2, The data output PD of the three blocks is PD2k+3, PD2k+4, PD2k+11, PD2k+12, PD2k+19, PDk+20, ..., PDn-3, PDn-2, corresponding to the third The data lines of the block are D2k+3, D2k+4, D2k+11, D2k+12, D2k+19, Dk+20, ..., Dn-3, Dn-2.

a fourth group of switching elements SW2k+5, SW2k+6, SW2k+13, SW2k+14, SW2k+21, SWk+22, ..., SWn-1, SWn, fourth block connected to the fourth starting circuit Star4 The data output terminal PD is PD2k+5, PD2k+6, PD2k+13, PD2k+14, PD2k+21, PDk+22, ..., PDn-1, PDn, and the corresponding value of the fourth block data line D2k+ 5. D2k+6, D2k+13, D2k+14, D2k+21, Dk+22, ..., Dn-1, Dn.

The operation of the data output timing control circuit TSC and the data drive 214 of the complex switching elements SW1 SWSW are the same as those of the data drive described in the preferred embodiment, and will not be described in detail in this embodiment.

Alternatively, the number of the delay circuits is five or six, and the number of the starting circuits is five or six. Correspondingly, the data output terminals PD1~PDn and the data lines D1~Dn are divided into five blocks or six. Blocks are not limited to this.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application.

S101, S103, S105, S107‧‧‧ steps

Claims (14)

A data driver driving method, wherein the data driver is configured to provide a data signal for a plurality of data lines of a display panel, wherein the plurality of data lines and the plurality of scanning lines define a plurality of pixel units; the data driver includes a plurality of data output ends and a signal output a timing control circuit, the complex data output end is connected to the plurality of data lines in a one-to-one correspondence, and includes a plurality of blocks, each block includes at least one data output end, and the driving method comprises: providing when displaying the xth frame picture a frame sync signal and a data output sync signal to the signal output timing control circuit, the frame sync signal has a first potential; the sync signal is output according to the data, and the signal output timing control circuit controls the data output end of the same block to simultaneously output The data signal is sent to the corresponding data line, and the data output end of the different blocks outputs the data signal to the corresponding data line at a delay time according to the first sequence; when the x+1th frame is displayed, the frame synchronization is provided. Signal and a data output synchronization signal to the signal output timing control circuit, the frame synchronization signal The number has a second potential different from the first potential; the synchronous signal is output according to the data, and the signal output timing control circuit controls the data output end of the same block to simultaneously output the data signal to the corresponding data line, and the data of different blocks The output end outputs the data signal to the corresponding data line according to the delay time in the second order; the first sequence is different from the second sequence, and x is greater than or equal to 1; when displaying any frame of the frame, the different blocks are The data output end stops outputting the data signal to the corresponding data line at the same time after the scanning period of any one of the scanning lines ends. The driving method of the data driver according to claim 1, wherein the first sequence is opposite to the second sequence, the first potential and the second potential are alternately changed, and the durations of the first potential and the second potential are The time displayed for one frame. The driving method of the data driver according to claim 2, wherein the plurality of data output ends are sequentially defined as the first to nth data output ends according to the positional order thereof, and the first to nth data output ends are divided into mutual ones according to the positional order. The four blocks are different, and the four blocks are the first block data output end, the second block data output end, the third block data output end and the fourth block data output end. The driving method of the data driver according to claim 3, wherein, when displaying the xth frame: after the first delay time is delayed from receiving the data output synchronization signal, the first block data output terminal outputs the The data signal is sent to the corresponding data line; after receiving the data output synchronization signal and delaying the second delay time, the second block data output end outputs the data signal to the corresponding data line; and the data output synchronous signal is received After starting to delay the third delay time, the third block data output end outputs the data signal to the corresponding data line; after receiving the data output synchronization signal, delaying the fourth delay time, the fourth block data output end The data signal is outputted to the corresponding data line, and the first, second, third, and fourth delay times are different from each other. When the x+1th frame is displayed, the delay time after receiving the data output synchronization signal is delayed by the fourth delay time. The first block data output end outputs the data signal to the corresponding data line; the third delay time is delayed after receiving the data output synchronization signal The second block data output end outputs the data signal to the corresponding data line; after receiving the data output synchronization signal and delaying the second delay time, the third block data output end outputs the data signal to the corresponding The data line; after receiving the data output synchronization signal and delaying the first delay time, the fourth block data output end outputs the data signal to the corresponding data line. The driving method of the data driver according to claim 4, wherein the first block data output end is the 2i+1~3i data output end, and the second block data output end is the i+1th~2i data output end. The third block data output end is 3i+1~4i data output end, and the fourth block data output end is the 1~i data output end, i is a positive integer, and n=4i. The driving method of the data driver according to claim 4, wherein the adjacent two data output ends are a pair, and the data output end corresponding to the first block is the kth, k+4, k+8, ......, n/2-3 pairs of data output; the data output corresponding to the second block is k+1, k+5, k+9, ..., n/2-2 for data output; The data output end corresponding to the three blocks is the k+2, k+6, k+10, ..., n/2-1 pair data output end; the data output end corresponding to the fourth block is the k+3 , i+7, i+11, ..., n/2 pairs of data outputs, where k is equal to 1. The method of driving a data driver according to claim 4, wherein the second delay time is twice the first delay time, and the third delay time is three times the first delay time, and the fourth delay time is Four times the delay time. A display panel driving method, the display panel includes a plurality of scan lines, a plurality of data lines vertically intersecting the scan lines, a data driver for providing data signals for the plurality of data lines, and a scan driver for providing scan signals for the plurality of scan lines The complex scan line and the complex data line define a plurality of pixel units, each pixel unit including at least one display element displaying the data signal, the plurality of data lines being divided into a plurality of blocks, each block including at least one piece of data a driving method comprising: providing a frame synchronization signal to the data driver when displaying the xth frame picture, the frame synchronization signal having a first potential, and simultaneously providing a data output synchronization for a scan period of any one of the scan lines Signal to the signal output timing control circuit; output synchronous signal according to the data, the signal output timing control circuit controls the data output end of the same block to simultaneously output the data signal to the corresponding data line, and the data output ends of different blocks follow The first sequence outputs the data signal to the pair with a delay time Information line When displaying the x+1th frame picture, providing a frame synchronization signal to the data driver, the frame synchronization signal has a second potential different from the first potential, and providing a data output for the scan period corresponding to the arbitrary one of the scan lines Synchronizing the signal to the signal output timing control circuit; outputting the synchronization signal according to the data, the signal output timing control circuit controls the data output end of the same block to simultaneously output the data signal to the corresponding data line, and the data output end of the different block And outputting the data signal to the corresponding data line according to the delay time in the second sequence; the first sequence is different from the second sequence, and x is greater than or equal to 1; when displaying any frame of the frame, the data output of the different block is The terminal stops outputting the data signal to the corresponding data line at the same time after the scanning period of any one of the scanning lines ends. The driving method of the display panel according to claim 8, wherein the first sequence is opposite to the second sequence, the first potential and the second potential are alternately changed, and the durations of the first potential and the second potential are The time displayed for one frame. The driving method of the display panel according to claim 9, wherein the plurality of data output ends are sequentially defined as the first to nth data output ends according to the positional order thereof, and the first to nth data output ends are divided into mutual ones according to the positional order. The four blocks are different, and the four blocks are the first block data output end, the second block data output end, the third block data output end and the fourth block data output end. The driving method of the display panel according to claim 10, wherein, when displaying the xth frame: after the first delay time is delayed from receiving the data output synchronization signal, the first block data output terminal outputs the The data signal is sent to the corresponding data line; after receiving the data output synchronization signal and delaying the second delay time, the second block data output end outputs the data signal to the corresponding data line; and the data output synchronous signal is received After the delay of the third delay, the third block The output end of the material outputs the data signal to the corresponding data line; after receiving the data output synchronous signal and delaying the fourth delay time, the fourth block data output end outputs the data signal to the corresponding data line, the first The second, third, and fourth delay times are different from each other. When the x+1th frame is displayed, the first block data output end outputs the data signal after receiving the data output synchronization signal and delaying the fourth delay time. To the corresponding data line; after receiving the data output synchronization signal and delaying the third delay time, the second block data output end outputs the data signal to the corresponding data line; since the receiving of the data output synchronization signal starts to delay After the second delay time, the third block data output end outputs the data signal to the corresponding data line; after receiving the data output synchronization signal and delaying the first delay time, the fourth block data output end outputs the Data signal to the corresponding data line. The driving method of the display panel according to claim 11, wherein the first block data output end is the 2i+1~3i data output end, and the second block data output end is the i+1th~2i data output end. The third block data output end is 3i+1~4i data output end, and the fourth block data output end is the 1~i data output end, i is a positive integer, and n=4i. The driving method of the display panel according to claim 11, wherein the adjacent two data output ends are a pair, and the data output end corresponding to the first block is the kth, k+4, k+8, ......, n/2-3 pairs of data output; the data output corresponding to the second block is k+1, k+5, k+9, ..., n/2-2 for data output; The data output end corresponding to the three blocks is the k+2, k+6, k+10, ..., n/2-1 pair data output end; the data output end corresponding to the fourth block is the k+3 , i+7, i+11, ..., n/2 pairs of data outputs, where k is equal to 1. The driving method of the display panel according to claim 11, wherein the second delay time is twice the first delay time, and the third delay time is three times the first delay time, the fourth delay The time is four times the first delay time.