CN115050703A

CN115050703A - Power device packaging structure and power converter

Info

Publication number: CN115050703A
Application number: CN202210981894.1A
Authority: CN
Inventors: 张弛
Original assignee: HANGZHOU FIRSTACK TECHNOLOGY CO LTD
Current assignee: Hangzhou Feishide Technology Co ltd
Priority date: 2022-08-16
Filing date: 2022-08-16
Publication date: 2022-09-13
Anticipated expiration: 2042-08-16
Also published as: CN115050703B

Abstract

The application discloses a power device packaging structure and a power converter, the power device packaging structure comprises a shell and a packaging structure positioned in the shell, the packaging structure is based on a half-bridge circuit which is the most basic circuit primitive form of power electronic topology, a first chip and a second chip are attached on two sides of a substrate to form a 3D current conversion path of the half-bridge circuit, thereby realizing the current conversion path in the power device packaging structure, greatly reducing the physical size of the current conversion path and reducing parasitic inductance, meanwhile, the current path adopts a laminated mode, magnetic fields generated by reverse current are mutually offset to further reduce the parasitic inductance, and the traditional mode of radiating at the bottom of the chip is changed into the mode of radiating at the top of the chip to improve the radiating performance, namely, the power device packaging structure has small parasitic inductance and simultaneously gives consideration to good radiating performance, the requirement of the chip on the substrate due to heating is greatly reduced, the cost is reduced, and the multi-parallel/modular expansion is facilitated.

Description

Power device packaging structure and power converter

Technical Field

The present disclosure relates to the field of power semiconductor device packaging technologies, and in particular, to a power device packaging structure and a power converter.

Background

A power semiconductor device, which is a power electronic device, is a semiconductor element widely used in power electronic systems for power conversion and control circuits. With the new requirements of power electronic systems on switching frequency and other aspects of power devices, third generation wide bandgap power semiconductor devices (such as SiC power devices) have come into existence, the wide bandgap power devices have excellent switching characteristics, the switching frequency of the wide bandgap power devices often reaches tens of kHz or even hundreds of kHz, when the wide bandgap power devices are applied, the wide bandgap power devices are sensitive to parasitic inductance in circuits, especially parasitic inductance of current commutation paths in the switching process, and the wide bandgap power devices can bear large peak voltage in the switching-off process due to the large parasitic inductance, and the devices can be damaged in severe cases.

Meanwhile, the chip area of the wide bandgap power device is much smaller than that of the conventional silicon device, so that heat generated by the chip is too concentrated in an actual power device packaging structure, and therefore, the spatial size of chip arrangement needs to be increased to meet the requirement of chip heat dissipation, but an electric loop is increased, the physical size of a current conversion path where the power device is located is increased, and parasitic inductance is further increased.

Therefore, it is very necessary to provide a power device package structure to reduce the parasitic inductance of the power device package structure.

Disclosure of Invention

In order to solve the above technical problem, embodiments of the present application provide a power device package structure and a power converter, so as to reduce parasitic inductance of the power device package structure.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

a power device package structure comprising a housing and a package structure located within the housing, the package structure comprising:

a substrate including a plurality of conductive portions insulated from each other, the plurality of conductive portions including a first conductive portion connected to a first side of the substrate, a second conductive portion connected to a second side of the substrate, and a third conductive portion penetrating the substrate, the first conductive portion and the second conductive portion extending in parallel directions, and the first conductive portion and the second conductive portion having opposite current directions;

the first chip and the first metal layer are stacked on the first side of the substrate, the first chip is electrically connected with the first conductive part and the first metal layer respectively, the first metal layer is also electrically connected with the third conductive part, and the surface of the first metal layer, which is far away from the substrate, is exposed outside the shell;

the second chip and the second metal layer are stacked on the second side of the substrate, the second chip is electrically connected with the third conductive part and the second metal layer respectively, the second metal layer is also electrically connected with the second conductive part, and the surface of the second metal layer, which is far away from the substrate, is exposed outside the shell;

the first conductive part, the first chip, the first metal layer, the third conductive part, the second chip, the second metal layer and the second conductive part which are electrically connected in sequence form a commutation path of a half-bridge circuit, and the first conductive part and the second conductive part are led out by direct-current power terminals.

Optionally, the method further includes:

a first interposer located between the first chip and the first metal layer, the first interposer being electrically connected to the first chip and the first metal layer, respectively, through a frit layer;

a second interposer located between the second die and the second metal layer, the second interposer being electrically connected to the second die and the second metal layer, respectively, by a frit layer.

Optionally, the method further includes:

a third metal layer located between the first conductive part and the first chip, the third metal layer being electrically connected to the first conductive part through a solder layer;

a fourth metal layer located between the third conductive portion and the second chip, the fourth metal layer being electrically connected to the third conductive portion through a solder layer.

Optionally, the method further includes:

be located the third conductive part with between the first metal layer, along deviating from fifth metal layer and third intermediary layer that the direction of base plate was arranged in proper order, the fifth metal layer with connect through the welding layer electricity between the third conductive part, the third intermediary layer respectively with the fifth metal layer with the first metal layer passes through the sintering layer electricity and connects.

Optionally, the method further includes:

and the sixth metal layer and the fourth intermediate layer are positioned between the second conductive part and the second metal layer and are sequentially arranged along the direction deviating from the substrate, the sixth metal layer is electrically connected with the second conductive part through a welding layer, and the fourth intermediate layer is respectively electrically connected with the sixth metal layer and the second metal layer through a sintering layer.

Optionally, the method further includes:

the first gate-level driving circuit and the first gate-level terminal are positioned on the first side of the substrate, the first gate-level driving circuit is electrically connected with the first chip through a first binding line, and the first gate-level driving circuit is led out from the first gate-level terminal;

and the second gate driving circuit is electrically connected with the second chip through a second binding line, and the second gate driving circuit is led out from the second gate terminal.

Optionally, the method further includes: a high frequency decoupling capacitance located at the DC power terminal.

Optionally, the plurality of conductive parts further includes a fourth conductive part, and the fourth conductive part is electrically connected to the third conductive part and led out from the ac power terminal.

A power converter, comprising:

the power device package structure comprises a plurality of power device package structures and an external gate driving circuit, wherein each power device package structure is any one of the power device package structures, and the external gate driving circuit sends driving signals to a first chip and a second chip in each power device package structure.

Optionally, the method further includes:

the first radiator is attached to the first metal layer in each power device packaging structure, and the second radiator is attached to the second metal layer in each power device packaging structure.

Compared with the prior art, the technical scheme has the following advantages:

the power device packaging structure provided by the embodiment of the application comprises a shell and a packaging structure positioned in the shell, wherein the packaging structure is based on a half-bridge circuit which is the most basic circuit primitive form of power electronic topology, one power device in the half-bridge circuit, namely a first chip, is arranged on the first side of a substrate through a first conducting part in the substrate, the first chip is electrically connected with a third conducting part penetrating through the substrate through a first metal layer, the other power device in the half-bridge circuit, namely a second chip, is arranged on the second side of the substrate through a third conducting part penetrating through the substrate, the second chip is electrically connected with a second conducting part in the substrate through a second metal layer, and the first conducting part, the first chip, the first metal layer, the third conducting part, the second chip, the second metal layer and the second conducting part which are electrically connected in sequence form a 3D (3D) commutation path of the half-bridge circuit, therefore, a current commutation path is realized in the power device packaging structure, the physical size of the commutation path is greatly reduced, and parasitic inductance is reduced.

In addition, the power device package structure provided in the embodiment of the application changes the traditional way of heat dissipation at the bottom of the chip into the way of heat dissipation at the top of the chip, specifically, a first metal layer at one side of the first chip, which is far away from the substrate, is exposed outside the package housing to dissipate heat generated by the first chip, and a second metal layer at one side of the second chip, which is far away from the substrate, is exposed outside the package housing to dissipate heat generated by the second chip, and the first chip and the second chip are respectively located at two sides of the substrate, so that the first metal layer and the second metal layer respectively dissipate heat from two sides of the substrate, thereby improving heat dissipation performance and greatly reducing the requirements of the chip on the substrate due to heat generation, on one hand, the chip does not need to be dissipated by using a substrate with a larger volume, so that the physical size of the power device package structure can be smaller, and then the physical size of the commutation path can also be smaller, therefore, parasitic inductance is further reduced, and on the other hand, the substrate can be made of conventional PCB materials without adopting high-temperature-resistant PCB materials, so that extra system cost is not required to be increased, and the cost is lower.

Therefore, the power device packaging structure provided by the embodiment of the application not only reduces parasitic inductance, but also improves heat dissipation performance, namely, the chip packaging structure has small parasitic inductance and simultaneously gives consideration to good heat dissipation performance, the requirement of chip heating on a substrate is greatly reduced, and the cost is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional in-line power device package structure;

fig. 2 is a schematic diagram of a conventional chip-type power device package structure;

FIG. 3 is a schematic structural view illustrating a conventional power device package structure mounted on an insulating metal substrate;

FIG. 4 is a schematic diagram of a conventional package structure in which a power device is embedded inside a PCB substrate;

fig. 5 is a schematic cross-sectional view of a power device package structure according to an embodiment of the present application;

fig. 6 is an external view of a power device package structure according to an embodiment of the present disclosure;

fig. 7(a) -7 (b) are schematic chip temperature distributions of a conventional power device package structure and the power device package structure provided by the embodiment of the present application under the same dissipative heat dissipation condition;

fig. 8 is a schematic structural diagram of a power converter according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As mentioned in the background section, it is very necessary to provide a power device package structure to reduce the parasitic inductance of the power device package structure.

The inventor researches and discovers that the packaging structure of the power device at present greatly limits the high-frequency application of the wide-bandgap power device, and in a PCB-level power electronic power converter, the power device is usually packaged in a direct-insert or patch manner to realize different power electronic circuit topologies, wherein, as shown in fig. 1, the pins of the power device are inserted through the mounting holes of the PCB and soldered on the PCB, and as shown in fig. 2, the pins of the power device are soldered on the bonding pads on the surface of the PCB, but such packaging manner has the following disadvantages:

(1) the packaging pins bring more parasitic inductance, which is not favorable for the switching performance of the power device;

(2) the current commutation path required by the power electronic circuit topology needs to be realized by copper paving in a PCB substrate (namely outside a power device), so that on one hand, the commutation path is longer due to the limitation of process rules, and on the other hand, the power device needs to be connected into the commutation path through a lead, the parasitic inductance of a loop can be increased by the lead, so that the parasitic inductance of the commutation loop introduced in the whole is larger, and the switching performance of the power device is not facilitated;

(3) the packaging form has limited heat dissipation capability, which is not beneficial to improving the output power;

(4) such a packaging form is not favorable for module design, and the difficulty of multi-parallel/modular expansion is high.

In order to solve the above problems, the following two solutions have been proposed for wide bandgap power devices for PCB level applications:

the first solution is to use an insulated metal substrate, as shown in fig. 3, compared to the conventional PCB substrate, the bottom layer of the insulated metal substrate 010 uses a thicker metal layer 011, and combines with a material layer 012 with higher thermal conductivity to enhance heat dissipation, and at this time, heat generated by the wide bandgap power device 013 is conducted to the material layer 012 with high thermal conductivity and the bottom thick metal layer 011 through the via holes 014 between layers to dissipate heat. However, although the situation of heat dissipation of the wide bandgap power device is improved in this solution, the package of the wide bandgap power device is still a conventional patch package, and therefore, the power electronic topology implementation manner is the same as the conventional manner, that is, a current commutation path needs to be implemented outside the power device through a multilayer PCB.

The second solution is to embed the wide bandgap power device 020 inside the PCB substrate 021, as shown in fig. 4, through the through hole 022 between the PCB substrate 021 layers, not only the conduction of chip heating can be realized, but also the commutation path of the power electronic topology in the 3D form can be realized, and compared with the conventional direct insertion type or patch type package, the PCB embedded package greatly reduces the parasitic inductance value in the commutation loop. However, in this solution, since the chip of the wide bandgap power device is placed inside the PCB substrate, and the chip operating temperature of the wide bandgap power device is high (up to 175 degC), the heat dissipation of the chip is limited by the multilayer PCB material, and it is known that the heat dissipation performance of the conventional PCB material is not good, so to achieve the same heat dissipation effect, on one hand, the PCB substrate needs to be made large, and on the other hand, the PCB material needs to be made of a material with higher temperature tolerance, which inevitably increases the cost and also brings certain challenges to the reliability of the system.

Therefore, in order to reduce the parasitic inductance of the power device package structure, the problem of heat dissipation of the power device has to be considered, and from the above analysis, neither of the above two solutions can achieve both the reduction of the parasitic inductance of the power device package structure and the improvement of the heat dissipation performance of the power device.

Based on the above research, an embodiment of the present application provides a power device package structure, fig. 5 shows a schematic cross-sectional structure diagram of the power device package structure provided by the embodiment of the present application, and fig. 6 shows an appearance schematic diagram of the power device package structure provided by the embodiment of the present application, and as shown in fig. 5 and fig. 6, the power device package structure includes:

a housing 100 and a package structure 200 located in the housing 100, the package structure 200 comprising:

a substrate 10, the substrate 10 including a plurality of conductive portions insulated from each other, the plurality of conductive portions including a first conductive portion 11 connected to a first side of the substrate, a second conductive portion 12 connected to a second side of the substrate, and a third conductive portion 13 penetrating the substrate, the first conductive portion 11 and the second conductive portion 12 extending in parallel, and the first conductive portion 11 and the second conductive portion 12 having opposite current directions;

a first chip 20 and a first metal layer 21 stacked on the first side of the substrate 10, wherein the first chip 20 is electrically connected to the first conductive part 11 and the first metal layer 21, respectively, the first metal layer 21 is also electrically connected to the third conductive part 13, and the surface of the first metal layer 21 away from the substrate 10 is exposed outside the housing 100;

a second chip 30 and a second metal layer 31 stacked on the second side of the substrate 10, wherein the second chip 30 is electrically connected to the third conductive part 13 and the second metal layer 31, the second metal layer 31 is also electrically connected to the second conductive part 12, and the surface of the second metal layer 31 away from the substrate 10 is exposed outside the housing 100;

as shown by the arrows in fig. 5, the first conductive part 11, the first chip 20, the first metal layer 21, the third conductive part 13, the second chip 30, the second metal layer 31, and the second conductive part 12, which are electrically connected in this order, form a commutation path of a half-bridge circuit, and the first conductive part 11 and the second conductive part 12 are led out from the dc power terminal 40.

It should be noted that, in this embodiment, the substrate 10 may be implemented by using a multilayer PCB, as shown in fig. 5, the substrate 10 may include multiple conductive layers, and the conductive layers are separated by insulating layers, so that different conductive layers may be connected by through holes according to actual needs, thereby forming a first conductive portion 11, a second conductive portion 12, and a third conductive portion 13 that are insulated from each other.

Specifically, as shown in fig. 5, the first conductive part 11 may be composed of a conductive layer near the first side of the substrate 10, and connected to the conductive layer on the first side surface of the substrate through a plurality of through holes so as to be electrically connected to the first chip 20 on the first side of the substrate 10; the second conductive part 12 may be directly composed of a conductive layer on the surface of the second side of the substrate 10 so as to be electrically connected to the second chip 30 on the second side of the substrate 10; the third conductive part 13 may form a conductive part penetrating the substrate 10 by a plurality of conductive layers and a plurality of through holes, wherein the first conductive part 11 and the second conductive part 12 are led out by the dc power terminal 40, and the second conductive part 12 may also be connected to the first side of the substrate 10 by a plurality of through holes penetrating the substrate 10.

While the description in fig. 5 and above is merely illustrative of one type of composition for the first conductive portion, the second conductive portion, and the third conductive portion, respectively, it is to be understood that the first conductive portion, the second conductive portion, and the third conductive portion can each be in a wide variety of compositions, so long as the first conductive portion is electrically connected to the first side of the substrate and the first chip, the second conductive portion is electrically connected to the second side of the substrate and the second chip, and the third conductive portion is electrically connected through the substrate to electrically connect the first side and the second side of the substrate.

The power device package structure provided in the embodiment of the present application is based on a half-bridge circuit, which is the most basic circuit primitive form of power electronic topology, a first chip 20 of the half-bridge circuit is disposed on a first side of a substrate 10 through a first conductive portion 11 of the substrate 10, the first chip 20 is electrically connected to a third conductive portion 13 penetrating through the substrate 10 through a first metal layer 21, a second chip 30 of the half-bridge circuit is disposed on a second side of the substrate 10 through a third conductive portion 13 penetrating through the substrate 10, and the second chip 30 is electrically connected to a second conductive portion 12 of the substrate 10 through a second metal layer 31, so that the first conductive portion 11, the first chip 20, the first metal layer 21, the third conductive portion 13, the second chip 30, the second metal layer 31 and the second conductive portion 12 which are electrically connected in sequence form a 3D commutation path of the half-bridge circuit (as shown by an arrow in fig. 5), therefore, a current commutation path is realized inside the power device packaging structure, the physical size of the commutation path is greatly reduced, and parasitic inductance is reduced, meanwhile, the extending directions of the first conductive part 11 and the second conductive part 12 are parallel, and the current directions are opposite, moreover, the current flows from the first conductive part 11 of the substrate 10 to the first metal layer 21 through the first chip 20, and then from the first metal layer 21 to the third conductive part 13 of the substrate 10, and similarly, the current flows from the third conductive layer 13 of the substrate 10 to the second metal layer 31 through the second chip 30, and then from the second metal layer 31 to the second conductive layer 12 of the substrate 10, and the current directions are also opposite, so that the current paths adopt a lamination mode, and magnetic fields generated by reverse currents are mutually cancelled, and parasitic inductance is further reduced.

Moreover, the power device package structure provided in the embodiment of the present application changes the conventional way of heat dissipation at the bottom of the chip into heat dissipation at the top of the chip, specifically, the first metal layer 21 on the side of the first chip 20 away from the substrate 10 is exposed outside the package housing 100 to dissipate heat generated by the first chip, and the second metal layer 31 on the side of the second chip 30 away from the substrate 10 is exposed outside the package housing 100 to dissipate heat generated by the second chip, and the first chip and the second chip are respectively located on both sides of the substrate, so that the first metal layer and the second metal layer respectively dissipate heat from both sides of the substrate, thereby improving heat dissipation performance and greatly reducing the requirement of the chip on the substrate for heat dissipation, on the one hand, a substrate with a larger volume is not required to dissipate heat of the chip, so that the physical size of the power device package structure can be smaller, the physical size of the commutation path can be smaller, so as to further reduce the parasitic inductance, and on the other hand, the substrate can adopt the conventional PCB material without adopting the high-temperature-resistant PCB material, so that the additional system cost is not required to be increased, and the cost is lower.

The present application does not limit the electrical connection between the first chip 20 and the first metal layer 21, and the following description is made by way of example.

Alternatively, in an embodiment of the present application, the first chip 20 and the first metal layer 21 may be connected by means of conventional bonding wires.

However, considering that the bonding lines are thin, the stray inductance caused by the interconnection of the substrate, the chip and the leads is large, and the parasitic inductance of the commutation loop is increased, therefore, optionally, in another embodiment of the present application, as shown in fig. 5, the power device package structure further includes:

a first interposer 22 located between the first chip 20 and the first metal layer 21, the first interposer 22 being electrically connected to the first chip 20 and the first metal layer 21, respectively, by a frit layer 23.

In the present embodiment, the first chip 20 and the first metal layer 21 are electrically connected through the first interposer 22 and the two sides of the sintering layer 23, compared with the electrical connection through the bonding wire, on the one hand, the bonding wire is very thin, and the first interposer and the two sides of the sintering layer form conductive posts, so that the current path is widened, thickened, and the impedance is reduced, on the other hand, the bonding wire usually adopts aluminum material, and the sintering layer usually uses silver material, i.e. the first interposer and the two sides of the sintering layer have better material property than the bonding wire, therefore, introducing the sintered first interposer 22 between the first chip 20 and the first metal layer 21 can further reduce the parasitic inductance caused by the internal packaging, and at the same time, the contact area of the first interposer 22 and the two sides of the sintering layer 23 is greatly increased compared with the conventional bonding wire, thereby also enhancing the ability of the heat generated by the first chip 20 to diffuse towards the first metal layer 21, i.e. enhancing the ability of the top layer of the first chip 20 to dissipate heat.

Similarly, the electrical connection manner between the second chip 30 and the second metal layer 31 is not limited in the present application, and optionally, in an embodiment of the present application, the second chip 30 and the second metal layer 31 may be connected by a conventional binding wire. However, considering that the thinner binding line may increase the parasitic inductance of the commutation loop, optionally, in another embodiment of the present application, as shown in fig. 5, the power device package structure further includes:

and a second interposer 32 located between the second chip 30 and the second metal layer 31, the second interposer 32 being electrically connected to the second chip 30 and the second metal layer 31, respectively, through the frit layer 23.

In this embodiment, the second interposer 32 and the sintering layers 23 on two sides thereof form conductive pillars, so that on one hand, the current path is widened, thickened and impedance is reduced, and parasitic inductance caused by internal packaging can be further reduced, and on the other hand, the contact area between the second interposer 32 and the conductive pillars formed by the sintering layers 23 on two sides thereof and the second chip 30 is greatly increased, thereby further enhancing the ability of heat generated by the second chip 30 to diffuse to the second metal layer 31, i.e., enhancing the ability of heat dissipation of the top layer of the second chip 30.

The present application is not limited to the electrical connection method between the first chip 20 and the first conductive part 11 of the substrate 10, and the following description will be given in terms of embodiments.

Alternatively, in an embodiment of the present application, the first chip 20 and the first conductive part 11 of the substrate 10 are directly electrically connected, similarly to the chip 020 and the conductive layer of the substrate 021 in fig. 4, through a plurality of through holes 022.

Optionally, in another embodiment of the present application, as shown in fig. 5, the power device package structure further includes:

a third metal layer 24 located between the first conductive part 11 and the first chip 20, the third metal layer 24 being electrically connected to the first conductive part 11 by a solder layer 25.

In the present embodiment, the first conductive part 11 of the substrate 10 and the first chip 20 are electrically connected through the third metal layer 24, which enables the first chip 20 and the first conductive part 11 of the substrate 10 to be better connected, and on the other hand, the third metal layer 24 serves as a buffer layer to connect the first chip 20 and the first conductive layer 11 of the substrate 10, so that the reliability of the first chip 20 during operation is better.

Similarly, the present application does not limit the electrical connection manner between the second chip 30 and the third conductive part 13 of the substrate 10, and optionally, in an embodiment of the present application, the second chip 30 and the third conductive part 13 of the substrate 10 are directly electrically connected, similarly to the chip 020 and the conductive layer in the substrate 021 in fig. 4, which are directly electrically connected through the plurality of through holes 022. Optionally, in another embodiment of the present application, as shown in fig. 5, the power device package structure further includes:

a fourth metal layer 33 located between the third conductive part 13 and the second chip 30, the fourth metal layer 33 and the third conductive part 13 being electrically connected by the solder layer 25.

In the present embodiment, the third conductive portion 13 of the substrate 10 and the second chip 30 are electrically connected through the fourth metal layer 33, so that the second chip 30 and the third conductive portion 13 of the substrate 10 can be better connected, and the fourth metal layer 33 serves as a buffer layer to connect the second chip 30 and the third conductive layer 13 of the substrate, so that the second chip 30 has better reliability in operation.

It should be noted that, the first chip 20 and the first conductive part 11 of the substrate 10, and the second chip 30 and the third conductive part 13 of the substrate 10 are connected by a metal layer (i.e. the third metal layer 24 and the fourth metal layer 33), and compared with the direct electrical connection between the chip 020 and the conductive layer of the substrate 021 through a plurality of through holes 022 in fig. 4, the current path is wider and thicker, the impedance is smaller, and the parasitic inductance caused by the internal package can be further reduced.

Based on the fact that the first chip 20 is electrically connected to the first metal layer 21 through the sintered first interposer 23, and is electrically connected to the first conductive part 11 of the substrate 10 through the third metal layer 24, in view of practical process, optionally, in an embodiment of the present application, as shown in fig. 5, the power device package structure further includes:

and a fifth metal layer 26 and a third intermediate layer 27 which are positioned between the third conductive part 13 and the first metal layer 21 and are sequentially arranged along a direction departing from the substrate 10, wherein the fifth metal layer 26 is electrically connected with the third conductive part 13 through a welding layer 25, and the third intermediate layer 27 is electrically connected with the fifth metal layer 26 and the first metal layer 21 through a sintering layer 23.

As can be seen from the foregoing, in the present embodiment, the third interposer 27 and the sintered layers 23 on both sides thereof form conductive pillars, so that the current path is widened, thickened, and impedance is reduced, thereby further reducing parasitic inductance due to the internal package, and the third interposer 27 is electrically connected to the third conductive portion 13 of the substrate 10 through the fifth metal layer 26, thereby improving reliability of the package structure.

Similarly, on the basis that the second chip 30 is electrically connected to the second metal layer 31 through the sintered second interposer 32, and is electrically connected to the third conductive part 13 of the substrate 10 through the fourth metal layer 33, in view of practical process, optionally, in an embodiment of the present application, as shown in fig. 5, the power device package structure further includes:

and a sixth metal layer 34 and a fourth interposer 35 located between the second conductive part 12 and the second metal layer 31 and sequentially arranged in a direction away from the substrate 10, wherein the sixth metal layer 34 is electrically connected to the second conductive part 12 through a solder layer 25, and the fourth interposer 35 is electrically connected to the sixth metal layer 34 and the second metal layer 31 through a sintering layer 23.

As can be seen from the foregoing, in the present embodiment, the fourth interposer 35 and the sintered layers 23 on both sides thereof form conductive pillars, so that the current path is widened, thickened, and impedance is reduced, thereby further reducing parasitic inductance caused by the internal package, and the fourth interposer 35 is electrically connected to the second conductive portion 12 of the substrate 10 through the sixth metal layer 34, thereby improving reliability of the package structure.

Because the power device packaging structure provided by the embodiments of the present application uses the half-bridge topology as a cell module, and the half-bridge topology is the most basic circuit cell form of the power electronic topology, the driving part can be integrated into the packaging structure to form an intelligent power module, so as to facilitate the expansion of multiple parallel/modular circuits.

Optionally, in an embodiment of the present application, as shown in fig. 5, the power device package structure further includes:

the first gate driving circuit 50 and the first gate terminal 51 are positioned on the first side of the substrate 10, the first gate driving circuit 50 is electrically connected with the first chip 20 through the first binding line 52, and the first gate driving circuit 50 is led out from the first gate terminal 51;

and the second gate driving circuit 60 and the second gate terminal 61 are positioned on the second side of the substrate 10, the second gate driving circuit 60 is electrically connected with the second chip 30 through a second binding line 62, and the second gate driving circuit 60 is led out from the second gate terminal 61.

In this embodiment, the first gate driving circuit 50 for driving the first chip 20 to operate and the second gate driving circuit 60 for driving the second chip 30 to operate are integrated into the package structure, so that the power device package structure provided in this embodiment becomes an intelligent power module to implement convenient multi-parallel/modular system expansion.

It should be noted that, in this embodiment, the gate level of the first chip 20 (which may be a wide bandgap power device) is still led out by using a conventional bonding wire, and then connected to the built-in first gate level driving circuit 50, and led out through the first gate level terminal 51; similarly, the gate level of the second chip 30 (which may be a wide bandgap power device) is also led out by using a conventional binding line, and then connected to the built-in second gate level driving circuit 60, and led out through the second gate level terminal 61. Since the binding line 52 between the first chip 20 and the first gate-level driving circuit 50 and the binding line 62 between the second chip 30 and the second gate-level driving circuit 60 do not participate in the current flowing in the commutation path, the parasitic inductance in the commutation path is not affected even by the conventional binding line connection.

It should be further noted that, as shown in fig. 5, the first gate-level driving circuit 50 and the first binding line 52 are electrically connected to the conductive layer on the first side of the substrate 10, so as to electrically connect the first gate-level driving circuit 50 and the first binding line 52, and further electrically connect the first gate-level driving circuit 50 and the first chip 20; similarly, the second gate driving circuit 60 and the second binding line 62 are electrically connected to the conductive layer on the second side of the substrate 10, so as to electrically connect the second gate driving circuit 60 and the second binding line 62, and further electrically connect the second gate driving circuit 60 and the second chip 30.

Therefore, the power device packaging structure provided by the embodiment of the application not only reduces parasitic inductance and improves heat dissipation capacity, but also overcomes the defects that the traditional power device packaging structure is not beneficial to module design and the difficulty of multi-parallel/modularized expansion is high, so that the module design is easy to realize.

As can be seen from the foregoing, the first conductive layer 11 and the second conductive layer 12 of the substrate 10 are led out through the dc power terminal 40, and in an embodiment of the present application, as shown in fig. 5, the power device package structure further includes: and the high-frequency decoupling capacitor 70, wherein the high-frequency decoupling capacitor 70 is positioned at the direct current power terminal 40, namely at the led-out direct current power terminal 40, and the high-frequency decoupling capacitor 70 is continuously added, so that the parasitic inductance is further reduced.

On the basis of any of the above embodiments, optionally, in an embodiment of the present application, as shown in fig. 5 and fig. 6, the plurality of conductive parts of the substrate further includes a fourth conductive part 14, and the fourth conductive part 14 is electrically connected to the third conductive part 13 and is led out from the ac power terminal 80.

Alternatively, the dc power terminal 40 and the ac power terminal 80 may be led out from two sides of the substrate 10, respectively, which is not limited in this application, as the case may be.

Alternatively, as shown in fig. 5, the fourth conductive part 14 is connected to the ac power terminal 80 through a plurality of through holes by a metal layer in the substrate 10, but the present application is not limited to the specific composition of the fourth conductive part, as long as the fourth conductive part 14 is electrically connected to the third conductive part 13 and is led out from the ac power terminal 80.

In the above embodiments, the first metal layer to the sixth metal layer may be copper metal layers, but other metal layers may be used as appropriate.

It should be noted that, in the above embodiments, the housing is encapsulated by injection molding, so as to achieve better reliability.

Table 1 shows a comparison situation of the parasitic inductance of the power device package structure provided in the embodiment of the present application, and compared with the parasitic inductance of the foregoing scheme using the insulating metal substrate and the scheme using the chip-embedded PCB substrate, as can be seen from table 1, compared with the foregoing scheme using the insulating metal substrate (the parasitic inductance is 12.74 nH) and the scheme using the chip-embedded PCB substrate (the parasitic inductance is 8.89 nH), the parasitic inductance of the power device package structure provided in the embodiment of the present application is only 2.23nH, which is greatly reduced.

Table 1 parasitic inductance comparison between the power device package structure provided in the embodiment of the present application and the scheme using the insulating metal substrate and the scheme using the chip embedded PCB substrate

	Insulated metal substrate	Chip embedded PCB substrate	This application
				Parasitic inductance	12.74nH	8.89nH	2.23nH

Fig. 7(a) -7 (b) respectively show chip temperature distributions of a conventional power device package structure and the power device package structure provided in the embodiment of the present application under the same dissipative heat dissipation condition, and as can be seen from a comparison between fig. 7(a) and 7(b), the chip junction temperature of the conventional power device package structure is up to 141degC, the chip junction temperature of the power device package structure provided in the embodiment of the present application is up to 128degC, and the temperature is reduced by 13 degC.

Since the power device package structure provided by the embodiment of the present application can implement a modular design and is easy to expand, further, the embodiment of the present application also provides a power converter, as shown in fig. 8, the power converter includes:

a plurality of power device packages 300, and an external gate driver circuit 400, wherein each power device package 300 is the power device package provided in any of the above embodiments, and the external gate driver circuit 400 sends driving signals to the first chip and the second chip in each power device package 300.

For example, when the power device package structure 300 includes the first gate-level driving circuit 50 and the second gate-level driving circuit 60, the external gate-level driving circuit 400 transmits a driving signal to the first gate-level driving circuit 50 to enable the first gate-level driving circuit 50 to drive the first chip 20 to operate, and simultaneously the external gate-level driving circuit 400 also transmits a driving signal to the second gate-level driving circuit 60 to enable the second gate-level driving circuit 60 to drive the second chip 30 to operate.

When the power device package structure 300 does not include a gate-level driving circuit therein, the external gate-level driving circuit 400 may also transmit a driving signal to the first chip 20 and the second chip 30 in each power device package structure 300 by means of a wire or the like, so as to drive the first chip and the second chip to operate.

On the basis of the above embodiments, in each power device package structure, no matter the first chip or the second chip, the lower surface of the chip may be connected to the conductive portion of the substrate, the upper surface may be sintered to the interposer by a sintering process, the interposer is further connected to a thick metal layer, and the thick metal layer is exposed outside the package structure to realize heat dissipation on the upper surface of the chip.

Optionally, in an embodiment of the present application, the power converter further includes:

the first heat sink 500 is attached to the first metal layer 21 in each power device package structure 300, and the second heat sink 600 is attached to the second metal layer 31 in each power device package structure 300, so as to further improve the heat dissipation performance.

It should be noted that, in the power converter provided in the embodiment of the present application, although the system expansion of each power device package structure 300 is performed, the parasitic inductance value can still be kept at a low value (< 7 nH).

To sum up, the embodiment of the present application provides a power device package structure and a power converter, the power device package structure includes a housing and a package structure located in the housing, the package structure is based on a half-bridge circuit, which is the most basic circuit primitive form of power electronic topology, and a first chip and a second chip are mounted on two sides of a substrate to form a 3D commutation path of the half-bridge circuit, thereby implementing a current commutation path inside the power device package structure, greatly reducing the physical size of the commutation path, and reducing parasitic inductance, meanwhile, the current path adopts a lamination mode, and utilizes magnetic fields generated by reverse currents to cancel each other out, further reducing parasitic inductance, and the traditional mode of heat dissipation at the bottom of the chip is changed into the mode of heat dissipation at the top of the chip, thereby improving heat dissipation performance, i.e. having good heat dissipation performance while having smaller parasitic inductance, the requirement of the chip on the substrate due to heating is greatly reduced, the cost is reduced, and the multi-parallel/modular expansion is facilitated.

All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.

In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power device package structure, comprising a housing and a package structure located in the housing, the package structure comprising:

2. The power device package structure of claim 1, further comprising:

3. The power device package structure of claim 2, further comprising:

4. The power device package structure of claim 3, further comprising:

and the third intermediate layer is respectively connected with the fifth metal layer and the first metal layer through a sintering layer in an electric connection manner.

5. The power device package structure of claim 4, further comprising:

6. The power device package structure of any one of claims 1-5, further comprising:

7. The power device package structure of any one of claims 1-5, further comprising: a high frequency decoupling capacitance located at the DC power terminal.

8. The power device package structure of any of claims 1-5, wherein the plurality of conductive portions further comprises a fourth conductive portion electrically connected to the third conductive portion and routed from an AC power terminal.

9. A power converter, comprising:

a plurality of power device packages each of which is as claimed in any one of claims 1 to 8, and an external gate driver circuit for sending a driving signal to the first chip and the second chip in each of the power device packages.

10. The power converter of claim 9, further comprising: