CN115020540A - Silicon wafer manufacturing method and silicon wafer - Google Patents
Silicon wafer manufacturing method and silicon wafer Download PDFInfo
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- CN115020540A CN115020540A CN202210601356.5A CN202210601356A CN115020540A CN 115020540 A CN115020540 A CN 115020540A CN 202210601356 A CN202210601356 A CN 202210601356A CN 115020540 A CN115020540 A CN 115020540A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67276—Production flow monitoring, e.g. for increasing throughput
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67282—Marking devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a silicon wafer manufacturing method and a silicon wafer, and the method comprises the steps of providing a crystal bar, and recording crystal pulling manufacturing data of the crystal bar and quality data of the crystal bar; carrying out a slicing procedure on the crystal bar to obtain a first silicon wafer, and recording slice manufacturing data of the slicing procedure; carrying out degumming cleaning procedures on the first silicon wafer to obtain a second silicon wafer, and recording cleaning manufacturing data of the cleaning procedures; carrying out a sorting procedure on the second silicon wafer to obtain a third silicon wafer, and recording sorting data of the sorting procedure; and forming a mark code on the surface of the third silicon wafer to obtain a mark code silicon wafer, wherein the mark code comprises crystal pulling manufacture data of the crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning manufacture data and sorting data. The marking code silicon wafer manufactured by the invention can trace the original data of the crystal bar.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a silicon wafer and a manufacturing method thereof.
Background
At present, photovoltaic modules are vigorously developed in China. Marking is necessary to track the solar cells in the photovoltaic module during and after the manufacturing process, and generally, marking can be used for information tracing in the production process by marking a line formed by connecting laser pits or small pits on the surface of a silicon wafer by laser to form a marking pattern, carrying out independent and unique coding on each silicon wafer, and reading the mark by shooting a marking image and identifying and analyzing the marking information corresponding to each silicon wafer after coding. Therefore, each silicon wafer can be traced in the process of obtaining the cell and the component through the post-treatment of the silicon wafer, and the method has great significance for tracing the informatization of the process of the whole photovoltaic industry chain.
In the related technology, the marking codes on the silicon wafers do not mark the quality of the crystal bars, the packaged silicon wafers are random silicon wafers, the silicon wafers can be in any region and position, the silicon wafer circulation randomness is high, the silicon wafers cannot be accurately traced in the circulation process, and the efficiency improvement of the solar cell cannot be accurately guided.
Therefore, it is desirable to provide a method for manufacturing a silicon wafer and a silicon wafer capable of tracking the information of the ingot.
Disclosure of Invention
In view of this, the invention provides a silicon wafer manufacturing method and a silicon wafer, which can trace the crystal bar information for manufacturing the silicon wafer.
In one aspect, the present invention provides a method for manufacturing a silicon wafer, including:
providing a crystal bar, and recording crystal pulling production data of the crystal bar and quality data of the crystal bar;
carrying out a slicing procedure on the crystal bar to obtain a first silicon wafer, and recording slice manufacturing data of the slicing procedure;
carrying out a degumming cleaning procedure on the first silicon chip to obtain a second silicon chip, and recording cleaning manufacturing data of the cleaning procedure;
carrying out a sorting procedure on the second silicon wafer to obtain a third silicon wafer, and recording sorting data of the sorting procedure;
and forming a mark code on the surface of the third silicon wafer to obtain a mark code silicon wafer, wherein the mark code comprises crystal pulling manufacture data of the crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning manufacture data and sorting data.
Optionally, the degumming and cleaning process is performed on the first silicon wafer to obtain a second silicon wafer, and the recording of the cleaning manufacturing data of the cleaning process includes:
the method comprises the steps that a first silicon wafer is fed into a flower basket, a flower basket identification code is arranged on the flower basket, and data obtained by cleaning the first silicon wafer comprise the flower basket identification code.
Optionally, forming a mark code on the surface of the third silicon wafer to obtain a mark code silicon wafer includes:
and taking a virtual symmetry axis and a virtual diagonal of the third silicon wafer, wherein the virtual symmetry axis divides the silicon wafer into a first half wafer and a second half wafer, a first mark code and a second mark code are formed on the virtual diagonal, the first mark code and the second mark code are in central symmetry, and the first mark code and the second mark code are respectively positioned on the first half wafer and the second half wafer.
Optionally, a first mark point and a second mark point are formed on the surface of the third silicon wafer, the first mark points form the first mark code, the second mark points form the second mark code, the virtual symmetry axis and the virtual diagonal have an intersection point, and the distance from the first mark point to the intersection point is equal to the distance from the second mark point to the intersection point.
Optionally, forming a half-chip identification code on the surface of the third silicon chip, including:
forming said half-chip identification code in said first half-chip, said half-chip identification code being non-coincident with said first indicia code;
or forming the half-piece identification code on the second half-piece, wherein the half-piece identification code is not overlapped with the second mark code.
Optionally, a pattern of one of oblique lines, transverse lines, vertical lines, circles, semi-circles, ellipses, stars, or drops is formed on the surface of the third silicon wafer as the half identification code.
Optionally, the identification code comprises a two-dimensional code or a barcode.
Optionally, the marking code is formed by laser or high energy particle impact.
In another aspect, the invention further provides a silicon wafer, wherein the surface of the silicon wafer comprises mark codes, and the mark codes comprise crystal pulling manufacture data of a crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning manufacture data and sorting data.
Optionally, the silicon wafer includes a virtual symmetry axis and a virtual diagonal line, the virtual symmetry axis divides the silicon wafer into a first half and a second half, the mark codes include a first mark code and a second mark code, the first mark code and the second mark code are located on the virtual diagonal line, the first mark code and the second mark code are centrosymmetric, and the first mark code and the second mark code are located on the first half and the second half, respectively;
the silicon wafer further comprises a half-wafer identification code:
the half-piece identification code is positioned on the first half piece, and the half-piece identification code is not overlapped with the first mark code;
or the half-piece identification code is positioned on the second half piece, and the half-piece identification code is not overlapped with the second mark code.
Compared with the prior art, the silicon wafer and the manufacturing method thereof provided by the invention at least realize the following beneficial effects:
when the silicon wafer is manufactured, firstly, crystal pulling manufacture data of a crystal bar and quality data of the crystal bar are recorded, then, a crystal bar is subjected to a slicing process to obtain a first silicon wafer, slicing manufacture data of the slicing process is recorded, the first silicon wafer is subjected to a degumming cleaning process to obtain a second silicon wafer, cleaning manufacture data of the cleaning process is recorded, the second silicon wafer is subjected to a sorting process to obtain a third silicon wafer, sorting data of the sorting process is recorded, when a mark code is formed on the surface of the third silicon wafer, crystal pulling manufacture data of the crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning data and sorting data can be included, original data of the crystal bar can be traced in the manufactured mark code silicon wafer, length information of the crystal bar is contained in the quality data of the crystal bar, and the position of the crystal bar can be restored after the mark code is decoded.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a flow chart of a method for fabricating a silicon wafer according to the present invention;
FIG. 2 is a schematic plane structure diagram of a mark code silicon chip;
FIG. 3 is a schematic plane structure diagram of another silicon chip with mark codes according to the present invention;
FIG. 4 is a schematic plane structure diagram of another silicon chip with mark codes according to the present invention;
fig. 5 is a schematic plan view of a solar cell according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1, fig. 1 is a flow chart of a method for manufacturing a silicon wafer according to the present invention, and the method for manufacturing a silicon wafer in fig. 1 includes the following steps:
s1: providing a crystal bar, and recording crystal pulling production data and quality data of the crystal bar;
s2: carrying out a slicing procedure on the crystal bar to obtain a first silicon wafer, and recording slice manufacturing data of the slicing procedure;
s3: carrying out a degumming cleaning procedure on the first silicon chip to obtain a second silicon chip, and recording cleaning manufacturing data of the cleaning procedure;
s4: carrying out a sorting procedure on the second silicon wafer to obtain a third silicon wafer, and recording sorting data of the sorting procedure;
s5: and forming a mark code on the surface of the third silicon wafer to obtain a mark code silicon wafer, wherein the mark code comprises crystal pulling manufacture data of the crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning manufacture data and sorting data.
Specifically, the ingot provided in step S1 has crystal pulling data and ingot quality data.
It will be appreciated that the production of ingots generally comprises several major steps: growing a crystal bar, cutting and detecting the crystal bar, and grinding the outer diameter. Wherein the crystal bar growing process also comprises the following steps: 1) putting the blocky high-purity polysilicon into a quartz crucible, and heating to a melting point of more than 1420 ℃ to completely melt the blocky high-purity polysilicon; 2) after the temperature of the silicon melt slurry is stable, slowly inserting the seed crystal into the silicon melt slurry, then slowly lifting the seed crystal upwards to reduce the diameter of the seed crystal to a certain size, maintaining the diameter and lengthening the seed crystal by 100 to 200 millimeters so as to eliminate the difference of the crystal grain arrangement orientation in the seed crystal; 3) after the growth of the neck is finished, slowly reducing the lifting speed and the temperature to gradually increase the diameter of the neck to the required size; 4) continuously adjusting the lifting speed and the melting temperature, and maintaining the fixed diameter of the crystal bar until the length of the crystal bar reaches a preset value; 5) after the length of the crystal bar reaches a preset value, the lifting speed is gradually increased, the melting temperature is increased, and the diameter of the crystal bar is gradually reduced, so that the phenomena of row difference, slippage and the like caused by thermal stress are avoided, and finally the crystal bar is completely separated from the liquid level. Thus obtaining a complete crystal bar. And then cutting and detecting the crystal bar, wherein the step is to remove head and tail parts with smaller diameters from the grown crystal bar, and detect the size to determine the technological parameters of the next processing step. Then, outer diameter grinding is carried out: in the process of growing the crystal bar, the outer diameter and the roundness of the crystal bar have certain deviation, and the outer cylindrical surface of the crystal bar is uneven, so the outer diameter must be trimmed and ground, and the size and shape errors are smaller than the allowable deviation.
The crystal rod manufactured through the above process has crystal pulling data, that is, process parameters including heating temperature, crystal pulling time and the like in the manufacturing process, and quality data of the crystal rod, such as minority carrier lifetime, resistivity, oxygen carbon content, length size, specific position of the silicon rod and the like, can be obtained by detecting the crystal rod after the crystal rod is manufactured.
Generally, an ingot sticking process is performed before a first silicon wafer is cut from an ingot, and the specific operation steps of the ingot sticking process refer to the related art, specifically, glue is firstly mixed, then the ingot is bonded with a plastic plate by using glue, and then solidification is performed, wherein in the ingot sticking process, pulling forming data of the ingot and quality data of the ingot, namely detailed source information of the ingot, need to be recorded, and an ingot code is generated.
The optional crystal bar code can be + 0001-.
Correspondingly, to distinguish the position of the ingot, a combination of the ingot coding and A and a combination of the ingot coding and B can be used for distinguishing, for example, the +0001A-9999A is the upper half of the ingot, and the +0001B-9999B is the lower half of the ingot, which is only schematically illustrated. The method can accurately position the single crystal rod from which each silicon wafer originates and the position of the single crystal rod, and can accurately guide the single crystal pulling end to improve and improve the effect.
In step S2, the ingot after the ingot sticking process is cut, specifically, the ingot is periodically cut by using a diamond wire at a certain speed, and the first silicon wafer is obtained after cutting, and there is also slice formation data during cutting, where the slice formation data needs to be recorded.
In the step S3, after the cutting process is completed, a degumming and cleaning process is required, the degumming and cleaning process includes a degumming process and a cleaning process, and the degumming process can be performed by using processes such as drying, medicament washing, lactic acid degumming and clear water rinsing, the cleaning process includes steps of inserting, drying, medicament washing, flowing water rinsing and drying, a second silicon wafer is obtained after the degumming process and the cleaning process are completed, and the cleaning process can record cleaning data.
The step S4 is to sort the second silicon wafer, and the sorting process includes sorting and feeding, module sorting, gear sorting, sorting and discharging, sorting and packaging, and warehousing, and the process is not limited specifically herein, and the sorting data needs to be recorded in the process.
In the step S5, the mark code is formed on the surface of the third silicon wafer to obtain the final mark code silicon wafer, and the silicon wafer is manufactured, and the mark code includes the crystal pulling data, the quality data of the ingot, the slicing data, the cleaning data and the sorting data in the upper steps S1-S4, so that the manufactured mark code silicon wafer can be traced back to the ingot data.
In summary, when manufacturing silicon wafers, the pull production data of a crystal bar and the quality data of the crystal bar are recorded, then the crystal bar is subjected to a slicing process to obtain a first silicon wafer, the slice production data of the slicing process is recorded, the first silicon wafer is subjected to a degumming cleaning process to obtain a second silicon wafer, the cleaning production data of the cleaning process is recorded, the second silicon wafer is subjected to a sorting process to obtain a third silicon wafer, and the sorting data of the sorting process is recorded.
The silicon wafer tracing method can accurately position the position of the silicon wafer, accurately improve the efficiency and guide the direction of the battery/silicon wafer end and improve the productivity, the silicon wafer is identified and recognized by the method, and the integrated verification of the rear-end battery and the assembly is combined, so that the overall direction of the battery efficiency improvement can be accurately and correspondingly guided, the productivity is improved by 0.5%, and the efficiency is improved by 0.1%.
In some optional embodiments, in step S3, the degumming and cleaning process is performed on the first silicon wafer to obtain a second silicon wafer, and the recording the cleaning manufacturing data of the cleaning process includes:
feeding the first silicon wafer into the flower basket, setting a flower basket identification code on the flower basket, wherein the cleaning and manufacturing data of the first silicon wafer comprises the flower basket identification code.
Specifically, accomplish the first silicon chip that obtains after section and come unstuck to the crystal bar and need go on the washing process that comes unstuck, in order to increase output, first silicon chip is left and right sides material loading simultaneously at the washing end, the order of first silicon chip can be disturbed completely here, so newly-increased basket of flowers identification code is spent in the inserted sheet process of washing end, optionally can carry out digit to the basket of flowers and beat sign indicating number discernment, virtual digit is beaten sign indicating number discernment, two-dimensional code pattern is beaten sign indicating number discernment etc. here does not specifically limit, discernment each material loading basket of flowers, the illustration: the method comprises the steps of using a basket identification code 1, 2, 3, 4, 5, 6, 7, 8 and 9, enabling the number of pieces contained in each basket to be 100, placing degummed first silicon pieces into a material loading support in sequence, enabling the number of the first silicon pieces loaded in each support to be a preset fixed number, optionally selecting integral multiples of 100, cleaning after loading, assuming that the piece loading amount is 800 pieces, enabling the first silicon pieces entering the first basket to be 1-100 pieces, enabling the first silicon pieces entering the second basket to be 101-200 pieces, enabling the first silicon pieces entering the 3 rd basket to be 301-400 pieces, repeating the steps until the first silicon pieces (not more than 5000 pieces) are completely arranged, combining the basket identification code at a sorting end, identifying the basket according to the basket identification code, identifying crystal pulling manufacturing data of a crystal bar of the first silicon pieces entering the basket, cleaning the crystal bar manufacturing data and crystal bar quality data, and making unique data on the surface of each first silicon piece according to the identification code and making unique data on the surface of the basket Therefore, the mark includes the source information of the first silicon wafer, that is, the crystal pulling formation data, the quality data of the ingot, and the slicing formation data, and it is possible to ensure that the ingot information can be traced back even if the order of the first silicon wafer is disturbed during the circulation of the cleaning process.
Optionally, a fragment imaging detection function is arranged after the degumming procedure and before the cleaning procedure, the first silicon wafer is placed in sequence, a fragment detection function is arranged before the loading, optionally, the intervention can be carried out in a manual detection mode, the fragments generated in the degumming and cleaning procedure are recorded in a manual recording mode and correspond to the data of the first silicon wafer, and the data can be stored in a computer; or, using a camera imaging principle to obtain each first silicon wafer image, determining whether there is a crack or a corner defect in the image according to an image processing method, and determining whether there is a crack or a corner defect by using, for example, OpenCV in the related art, the general steps are as follows: the method comprises the steps of graying an image, increasing contrast, detecting a Canny edge and the like, and of course, other methods can be adopted, and are not specifically limited, after the image is judged to have cracks or unfilled corners, the first silicon wafer with the cracks and the unfilled corners is removed, and meanwhile, the data of the first silicon wafer corresponding to fragments are automatically recorded.
The method adds a basket identification mode in the insert-in process of the cleaning process, and sequentially arranges the first silicon wafers in a fixed quantity feeding support arrangement mode. In order to identify the rear-end battery and the rear-end assembly, the preparation parameters of the silicon wafer/battery can be accurately traced through the battery efficiency data, so that the effect improvement direction can be known.
In the correlation technique, the crystal bar can be degummed, cleaned and sorted at random after being sliced, and the tracing of the silicon wafer is disordered, so that the accurate position of the silicon wafer cannot be positioned, and the accurate tracing cannot be carried out. The embodiment utilizes the flower basket for cleaning and arranging the slices to carry out identification and recognition and arranges the first silicon slice into the flower basket after recognition according to the sequence so as to achieve the purposes of slice arranging and tracing in sequence.
In some alternative embodiments, referring to fig. 1 and fig. 2, fig. 2 is a schematic plan view of a silicon chip with a mark code, and the step S5: the process of forming the mark code on the surface of the third silicon wafer 000 to obtain the mark code silicon wafer 100 includes:
taking a virtual symmetry axis 1 and a virtual diagonal 2 of the third silicon wafer 000, the virtual symmetry axis 1 divides the silicon wafer into a first half 3 and a second half 4, and forming a first mark code 10 and a second mark code 20 on the virtual diagonal 2, wherein the first mark code 10 and the second mark code 20 are in central symmetry, and the first mark code 10 and the second mark code 20 are respectively located on the first half 3 and the second half 4.
Specifically, in fig. 2, only the third silicon wafer 000 is illustrated as a square silicon wafer, but of course, the first mark code 10 and the second mark code 20 in fig. 2 are only illustrated schematically and are not specifically limited to actual products.
Alternatively, the first mark code 10 and the second mark code 20 may be two-dimensional code patterns, or may be simple numbers or bar codes, which is not limited herein. Of course, the size of the two-dimensional code pattern or the number can be defined according to the inspection label of the battery. It should be noted that the first mark code 10 and the second mark code 20 are not limited to a single identification pattern, and may be one or a combination of several patterns such as a numerical identification and a letter indication.
It can be understood that the virtual symmetry axis 1 and the virtual diagonal line 2 are not structures actually existing in the mark code silicon wafer, and both the symmetry axis and the diagonal line exist for a square structure, so that the mark code silicon wafer is divided into two equal-sized half pieces, the mark code silicon wafer is cut into two pieces in the subsequent process of manufacturing a battery string, and if only one identification code is arranged on the surface 000 of the third silicon wafer, one half piece cannot trace back to the original information after slicing.
In the present embodiment, the first mark code 10 and the second mark code 20 are formed on the virtual diagonal line 2, the first mark code 10 and the second mark code 20 are formed in central symmetry, and the first mark code 10 and the second mark code 20 are respectively positioned on the first half-piece 3 and the second half-piece 4, on one hand, the mark codes can be ensured to be arranged on the first half-piece 3 and the second half-piece 4 after slicing, and the first mark code 10 is arranged on the first half-piece 3 and the second mark code 20 is arranged on the second half-piece 4, and in order to ensure that the first half 3 and the second half 4 are convenient to recognize the first code 10 and the second code 20 after the battery string is assembled, therefore, the first mark code 10 and the second mark code 20 are in central symmetry, that is, the first half-piece 3 can be superposed with the second half-piece 4 by rotating 180 degrees anticlockwise, and the positions of the first mark code 10 and the second mark code 20 are at the same position, so that two identification devices are not needed to be arranged during subsequent identification. And of course, more aesthetically pleasing.
In some alternative embodiments, with continuing reference to fig. 1 and 2, the step S5 further includes: the first mark point 101 and the second mark point 201 are formed on the surface of the third silicon wafer 000, the plurality of first mark points 101 form the first mark code 10, the plurality of second mark points 201 form the second mark code 20, the virtual symmetry axis 1 and the virtual diagonal line 2 have an intersection point O, and the distance from the first mark point 101 to the intersection point O is equal to the distance from the second mark point 201 to the intersection point O.
Specifically, fig. 2 shows a case where a plurality of first mark points 101 and second mark points 201 are formed on the surface of the third silicon wafer 000, but the first mark points 101 and the second mark points 201 may be pits or bumps, and the first mark code 10 and the second mark code 20 are formed by the bumps or the pits, as is known from the above embodiments, the first mark code 10 and the second mark code 20 can be traced back to the crystal pulling formation data, the crystal quality data, the slicing formation data, the cleaning data, and the sorting data of the crystal bar. Of course, the manufacturing method in this embodiment may also have the features of any of the above embodiments, and will not be described herein again.
In fig. 2, the distance from the first mark point 101 to the intersection point O is equal to the distance from the second mark point 201 to the intersection point O, so that after the marking code silicon wafer is subjected to binary slicing, the first half piece 3 can be coincided with the second half piece 4 by rotating 180 degrees anticlockwise, and the positions of the first mark code 10 and the second mark code 20 are at the same position, so that two pieces of identification equipment are not required to be arranged during subsequent identification.
Of course, the first mark code 10 and the second mark code 20 in this embodiment are still located on the first half 3 and the second half 4, respectively, so that after the mark code silicon wafer is divided into two pieces, each half has the first mark code 10 and the second mark code 20.
In some alternative embodiments, referring to fig. 3 and fig. 4, fig. 3 is a schematic plane structure diagram of another silicon slice with a mark code provided by the present invention, and fig. 4 is a schematic plane structure diagram of another silicon slice with a mark code provided by the present invention.
Step S5 of the method for manufacturing a silicon wafer of the present invention further includes forming a half-chip identification code 30 on the surface of the third silicon wafer 000, including:
forming a half-piece identification code 30 on the first half-piece 3, wherein the half-piece identification code 30 is not overlapped with the first mark code 10;
or a half-chip identification code 30 is formed on the second half-chip 4, the half-chip identification code 30 not being coincident with the second mark code 20.
With reference to fig. 3, a half-chip identification code 30 is formed on the first half-chip 3 on the surface 000 of the third silicon chip in fig. 3, and the half-chip identification code 30 is only used for marking the first half-chip 3, so that it can be clearly determined whether the first half-chip 3 or the second half-chip 4 is used in the subsequent process of manufacturing the battery string, that is, the first half-chip 3 is used when the half-chip identification code 30 is present, and the second half-chip 4 is used when the half-chip identification code 30 is absent, which is beneficial for tracing the half-chip battery.
With reference to fig. 4, a half-chip identification code 30 is formed on the second half-chip 4 on the surface 000 of the third silicon chip in fig. 4, and the half-chip identification code 30 is only used for marking the second half-chip 4, so that it can be clearly determined whether the first half-chip 3 or the second half-chip 4 is used in the subsequent process of manufacturing the battery string, that is, the second half-chip 4 is used when the half-chip identification code 30 is present, and the first half-chip 3 is used when the half-chip identification code 30 is absent, which is beneficial for tracing the half-chip battery.
In addition, the half-chip identification code 30 is formed on the first half-chip 3, and the half-chip identification code 30 is not overlapped with the first mark code 10, so that the half-chip identification code 30 can not shield the first mark code 10, and the decoding rate can not be influenced. Alternatively, the half-chip identification code 30 is formed on the second half-chip 4, and the half-chip identification code 30 is not overlapped with the second mark code 20, so as not to affect the decoding rate.
Optionally, the first half-piece 3 and the second half-piece 4 both have the half-piece identification code 30 thereon, but in order to distinguish the first half-piece 3 from the second half-piece 4, the half-piece identification code 30 in the first half-piece 3 may be distinguished from the half-piece identification code 30 in the fourth half-piece 4 by different shape arrangements.
Alternatively, with continued reference to fig. 3 and 4, a pattern of one of oblique lines, transverse lines, vertical lines, circles, semicircles, ellipses, stars, or drops is formed on the surface of the third silicon wafer 000 as the half-chip identification code 30.
In fig. 3 and 4, oblique lines are formed only on the surface of the third silicon wafer 000 to distinguish the first half wafer 3 from the second half wafer 4, so as to ensure the tracing of the subsequent half cell. Of course, the first half piece 3 or the second half piece 4 may be a combination of two or more patterns selected from a horizontal line, a vertical line, a circle, a semicircle, an ellipse, a star, and a drop shape, or may be a combination of two or more patterns selected from a diagonal line, a horizontal line, a vertical line, a circle, a semicircle, an ellipse, a star, and a drop shape.
By arranging the half-piece mark code 30, whether the first half-piece 3 or the second half-piece 4 is determined clearly in the subsequent process of manufacturing the battery string, so that the half-piece battery can be traced.
In some alternative embodiments, the marking code is formed by a laser or high energy particle impact.
Alternatively, the pits or bumps formed by laser or high energy particle impact or chemical etching may be a plurality of pits or bumps that constitute the mark code, such as the first mark code 10 and the second mark code 20 in the above embodiment.
The method for forming the mark code may be laser irradiation, or high-energy particle impact, or chemical etching, and the method for forming the mark code is not specifically limited herein. For example only, the mark code is a pit formed by laser irradiation.
Based on the same inventive concept, the present invention further provides a silicon chip 1000, and with reference to fig. 2 to fig. 4, the silicon chip 1000 of this embodiment is the mark code silicon chip 100 in fig. 2 to fig. 4, which is not described in detail below. According to the silicon wafer 1000 provided by the invention, the surface of the silicon wafer 1000 comprises the mark codes, and the mark codes comprise crystal pulling manufacture data of a crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning manufacture data and sorting data.
The silicon wafer 1000 provided by the invention can comprise crystal pulling production data, quality data of the crystal bar, slicing production data, cleaning data and sorting data of the crystal bar, so that the original data of the crystal bar can be traced back, the length information of the crystal bar is contained in the quality data of the crystal bar, and the position of the crystal bar can be restored after the mark code is decoded.
In some alternative embodiments, with continued reference to fig. 2 to 4, the silicon wafer 1000 includes a virtual symmetry axis 1 and a virtual diagonal 2, the virtual symmetry axis 1 divides the silicon wafer 1000 into a first half 3 and a second half 4, the mark codes include a first mark code 10 and a second mark code 20, the first mark code 10 and the second mark code 20 are located on the virtual diagonal 2, the first mark code 10 and the second mark code 20 are in central symmetry, and the first mark code 10 and the second mark code 20 are located on the first half 3 and the second half 4, respectively;
the silicon wafer 1000 further includes a half-chip identification code 30:
the half piece identification code 30 is positioned on the first half piece 3, and the half piece identification code 30 is not overlapped with the first mark code 10;
alternatively, the half-chip identification code 30 is located on the second half-chip 4, and the half-chip identification code 30 is not coincident with the second mark code 20.
Specifically, a first mark code 10 and a second mark code 20 are formed on the virtual diagonal line 2, the first mark code 10 and the second mark code 20 are formed in central symmetry, and the first mark code 10 and the second mark code 20 are respectively positioned on the first half-piece 3 and the second half-piece 4, on one hand, the mark codes can be ensured to be arranged on the first half-piece 3 and the second half-piece 4 after slicing, and the first mark code 10 is arranged on the first half-piece 3 and the second mark code 20 is arranged on the second half-piece 4, and in order to ensure that the first half 3 and the second half 4 are convenient to recognize the first code 10 and the second code 20 after the battery string is assembled, therefore, the first mark code 10 and the second mark code 20 are in central symmetry, the first half piece 3 can be coincided with the second half piece 4 by rotating 180 degrees anticlockwise, and the positions of the first mark code 10 and the second mark code 20 are at the same position, so that two identification devices are not needed to be arranged during subsequent identification. Specifically, the distance from the first mark point 101 to the intersection point O in fig. 2 is equal to the distance from the second mark point 201 to the intersection point O, so that after the mark code silicon wafer 100/1000 is divided into two pieces, the first half piece 3 rotates 180 degrees counterclockwise and can be overlapped with the second half piece 4, the positions of the first mark code 10 and the second mark code 20 are in the same position, and thus, two pieces of identification equipment are not required to be arranged during subsequent identification.
Optionally, in fig. 3, the first half-piece 3 has a half-piece identification code 30, and the half-piece identification code 30 only records the first half-piece 3 in a marking manner, so that it can be clearly determined whether the first half-piece 3 or the second half-piece 4 is used in a subsequent battery string manufacturing process, that is, the first half-piece 3 is used as the half-piece identification code 30, and the second half-piece 4 is used as the half-piece identification code 30, which is beneficial for tracing the half-piece battery. In fig. 4, the second half piece 4 has the half piece identification code 30, and the half piece identification code 30 is only used for marking the second half piece 4, so that the first half piece 3 or the second half piece 4 can be clearly determined in the subsequent process of manufacturing the battery string, that is, the second half piece 4 is used for the half piece identification code 30, and the first half piece 3 is used for the half piece identification code 30, so that the half piece battery can be traced.
When the half-chip identification code 30 is located in the first half-chip 3, the half-chip identification code 30 is not overlapped with the first mark code 10, so that the half-chip identification code 30 can not shield the first mark code 10, and the decoding rate can not be influenced. Alternatively, when the half-chip identification code 30 is located on the second half-chip 4, the half-chip identification code 30 is not overlapped with the second mark code 20, so as not to affect the decoding rate.
Referring to fig. 5, fig. 5 is a schematic plan view of a solar cell according to the present invention, in which the solar cell 2000 in fig. 5 includes a silicon wafer 1000, and the solar cell 2000 of this embodiment includes a mark code, specifically, a first mark code 10 and a second mark code 20, and further includes a half mark code 30.
In order to derive the current generated by the photovoltaic effect in the silicon wafer 1000, the gate line electrode 200 needs to be disposed on the surface of the silicon wafer 1000, the gate line electrode 200 may be composed of a main gate line and a thin gate line, and the main gate line and the thin gate line may be made of a conductive metal material such as copper, nickel, aluminum, silver, or an aluminum-silver alloy. The solar cell 2000 further includes thin gate lines arranged in the row direction X and the column direction Y, and main gate lines arranged in the row direction X and the column direction Y, and it should be noted that the number and the spacing of the thin gate lines and the main gate lines in fig. 5 are not limited to actual products, and are only schematic illustrations.
Referring to fig. 5, for a two-piece solar cell, a blank area 300 is usually disposed at the position of the symmetry axis of the solar cell, so as to be conveniently cut into two halves, the main grid lines are disconnected in the blank area 300, and certainly, no fine grid lines are disposed in the blank area 300.
It should be noted that the size, shape and position of the first mark code 10 and the second mark code 20 in fig. 5 are only schematic illustrations, and the first mark code 10 and the second mark code 20 may be located in the middle of the solar cell or at the edge of the solar cell, and are not limited in this respect.
The manufacturing processes of the solar cell are more, the process and parameters of the solar cell end are continuously added to the content of the mark code according to the accumulation of the manufacturing processes, the process and the parameters are only schematically illustrated, in addition, the mark code of the previous process is damaged in the process of manufacturing the solar cell, and the decoding rate can be improved in a mode of repeatedly printing the code for many times.
In some optional embodiments, the solar cell may be multi-segment, the solar cell may be three-segment, four-segment, six-segment, and the like, and more than two mark codes may be correspondingly set, at this time, the mark codes may not be set on the central axis, the mark codes may be set at the same position corresponding to each segment, or adjacent mark codes are line-symmetric along the cutting line, so as to ensure that after the silicon wafer is cut, each segment has a mark code, and no specific limitation is made here. Of course, the slicing marks may be set to distinguish the slicing positions, for example, a horizontal line is set on the first slice, a circle is set on the second slice, and an oblique line is set on the third slice, which are only schematic illustrations here, as long as the slicing positions can be distinguished by the slicing marks.
Of course, the solar cell 2000 of the present embodiment also has the beneficial effects of the silicon wafer 1000, and the description thereof is omitted here.
According to the embodiment, the silicon wafer and the manufacturing method thereof provided by the invention at least realize the following beneficial effects:
when the silicon wafer is manufactured, firstly, crystal pulling manufacture data of a crystal bar and quality data of the crystal bar are recorded, then, a crystal bar is subjected to a slicing process to obtain a first silicon wafer, slicing manufacture data of the slicing process is recorded, the first silicon wafer is subjected to a degumming cleaning process to obtain a second silicon wafer, cleaning manufacture data of the cleaning process is recorded, the second silicon wafer is subjected to a sorting process to obtain a third silicon wafer, sorting data of the sorting process is recorded, when a mark code is formed on the surface of the third silicon wafer, crystal pulling manufacture data of the crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning data and sorting data can be included, original data of the crystal bar can be traced in the manufactured mark code silicon wafer, length information of the crystal bar is contained in the quality data of the crystal bar, and the position of the crystal bar can be restored after the mark code is decoded.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. A method for manufacturing a silicon wafer is characterized by comprising the following steps:
providing a crystal bar, and recording crystal pulling production data of the crystal bar and quality data of the crystal bar;
carrying out a slicing procedure on the crystal bar to obtain a first silicon wafer, and recording slice manufacturing data of the slicing procedure;
carrying out a degumming cleaning procedure on the first silicon chip to obtain a second silicon chip, and recording cleaning manufacturing data of the cleaning procedure;
carrying out a sorting procedure on the second silicon wafer to obtain a third silicon wafer, and recording sorting data of the sorting procedure;
and forming a mark code on the surface of the third silicon wafer to obtain a mark code silicon wafer, wherein the mark code comprises crystal pulling manufacture data of the crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning manufacture data and sorting data.
2. The method for manufacturing a silicon wafer according to claim 1, wherein the step of performing a degumming cleaning process on the first silicon wafer to obtain a second silicon wafer, and the step of recording cleaning production data of the cleaning process comprises:
the method comprises the steps that a first silicon wafer is fed into a flower basket, a flower basket identification code is arranged on the flower basket, and data obtained by cleaning the first silicon wafer comprise the flower basket identification code.
3. The method of claim 1, wherein forming the mark code on the surface of the third silicon wafer to obtain a mark code silicon wafer comprises:
and taking a virtual symmetry axis and a virtual diagonal of the third silicon wafer, wherein the virtual symmetry axis divides the silicon wafer into a first half wafer and a second half wafer, a first mark code and a second mark code are formed on the virtual diagonal, the first mark code and the second mark code are in central symmetry, and the first mark code and the second mark code are respectively located on the first half wafer and the second half wafer.
4. The method for manufacturing a silicon wafer according to claim 1, wherein a first mark point and a second mark point are formed on the surface of the third silicon wafer, a plurality of first mark points form the first mark code, a plurality of second mark points form the second mark code, the virtual symmetry axis and the virtual diagonal have an intersection point, and the distance from the first mark point to the intersection point is equal to the distance from the second mark point to the intersection point.
5. The method of claim 3, further comprising forming a half-chip identification code on the third silicon wafer surface, comprising:
forming said half-chip identification code in said first half-chip, said half-chip identification code being non-coincident with said first indicia code;
or forming the half-piece identification code on the second half-piece, wherein the half-piece identification code is not overlapped with the second mark code.
6. The method of manufacturing a silicon wafer according to claim 5, wherein a pattern of one of a diagonal line, a transverse line, a vertical line, a circle, a semicircle, an ellipse, a star, or a drop is formed on the surface of the third silicon wafer as the half-chip identification code.
7. The method of claim 1, wherein the identification code comprises a two-dimensional code or a bar code.
8. The method of claim 1, wherein the mark code is formed by laser or high energy particle impact.
9. The silicon wafer is characterized in that the surface of the silicon wafer comprises mark codes, and the mark codes comprise crystal pulling manufacture data of a crystal bar, quality data of the crystal bar, slicing manufacture data, cleaning manufacture data and sorting data.
10. The silicon wafer of claim 9, wherein the silicon wafer comprises a virtual symmetry axis and a virtual diagonal, the virtual symmetry axis divides the silicon wafer into a first half and a second half, the mark codes comprise a first mark code and a second mark code, the first mark code and the second mark code are located on the virtual diagonal, the first mark code and the second mark code are centrosymmetric, and the first mark code and the second mark code are located on the first half and the second half, respectively;
the silicon wafer further comprises a half-wafer identification code:
the half-piece identification code is positioned on the first half piece, and the half-piece identification code is not overlapped with the first mark code;
or the half-piece identification code is positioned on the second half piece, and the half-piece identification code is not overlapped with the second mark code.
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