CN115020475A - Planar gate SJ IGBT device with Schottky contact - Google Patents
Planar gate SJ IGBT device with Schottky contact Download PDFInfo
- Publication number
- CN115020475A CN115020475A CN202210754547.5A CN202210754547A CN115020475A CN 115020475 A CN115020475 A CN 115020475A CN 202210754547 A CN202210754547 A CN 202210754547A CN 115020475 A CN115020475 A CN 115020475A
- Authority
- CN
- China
- Prior art keywords
- region
- type
- emitter
- metal
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 210000000746 body region Anatomy 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 210000003850 cellular structure Anatomy 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000000605 extraction Methods 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract 1
- 238000005036 potential barrier Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a planar gate SJ IGBT device with Schottky contact, and belongs to the technical field of power semiconductor devices. According to the invention, a P-type ring region is introduced into a JFET region of a traditional plane gate SJ IGBT device, and the P-type ring region is connected with emitter metal to form Schottky contact, so that a hole barrier is formed between the P-type ring region and the emitter metal. When the device is in an on state, the potential barrier blocks a hole from directly flowing to the emitter from the P-type ring region, and the carrier concentration of the cathode side of the device is ensured; in the turn-off process, a new hole extraction path is formed by the P-type ring region and the emitter metal, so that the extraction of redundant minority carriers in the drift region is accelerated, the turn-off speed of the device is improved, and the turn-off loss of the device is reduced.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a planar gate SJ IGBT device with Schottky contact.
Background
Insulated Gate Bipolar Transistor (IGBT) has become a core device of medium and high power electronic system because it has the advantages of high input resistance, fast switching speed, easy driving, etc. of MOS devices and low forward voltage drop of Bipolar devices. The IGBT technology has been developed to the seventh generation, and a Field Stop (FS) technology, a Carrier Stored (CS) technology, a floating P-body region, a sheet process and other new structures and new processes are adopted, so that the static and dynamic performance and reliability of the IGBT device are significantly improved. In addition to the above-mentioned technologies, Super Junction (SJ) technology can be adopted to further improve the dynamic and static performances of the IGBT device. Compared with the traditional IGBT device, the SJ IGBT device can have lower turn-off loss at the same withstand voltage level, but with the continuous development of the application scene of the IGBT device, the IGBT device is required to have higher switching speed.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a planar gate SJ IGBT device with Schottky contact. According to the invention, the P-type doped P-type ring region is introduced into the JFET region of the planar gate SJ IGBT device, and Schottky contact is formed between the P-type ring region and the emitter metal, so that the switching speed of the planar gate SI IGBT device is increased, and the turn-off loss is reduced.
In order to solve the technical problem, an embodiment of the invention provides a planar gate SJ IGBT device with schottky contact, a cellular structure of which includes a collector metal 1, a P + collector region 2, an N-type field stop region 3, a drift region, an N-type carrier storage region 6, and a metal emitter 12, which are sequentially stacked from bottom to top;
the drift region is provided with a super junction structure formed by a P column 4 and an N column 5, wherein the side surfaces of the P column 4 and the N column 5 are mutually contacted, and the P column 4 is positioned at two sides of the N column 5;
the top layer of the N-type carrier storage region 6 is provided with P-type body regions 7 at two sides, the top layer of the N-type carrier storage region 6 between the two P-type body regions 7 is provided with a P-type ring region 10, and the P-type body regions 7 and the P-type ring region 10 are isolated by the N-type carrier storage region 6; the top layer of the P-type body region 7 is provided with an N + type emitting region 8;
a gate dielectric 11 is arranged on the first part of the N + type emitter region 8, the first part of the P type body region 7, the first part of the P type ring region 10 and the N type carrier storage region 6, and the gate electrode 9 is positioned in the gate dielectric 11; a metal emitter 12 is arranged on the second part of the N + type emitter region 8, the second part of the P type body region 7, the second part of the P type ring region 10 and the gate dielectric 11, the gate electrode 9 is isolated from the metal emitter 12 and the N type carrier storage region 6 through the gate dielectric 11, and the two gate dielectrics 11 are isolated through the metal emitter 12; ohmic contact is formed between the metal emitter 12 and the P-type body region 7 and the N + -type emitter region 8, and schottky contact is formed between the metal emitter 12 and the P-type ring region 10.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the material used for the gate electrode 9 is polysilicon or metal.
Furthermore, the semiconductor material used by the device is monocrystalline silicon, silicon carbide or gallium nitride.
The invention has the beneficial effects that: compared with the prior flat grid SJ IGBT structure, the flat grid SJ IGBT structure with Schottky contact provided by the invention has the advantages that in the conducting state, the Schottky barrier between the metal emitter and the P-type ring region blocks the direct flow of holes from the P-type ring region to the emitter, the carrier concentration of the cathode side of the device is ensured, and the conducting voltage drop is comparable to that of the prior flat grid SJ IGBT structure; in the turn-off process of the device, the P-type ring area is connected with the emitting electrode through metal, an extra hole extraction channel is provided, the switching speed of the plane gate SJ IGBT device is increased, and the turn-off loss of the device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a planar gate SJ IGBT device with schottky contacts according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a conventional planar gate SJ IGBT.
In the drawings, the components represented by the respective reference numerals are listed below:
the device comprises a collector metal 1, a P + type collector region 2, an N field stop region 3, a P type column region 4, an N type column region 5, an N type carrier storage region 6, a P type body region 7, an N + type emitter region 8, a gate electrode 9, a P type ring region 10, a gate dielectric 11 and an emitter metal 12.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a planar gate SJ IGBT device with schottky contact according to a first embodiment of the present invention has a cellular structure including a collector metal 1, a P + collector region 2, an N-type field stop region 3, a drift region, an N-type carrier storage region 6, and a metal emitter 12, which are sequentially stacked from bottom to top;
the drift region is provided with a super junction structure formed by a P column 4 and an N column 5, wherein the side surfaces of the P column 4 and the N column 5 are mutually contacted, and the P column 4 is positioned at two sides of the N column 5;
the top layer of the N-type carrier storage region 6 is provided with P-type body regions 7 at two sides, the top layer of the N-type carrier storage region 6 between the two P-type body regions 7 is provided with a P-type ring region 10, and the P-type body regions 7 and the P-type ring region 10 are isolated by the N-type carrier storage region 6; the top layer of the P-type body region 7 is provided with an N + type emitting region 8;
a gate dielectric 11 is arranged on the first part of the N + type emitter region 8, the first part of the P type body region 7, the first part of the P type ring region 10 and the N type carrier storage region 6, and the gate electrode 9 is positioned in the gate dielectric 11; a metal emitter 12 is arranged on the second part of the N + type emitter region 8, the second part of the P type body region 7, the second part of the P type ring region 10 and the gate dielectric 11, the gate electrode 9 is isolated from the metal emitter 12 and the N type carrier storage region 6 through the gate dielectric 11, and the two gate dielectrics 11 are isolated through the metal emitter 12; ohmic contact is formed between the metal emitter 12 and the P-type body region 7 and the N + -type emitter region 8, and schottky contact is formed between the metal emitter 12 and the P-type ring region 10.
The working principle of the embodiment is as follows:
the planar gate SJ IGBT device with the Schottky contact has similar conduction voltage drop, faster switching speed and lower turn-off loss compared with the traditional structure (shown in figure 2) under normal operation.
When the device is in a conducting state, a Schottky contact barrier between the metal emitter and the P-type ring region blocks holes from flowing from the P-type ring region to the emitter directly, the carrier concentration of the cathode side of the device is guaranteed, and compared with the conventional flat gate SJ IGBT structure, the Schottky contact barrier has conducting voltage drop.
In the turn-off process of the device, the P-type ring area is connected with the emitting electrode through metal, an extra hole extraction channel is provided, the switching speed of the plane gate SJ IGBT device is increased, and the turn-off loss of the device is reduced.
Optionally, the material of the gate electrode 9 is polysilicon or metal.
Optionally, the semiconductor material used for the device is single crystal silicon, silicon carbide or gallium nitride.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (3)
1. A planar gate SJ IGBT device with Schottky contact is characterized in that a cellular structure comprises a collector metal (1), a P + collector region (2), an N-type field stop region (3), a drift region, an N-type carrier storage region (6) and a metal emitter (12) which are sequentially stacked from bottom to top;
the drift region is provided with a super junction structure formed by a P column (4) and an N column (5) with side surfaces mutually contacted, and the P column (4) is positioned at two sides of the N column (5);
the two sides of the top layer of the N-type carrier storage region (6) are provided with P-type body regions (7), the top layer of the N-type carrier storage region (6) between the two P-type body regions (7) is provided with a P-type ring region (10), and the P-type body regions (7) and the P-type ring region (10) are isolated by the N-type carrier storage region (6); the top layer of the P-type body region (7) is provided with an N + type emitter region (8);
a gate dielectric (11) is arranged on the first part of the N + type emitter region (8), the first part of the P type body region (7), the first part of the P type ring region (10) and the N type carrier storage region (6), and the gate electrode (9) is positioned in the gate dielectric (11); a metal emitter (12) is arranged on the second part of the N + type emitter region (8), the second part of the P type body region (7), the second part of the P type ring region (10) and the gate dielectric (11), the gate electrode (9) is isolated from the metal emitter (12) and the N type carrier storage region (6) through the gate dielectric (11), and the two gate dielectrics (11) are isolated through the metal emitter (12); ohmic contact is formed between the metal emitter (12) and the P-type body region (7) and the N + type emitter region (8), and Schottky contact is formed between the metal emitter (12) and the P-type ring region (10).
2. The planar gate SJ IGBT device with Schottky contact as claimed in claim 1, wherein the gate electrode (9) is made of polysilicon or metal.
3. The SJ IGBT device with Schottky contacts as claimed in claim 1, wherein the semiconductor material used for the device is single crystal silicon, silicon carbide or gallium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210754547.5A CN115020475A (en) | 2022-06-30 | 2022-06-30 | Planar gate SJ IGBT device with Schottky contact |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210754547.5A CN115020475A (en) | 2022-06-30 | 2022-06-30 | Planar gate SJ IGBT device with Schottky contact |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115020475A true CN115020475A (en) | 2022-09-06 |
Family
ID=83079864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210754547.5A Pending CN115020475A (en) | 2022-06-30 | 2022-06-30 | Planar gate SJ IGBT device with Schottky contact |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115020475A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115440589A (en) * | 2022-10-26 | 2022-12-06 | 深圳市美浦森半导体有限公司 | IGBT device and manufacturing method thereof |
-
2022
- 2022-06-30 CN CN202210754547.5A patent/CN115020475A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115440589A (en) * | 2022-10-26 | 2022-12-06 | 深圳市美浦森半导体有限公司 | IGBT device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103383958A (en) | Reverse conducting (RC)-insulated gate bipolar transistor (IGBT) device and manufacturing method thereof | |
| CN105206656A (en) | Reverse conducting IGBT device | |
| CN114664929B (en) | Split gate SiC MOSFET integrated with heterojunction diode and manufacturing method thereof | |
| CN202282352U (en) | High-voltage IGBT forming FS layer through epitaxial method | |
| CN110137250B (en) | High-speed IGBT device with ultralow conduction voltage drop | |
| US9263560B2 (en) | Power semiconductor device having reduced gate-collector capacitance | |
| CN114784108B (en) | Planar gate SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof | |
| CN108899363B (en) | Trench gate IGBT device capable of reducing on-voltage drop and turn-off loss | |
| US6255692B1 (en) | Trench-gate semiconductor device | |
| CN108336133B (en) | Silicon carbide insulated gate bipolar transistor and manufacturing method thereof | |
| US20240274656A1 (en) | Semiconductor device | |
| CN117497601B (en) | Structure, manufacturing method and electronic equipment of planar silicon carbide transistor | |
| CN117476774B (en) | Structure, manufacturing method and electronic equipment of vertical silicon carbide transistor | |
| CN117497600B (en) | Structure, manufacturing method and electronic equipment of super-junction silicon carbide transistor | |
| CN117497579B (en) | Silicon carbide IGBT structure, manufacturing method and electronic equipment | |
| CN115020475A (en) | Planar gate SJ IGBT device with Schottky contact | |
| CN114784107A (en) | SiC MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with junction barrier Schottky diode and manufacturing method thereof | |
| CN110534575B (en) | VDMOS device | |
| CN116404039B (en) | Power semiconductor device and manufacturing method thereof | |
| CN110504314B (en) | Groove-type insulated gate bipolar transistor and preparation method thereof | |
| CN117116937A (en) | RC-IGBT device structure and preparation method | |
| CN111668212A (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN110534566B (en) | IGBT power device | |
| CN111211167B (en) | RC-IGBT device structure for eliminating negative resistance effect | |
| CN110444590B (en) | Super junction LIGBT power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |