CN115020259A - Semiconductor structure and packaging method thereof - Google Patents
Semiconductor structure and packaging method thereof Download PDFInfo
- Publication number
- CN115020259A CN115020259A CN202210739444.1A CN202210739444A CN115020259A CN 115020259 A CN115020259 A CN 115020259A CN 202210739444 A CN202210739444 A CN 202210739444A CN 115020259 A CN115020259 A CN 115020259A
- Authority
- CN
- China
- Prior art keywords
- groove
- solder
- layer
- photoresist layer
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
- H01L2224/1607—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
Abstract
The invention discloses a semiconductor structure and a packaging method thereof, which comprises the steps of providing a substrate with a first surface and a second surface which are oppositely arranged, wherein a solder bump is arranged on the first surface, and a metal convex layer is arranged on the second surface; forming a photoresist layer I on the second surface, wherein the photoresist layer I is provided with a first groove which exposes the top of the metal convex layer; providing a chip with a first upper surface and a second lower surface which are opposite to each other, wherein the first upper surface is provided with bonding pads, and the upper surface of each bonding pad is correspondingly provided with a conductive connecting layer; forming a photoresist layer II on the first upper surface and the conductive connecting layer, wherein the photoresist layer II is provided with a second groove which exposes the top of the conductive connecting layer; a conductive sheet is arranged in the second groove, and one side of the conductive sheet, which is opposite to the conductive connecting layer, is provided with a notch for accommodating the solder bump; and bonding and connecting the conducting sheet of the chip and the metal convex layer of the substrate. The invention clamps and positions the chip during flip-chip welding by utilizing the shape of the conducting strip, thereby improving the production yield.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a packaging method thereof.
Background
Due to the development of semiconductor integration and high performance miniaturization, the flip chip technology has been widely used. Chinese patent application No. 2005101038187, published as 2008.07.02 discloses a semiconductor device and a method of manufacturing the same, wherein, as shown in fig. 1, a semiconductor device 10 has a flip chip bonding structure including a microchip 11 and a substrate 13, a first electrode pad 12 on the microchip 11 is electrically connected to a second electrode pad 14 on the substrate 13 through a first low melting point solder layer 16, a solder bump 15 and a second low melting point solder layer 17, and a gap portion between the microchip 11 and the substrate 13 is filled with a sealing resin 18. When the technology is adopted to perform flip chip welding on a chip, the problem of short circuit easily exists in the adjacent solder bumps 15, meanwhile, when the substrate or the chip is warped due to the action of thermal stress, the problem of virtual connection easily occurs between the solder bumps and the corresponding second electrode pads, and in addition, the problems of displacement, deviation or inclination easily occur in the chip welding process due to uneven down pressure of the solder bumps or the chip.
Chinese patent application No. 2019104776156, published japanese patent No. 2019.10.01, discloses a semiconductor bonding packaging method, as shown in fig. 2, a pad 31 of a chip 30 is connected with a metal bump 11 of a substrate 10 through a functional bump 33 and a solder 34 by a thermocompression bonding method, which solves the problem of short circuit of adjacent solder balls, but also has the problem of virtual connection between the solder balls and corresponding pads when the substrate or the chip is warped, and meanwhile, the manufacturing process also needs a special jig for pressing, which is high in cost.
Disclosure of Invention
In view of the above technical problems, the present invention provides a semiconductor structure and a packaging method thereof. In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a packaging method of a semiconductor structure comprises the following steps:
s1, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, the first surface is provided with a plurality of solder bumps, and the second surface is provided with a plurality of metal convex layers;
s2, forming a photoresist layer I on the second surface, wherein the photoresist layer I is provided with a first groove which exposes the top of the metal convex layer;
s3, providing a chip, wherein the chip is provided with a first upper surface and a second lower surface which are opposite, the first upper surface is provided with a plurality of bonding pads, and the upper surface of each bonding pad is correspondingly provided with a conductive connecting layer;
s4, forming a photoresist layer II on the first upper surface and the conductive connecting layer, wherein the photoresist layer II is provided with a second groove exposing the top of the conductive connecting layer;
s5, arranging a conductive sheet in the second groove, wherein one side of the conductive sheet, which is opposite to the conductive connecting layer, is provided with a notch for accommodating the solder bump;
and S6, bonding and connecting the conducting sheet of the chip and the metal convex layer of the substrate by a hot-pressing bonding method.
The step S5 includes the following steps:
s5.1, providing solder pads, and respectively placing the solder pads on the second grooves to enable at least two opposite side edges of the solder pads to be lapped on the photoresist layer II on the periphery of the second grooves;
s5.2, placing the conducting sheet on the solder pad, wherein the conducting sheet is positioned right above the second groove, and pressing the conducting sheet downwards to bend the solder pad so as to position and clamp the conducting sheet;
and S5.3, heating the solder pad to enable the solder pad to be molten into solder and to reflow to the bottom of the second groove, and further welding and fixing the conducting sheet and the conducting connecting layer.
Preferably, the step S5 may also include the following steps:
s5.1a, etching a gasket placing groove with the size consistent with that of the solder gasket on the photoresist layer II, wherein the size of the gasket placing groove in the length direction is larger than that of the second groove, or the size of the gasket placing groove in the width direction is larger than that of the second groove;
s5.1b, providing a solder gasket, and placing the solder gasket in the gasket placing groove so that at least two opposite side edges of the solder gasket are lapped on the photoresist layer II where the gasket placing groove is located;
s5.2, placing the conducting sheet on the solder pad, wherein the conducting sheet is positioned right above the second groove, and pressing the conducting sheet downwards to bend the solder pad so as to position and clamp the conducting sheet;
and S5.3, heating the solder pad to enable the solder pad to be molten into solder and to reflow to the bottom of the second groove, and further welding and fixing the conducting sheet and the conducting connecting layer.
In order to facilitate positioning of the conducting strip, the length of the solder pad is smaller than that of the second groove, and the width of the solder pad is larger than that of the second groove, or the length of the solder pad is larger than that of the second groove, and the width of the solder pad is smaller than that of the second groove.
To avoid solder overflow, the solder pad has a thickness no greater than 1/3 of the depth of the second recess.
The length of the conducting strip is smaller than or equal to that of the second groove, and the width of the conducting strip is smaller than or equal to that of the second groove, so that the conducting strip can be placed conveniently.
The total thickness of the metal convex layer, the solder bump and the conducting sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conducting sheet and lower than the total height of the conducting sheet and the solder bump.
A semiconductor structure comprises at least one semiconductor module, wherein a plurality of semiconductor modules are connected through a substrate in each module; each semiconductor module includes:
the substrate is provided with a first surface and a second surface which are oppositely arranged, the second surface is provided with a plurality of metal convex layers, a photoresist layer I is arranged between every two adjacent metal convex layers, and the upper part of each metal convex layer is provided with a first groove formed by the photoresist layer I and the metal convex layer in a surrounding mode;
the chip is provided with a first upper surface and a second lower surface which are oppositely arranged, a plurality of bonding pads are arranged on the first upper surface, a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad, a photoresist layer II is arranged between every two adjacent conductive connecting layers, and a second groove surrounded by the photoresist layer II and the conductive connecting layers is arranged at the upper part of each conductive connecting layer;
the conductive sheet is arranged in the second groove, one side of the conductive sheet, which is opposite to the conductive connecting layer, is provided with a notch matched with the shape of the solder bump, and the conductive connecting layer is connected with the metal convex layer through the conductive sheet and the solder bump.
The total thickness of the metal convex layer, the solder bump and the conducting sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conducting sheet and lower than the total height of the conducting sheet and the solder bump.
The invention has the beneficial effects that:
the conducting sheet with the shape matched with the shape of the solder bump is arranged, and the other side of the conducting sheet is welded with the conducting connecting layer through the solder gasket, so that clamping and positioning are performed when the chip is in flip-chip welding through the shape of the conducting sheet, the problems of displacement, offset or inclination in the chip welding process are avoided, the manufacturing yield of a semiconductor is improved, and the phenomena of offset and desoldering are reduced; the gasket placing groove can play the effect of location to the solder gasket, and then fixes a position and the centre gripping to the conducting strip through the solder gasket better, and conducting strip and solder gasket can improve the electric connection cohesiveness between solder bump and the base plate after the high temperature backward flow, and then reach the problem of effectively improving virtual connection and rosin joint, further improve the technology process of semiconductor, improve the production yield.
Meanwhile, when the chip is bonded with the substrate, the arch-like structure of the conducting plate can decompose mechanical force in the hot pressing process, so that the pressure in the direction perpendicular to the substrate and the chip is reduced, the warping in the directions of the substrate and the chip is further reduced, the poor disconnection caused by the warping is further reduced, and the packaging quality is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device in the prior art.
Fig. 2 is a schematic diagram of another prior art semiconductor device.
Fig. 3 is a cross-sectional view of a substrate.
FIG. 4 is a cross-sectional view of a first recess formed in a substrate.
Fig. 5 is a cross-sectional view of a chip.
Fig. 6-8 are cross-sectional views illustrating a process of forming the second groove.
Fig. 9 is a top view and corresponding cross-sectional view after formation of a gasket-placing groove.
Fig. 10 is a top view and corresponding cross-sectional view of placing a solder pad directly on photoresist layer II.
Fig. 11 is a top view and corresponding cross-sectional view of placing a solder pad on a pad placement channel.
Fig. 12 is a top view and corresponding cross-sectional view of the placement of a conductive tab on the solder pad of fig. 10.
Fig. 13 is a top view and corresponding cross-sectional view of the placement of a conductive tab on the solder pad of fig. 11.
FIG. 14 is a cross-sectional view of the conductive sheet after being formed in the second groove.
Fig. 15 is a schematic cross-sectional view of a conductive sheet with solder bumps added.
Fig. 16 is a schematic cross-sectional view of the chip and the substrate after they are connected.
Is a schematic cross-sectional view illustrating a semiconductor manufacturing process of the present invention.
In the figure, 1 is a substrate, 1-1 is a solder bump, 2 is a photoresist layer I, 3 is a metal bump, 4 is a solder bump, 5 is a photoresist layer II, 6 is a conductive sheet, 7 is a conductive connection layer, 8 is a pad, 9 is a chip, 101 is a first mask layer, 111 is a first groove, 112 is a second groove, 113 is a pad placement groove, and 93 is a solder pad.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Example 1: a method for packaging a semiconductor, comprising the steps of:
s1, providing a substrate, as shown in fig. 3, where the substrate 1 has a first surface and a second surface opposite to each other, the first surface is provided with a plurality of solder bumps 1-1, and the second surface is provided with a plurality of metal bumps 3;
in step S1, the substrate 1 may be a PCB board or other substrate.
S2, forming a photoresist layer I2 on the second surface, wherein the photoresist layer I2 is provided with a first groove 111 exposing the top of the metal convex layer;
as shown in fig. 4, a layer of photoresist is first coated on the second surface of the substrate 1, the photoresist covers the second surface of the substrate, and the upper surface of the photoresist layer is higher than the upper surface of the metal convex layer. The patterned photoresist layer I is formed by exposure and development, the top of the metal convex layer is exposed, and the side wall of the photoresist layer I and the upper surface of the metal convex layer form a first groove 111, so that the flip chip bonding with the chip is facilitated.
S3, providing a chip, as shown in fig. 5, where the chip 9 has a first upper surface and a second lower surface opposite to each other, the first upper surface is provided with a plurality of bonding pads 8, and the upper surface of each bonding pad is correspondingly provided with a conductive connection layer 7;
specifically, a chip 9 is provided, the chip 9 has a first upper surface and a second lower surface which are opposite to each other, a plurality of bonding pads 8 are arranged on the first upper surface, a metal layer covers the first upper surface and all the bonding pads, a photoresist layer is coated on the metal layer, the metal layer between two adjacent bonding pads is exposed through illumination and development, the metal layer between the two bonding pads is etched to form a conductive connecting layer 7 which is located right above the bonding pads, and the photoresist on the conductive connecting layer is removed, wherein the size of the conductive connecting layer is smaller than that of the bonding pads.
S4, forming a photoresist layer II5 on the first upper surface and the conductive connecting layer 7, wherein the photoresist layer II5 is provided with a second groove 112 exposing the top of the conductive connecting layer;
as shown in fig. 6 to 8, a photoresist layer II is covered on the conductive connection layer 7 and the first upper surface of the chip 9, a patterned first mask layer 101 is formed on the photoresist layer II, the photoresist layer II is etched by using the first mask layer as a mask to expose the top of the conductive connection layer 7, and a second groove 112 is formed on the sidewall of the photoresist layer II and the upper surface of the conductive connection layer, so as to implement the flip-chip electrical connection with the substrate. The photoresist layer II between the two conductive connection layers realizes electrical isolation between the adjacent pads.
S5, placing a conductive sheet 6 in the second groove 112, wherein the conductive sheet 6 has a notch for accommodating the solder bump 4 on the side opposite to the conductive connection layer;
as shown in fig. 9 to 13, the step S5 includes the following steps:
s5.1, as shown in fig. 10, providing solder pads 93, placing each solder pad 93 on the second groove 112 respectively, so that at least two opposite side edges of the solder pad 93 overlap the photoresist layer II5 on the periphery of the second groove 112;
preferably, the step S5.1 may also include the steps of:
a. as shown in fig. 9, a pad placement groove 113 conforming to the size of the solder pad 93 is etched on the photoresist layer II5, the size in the length direction or the size in the width direction of the pad placement groove 113 being larger than the corresponding size of the second groove 112;
b. as illustrated in fig. 11, providing a solder pad 93, placing the solder pad 93 in the pad placement groove 113 so that at least two opposite side edges of the solder pad 93 overlap the photoresist layer II5 on which the pad placement groove 113 is located;
the solder pad is a cuboid, and the size setting conditions of the solder pad are as follows: the length of the solder pad is smaller than that of the second groove, the width of the solder pad is larger than that of the second groove, or the length of the solder pad is larger than that of the second groove, and the width of the solder pad is smaller than that of the second groove; and the thickness of the solder pad is not more than 1/3 of the depth of the second groove, so that the solder pad can be correspondingly carried on the photoresist layer II around the second groove when being laid above the second groove, and the conductive sheet is prevented from being exposed out of the second groove when the solder pad is melted, thereby facilitating the placement of solder bumps. In this embodiment, the length L1 of the solder pad is less than the length L2 of the second groove, and the width W1 of the solder pad is greater than the width W2 of the second groove.
In this embodiment, the gasket placing groove is a square groove, and the center of the square groove coincides with the center of the second groove, so that the two sides of the solder gasket can uniformly and stably clamp the conductive sheet. Adjacent gasket placing grooves are not connected with each other, so that the error connection between adjacent welding discs in the melting process is avoided, and the gasket placing grooves can play a role in positioning the welding flux gaskets. The solder bump is made of tin, and the conductive sheet is made of copper or an alloy thereof.
S5.2, as shown in FIG. 12 or FIG. 13, placing the conducting strip 6 on the solder pad 93, and the conducting strip 6 is located right above the second groove 112, pressing the conducting strip 6 downwards to bend the solder pad 93 to position and temporarily clamp the conducting strip;
preferably, the length L3 of the conducting strip is less than or equal to the length L2 of the second groove, and the width W3 of the conducting strip is less than or equal to the width W2 of the second groove, so that the conducting strip can be placed in the second groove, and the height of the conducting strip is less than or equal to half of the depth of the second groove, so as to ensure the stability of the solder ball when the solder ball is placed at a later stage. In this embodiment, the length L3 of the conductive strip is slightly less than the length L2 of the second groove, and the width W3 of the conductive strip is slightly less than the width W2 of the second groove (not shown in fig. 10). Place every conducting strip correspondingly on every solder pad, do not connect between the adjacent solder pad, the bottom of conducting strip is the plane shape, make it laminate with the bottom of second recess well, the top of conducting strip is equipped with the notch, the bottom of notch is located the middle part of conducting strip, and the shape of notch is identical with the solder bump also that the shape of solder ball is identical, make the notch bear well and hold the solder ball, be convenient for place at the chip flip-chip and play the effect of clamp system and location chip with the welding in-process, and then solve because solder ball or chip pushing down force is inhomogeneous and lead to taking place the aversion among the chip welding process, the problem of skew or slope, simultaneously, because the conducting strip does not need special tool also to solve the higher problem of cost. The solder pad can play a role in positioning the conducting strip, the conducting strip is prevented from shifting in the welding process, the conducting strip is pressed downwards, and the solder pad is pressed to deform and is bent towards the direction of the second groove until the conducting strip is clamped. The bent shape of the solder pad may be V-shaped or U-shaped.
Preferably, the shape of the solder pad can be any shape and material as long as the conductive sheet can be positioned and temporarily clamped after being deformed by pressure, and the solder is melted after being heated and reflows to the bottom of the second groove, so that the conductive sheet and the conductive connecting layer are welded without affecting the electrical connection between the conductive sheet and the conductive connecting layer.
S5.3, as shown in fig. 14 and 15, the solder pad 93 is heated, so that the solder pad is melted into solder and reflows to the bottom of the second groove 112, and the conductive sheet 6 and the conductive connection layer 7 are soldered and fixed.
The chip with the solder pad and the conducting sheet placed is heated and subjected to high-temperature reflow treatment, the solder pad is melted into fluid through high temperature to become solder, the solder can be welded and fixed with the conducting connecting layer due to the material characteristics of the solder, such as small intermolecular distance, large intermolecular attraction and surface tension, and then the solder reflows to the bottom of the second groove, namely the surface of the conducting connecting layer opposite to the second groove and is solidified, and the conducting sheet is formed on the surface of the conducting connecting layer and part of the side wall of the second groove due to the action of the surface tension after becoming the semi-solidified conducting material. The solder bumps 4 are arranged on the conducting strips, bridging between the adjacent conducting strips is caused for avoiding overflow of solder of the solder bumps, the total thickness of the metal convex layer, the solder bumps and the conducting strips does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than that of the conducting strips 6 and lower than that of the conducting strips 6 and the solder bumps.
S6, as shown in fig. 16, the conductive sheet 6 of the chip and the metal bump 3 of the substrate are bonded and connected by thermocompression bonding.
The conducting strip of the chip is connected with the metal convex layer of the substrate through the solder bump, the conducting strip and the metal convex layer are connected through the melting of the solder bump under the hot-pressing bonding process, and then the melting solder bump is subjected to cold-solidification forming, so that the stable electric connection among the bonding pad of the chip, the conducting connecting layer, the conducting strip and the metal convex layer of the substrate is realized. The metal convex layers on the substrate are more, one or more same or different chips can be connected with the substrate, the integration process of the wafer is realized, the packaging efficiency is improved, and the element size is reduced.
In this embodiment, the length and the width of the first groove and the second groove are consistent, so as to facilitate positioning and fixing the chip.
Example 2: a semiconductor structure comprises at least one semiconductor module, wherein a plurality of semiconductor modules are connected through a substrate in each module; each semiconductor module includes:
the substrate is provided with a first surface and a second surface which are oppositely arranged, the second surface is provided with a plurality of metal convex layers, a photoresist layer I is arranged between every two adjacent metal convex layers, and the upper part of each metal convex layer is provided with a first groove formed by the photoresist layer I and the metal convex layer in a surrounding mode;
the chip is provided with a first upper surface and a second lower surface which are oppositely arranged, a plurality of bonding pads are arranged on the first upper surface, a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad, a photoresist layer II is arranged between every two adjacent conductive connecting layers, and a second groove surrounded by the photoresist layer II and the conductive connecting layers is arranged at the upper part of each conductive connecting layer;
and the conductive sheet is arranged in the second groove, one side of the conductive sheet, which is back to the conductive connecting layer, is provided with a notch matched with the shape of the solder bump, and the conductive connecting layer is connected with the metal convex layer through the conductive sheet and the solder bump.
The total thickness of the metal convex layer, the solder bump and the conducting sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is higher than the height of the conducting sheet and lower than the total height of the conducting sheet and the solder bump.
In this embodiment, the manufacturing method and the structural requirements of each structure are as shown in embodiment 1, and a solder pad is further disposed between the conductive sheet and the conductive connection layer, and the structure and the arrangement method thereof are as shown in embodiment 1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. A method for packaging a semiconductor structure, comprising the steps of:
s1, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, the first surface is provided with a plurality of solder bumps, and the second surface is provided with a plurality of metal convex layers;
s2, forming a photoresist layer I on the second surface, wherein the photoresist layer I is provided with a first groove which exposes the top of the metal convex layer;
s3, providing a chip, wherein the chip is provided with a first upper surface and a second lower surface which are opposite, the first upper surface is provided with a plurality of bonding pads, and the upper surface of each bonding pad is correspondingly provided with a conductive connecting layer;
s4, forming a photoresist layer II on the first upper surface and the conductive connecting layer, wherein the photoresist layer II is provided with a second groove exposing the top of the conductive connecting layer;
s5, arranging a conductive sheet in the second groove, wherein one side of the conductive sheet, which is opposite to the conductive connecting layer, is provided with a notch for accommodating the solder bump;
and S6, bonding and connecting the conducting sheet of the chip and the metal convex layer of the substrate by a hot pressing bonding method.
2. The method for packaging a semiconductor structure according to claim 1, wherein the step S5 comprises the steps of:
s5.1, providing solder pads, and respectively placing the solder pads on the second grooves to enable at least two opposite side edges of the solder pads to be lapped on the photoresist layer II on the periphery of the second grooves;
s5.2, placing the conducting sheet on the solder pad, wherein the conducting sheet is positioned right above the second groove, and pressing the conducting sheet downwards to bend the solder pad so as to position and clamp the conducting sheet;
and S5.3, heating the solder pad to enable the solder pad to be molten into solder and to reflow to the bottom of the second groove, and further welding and fixing the conducting sheet and the conducting connecting layer.
3. The method for packaging a semiconductor structure according to claim 1, wherein the step S5 comprises the steps of:
s5.1a, etching a gasket placing groove with the size consistent with that of the solder gasket on the photoresist layer II, wherein the size of the gasket placing groove in the length direction is larger than that of the second groove, or the size of the gasket placing groove in the width direction is larger than that of the second groove;
s5.1b, providing a solder gasket, and placing the solder gasket in the gasket placing groove so that at least two opposite side edges of the solder gasket are lapped on the photoresist layer II where the gasket placing groove is located;
s5.2, placing the conducting sheet on the solder pad, wherein the conducting sheet is positioned right above the second groove, and pressing the conducting sheet downwards to bend the solder pad so as to position and clamp the conducting sheet;
and S5.3, heating the solder pad to enable the solder pad to be molten into solder and to reflow to the bottom of the second groove, and further welding and fixing the conducting sheet and the conducting connecting layer.
4. The method for packaging a semiconductor structure according to claim 2 or 3, wherein the length of the solder pad is smaller than the length of the second groove and the width of the solder pad is larger than the width of the second groove, or the length of the solder pad is larger than the length of the second groove and the width of the solder pad is smaller than the width of the second groove.
5. The method for packaging a semiconductor structure according to claim 2 or 3, wherein the thickness of the solder pad is not greater than 1/3 of the depth of the second groove.
6. The method of claim 1, wherein the length of the conductive strip is less than or equal to the length of the second groove, and the width of the conductive strip is less than or equal to the width of the second groove.
7. The method for packaging a semiconductor structure as recited in claim 6, wherein a total thickness of the metal bump layer, the solder bump and the conductive sheet does not exceed a total thickness of the photoresist layer I and the photoresist layer II, and the photoresist layer II has a thickness higher than a height of the conductive sheet and lower than a total height of the conductive sheet and the solder bump.
8. A semiconductor structure is characterized by comprising at least one semiconductor module, wherein a plurality of semiconductor modules are connected through a substrate in each module; each semiconductor module includes:
the substrate is provided with a first surface and a second surface which are oppositely arranged, the second surface is provided with a plurality of metal convex layers, a photoresist layer I is arranged between every two adjacent metal convex layers, and the upper part of each metal convex layer is provided with a first groove formed by the photoresist layer I and the metal convex layer in a surrounding mode;
the chip is provided with a first upper surface and a second lower surface which are oppositely arranged, a plurality of bonding pads are arranged on the first upper surface, a conductive connecting layer is correspondingly arranged on the upper surface of each bonding pad, a photoresist layer II is arranged between every two adjacent conductive connecting layers, and a second groove surrounded by the photoresist layer II and the conductive connecting layers is arranged at the upper part of each conductive connecting layer;
and the conductive sheet is arranged in the second groove, one side of the conductive sheet, which is back to the conductive connecting layer, is provided with a notch matched with the shape of the solder bump, and the conductive connecting layer is connected with the metal convex layer through the conductive sheet and the solder bump.
9. The semiconductor structure of claim 8, wherein the total thickness of the metal bump layer, the solder bump and the conductive sheet does not exceed the total thickness of the photoresist layer I and the photoresist layer II, and the thickness of the photoresist layer II is greater than the height of the conductive sheet and less than the total height of the conductive sheet and the solder bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210739444.1A CN115020259B (en) | 2022-06-28 | 2022-06-28 | Semiconductor structure and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210739444.1A CN115020259B (en) | 2022-06-28 | 2022-06-28 | Semiconductor structure and packaging method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115020259A true CN115020259A (en) | 2022-09-06 |
| CN115020259B CN115020259B (en) | 2023-08-04 |
Family
ID=83076508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210739444.1A Active CN115020259B (en) | 2022-06-28 | 2022-06-28 | Semiconductor structure and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115020259B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060043364A1 (en) * | 2004-08-26 | 2006-03-02 | Tongbi Jiang | Methods for applying front side and edge protection material to electronic devices at the wafer level, devices made by the methods, and systems including the devices |
| CN104576547A (en) * | 2013-10-25 | 2015-04-29 | Lg伊诺特有限公司 | Printed circuit board and manufacturing method thereof and semiconductor package using the same |
| US20180374780A1 (en) * | 2017-06-27 | 2018-12-27 | Stmicroelectronics S.R.L. | Process for manufacturing a flip chip semiconductor package and a corresponding flip chip package |
| CN110299295A (en) * | 2019-06-03 | 2019-10-01 | 苏州通富超威半导体有限公司 | Bonding semiconductor packaging method |
| US20200373268A1 (en) * | 2019-05-22 | 2020-11-26 | Lenovo (Singapore) Pte. Ltd. | Substrate, electronic substrate, and method for producing electronic substrate |
-
2022
- 2022-06-28 CN CN202210739444.1A patent/CN115020259B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060043364A1 (en) * | 2004-08-26 | 2006-03-02 | Tongbi Jiang | Methods for applying front side and edge protection material to electronic devices at the wafer level, devices made by the methods, and systems including the devices |
| CN104576547A (en) * | 2013-10-25 | 2015-04-29 | Lg伊诺特有限公司 | Printed circuit board and manufacturing method thereof and semiconductor package using the same |
| US20180374780A1 (en) * | 2017-06-27 | 2018-12-27 | Stmicroelectronics S.R.L. | Process for manufacturing a flip chip semiconductor package and a corresponding flip chip package |
| US20200373268A1 (en) * | 2019-05-22 | 2020-11-26 | Lenovo (Singapore) Pte. Ltd. | Substrate, electronic substrate, and method for producing electronic substrate |
| CN110299295A (en) * | 2019-06-03 | 2019-10-01 | 苏州通富超威半导体有限公司 | Bonding semiconductor packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115020259B (en) | 2023-08-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8274143B2 (en) | Semiconductor device, method of forming the same, and electronic device | |
| KR100470897B1 (en) | Method for manufacturing dual die package | |
| JP2795788B2 (en) | Semiconductor chip mounting method | |
| US9520374B2 (en) | Semiconductor device, substrate and semiconductor device manufacturing method | |
| JPH0810716B2 (en) | Electronic package | |
| JP3213703B2 (en) | Reworkable microelectronic multichip module | |
| JPH11121526A (en) | Semiconductor element mounting structure | |
| JP2009246337A (en) | Semiconductor device and method of manufacturing the same | |
| TW506003B (en) | Manufacturing method of a semiconductor device | |
| CN115020259B (en) | Semiconductor structure and packaging method thereof | |
| JPS5873127A (en) | Solder melting connection for ic chip | |
| CN114783883B (en) | Power packaging structure and manufacturing method thereof | |
| JP3847602B2 (en) | Stacked semiconductor device, method for manufacturing the same, motherboard mounted with semiconductor device, and method for manufacturing motherboard mounted with semiconductor device | |
| CN113972183A (en) | Chip, wafer packaging method and packaging structure | |
| JP3686047B2 (en) | Manufacturing method of semiconductor device | |
| JPH10154726A (en) | Semiconductor device and its manufacture | |
| JP4038021B2 (en) | Manufacturing method of semiconductor device | |
| JP6304085B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| JPH06252326A (en) | Multi-terminal component, wiring substrate and packaging structure of multi-terminal component | |
| CN116487344B (en) | Three-dimensional packaging structure and packaging method | |
| JP7227304B2 (en) | Straight wire bonding of silicon die | |
| CN113937010B (en) | Method for manufacturing semiconductor device | |
| JP2000294586A (en) | Semiconductor device and manufacture of the semiconductor device | |
| JPH10242328A (en) | Circuit board, circuit module having the circuit board and electronic equipment having the circuit module | |
| JPH0410635A (en) | Flip chip package mounting |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |