CN115016243B - Linearity enhancement method for random time-to-digital converter - Google Patents
Linearity enhancement method for random time-to-digital converter Download PDFInfo
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Abstract
The invention discloses a linearity enhancement method of a random time-to-digital converter. The method comprises the following steps: defining an input signal coordinate system of the random time-to-digital converter; the method comprises the steps that power supply voltage inside a comparator array is controlled, so that input signals generate a probability distribution curve Group A and a probability distribution curve Group B which are Gaussian functions; translating the probability distribution curve Group A to the right by 2 delta in the direction of an x axis, translating the probability distribution curve Group B to the left by 2 delta in the direction of the x axis, and performing function superposition on data in [ -delta, delta ] to obtain a new distribution function; the signal conversion of the random-type time-to-digital converter is performed based on the new distribution function. The invention greatly improves the linearity of the input signal, avoids the redundant algorithm calibration work and can be integrated on a single chip on a silicon-based standard CMOS process.
Description
Technical Field
The invention belongs to the field of radio frequency/analog integrated circuits, relates to a time-to-digital converter, in particular to a linearity enhancement method of a random time-to-digital converter, and is applied to accurate quantization of time signals.
Background
A Time To Digital Converter (TDC) is a circuit that is widely used in the field of Digital-to-analog conversion to convert a Time signal into a Digital signal, and can be used in medical image detection, automatic test equipment, analog/all-Digital phase-locked loops, high-precision Digital-to-analog converters, transmitters, receivers, radars, high-energy physical and phase control array systems, and the like.
In a conventional time-to-digital converter, a series of delay units generate sequentially increasing delay times, and then a plurality of time comparators compare input signals with delayed signals one by one to determine a time difference between rising edges of two input signals. The thermometer code at the output of the comparator is then encoded into a binary code. The time-to-digital converter has simple structure and easy design, but the quantization precision of the time-to-digital converter depends on the delay time of a gate-level circuit, so that the quantization precision of the time-to-digital converter is low. At present, there are three common time-to-digital converter structures with sub-gate time precision, which are a vernier caliper type time-to-digital converter, a pulse contraction type time-to-digital converter and an interpolation type time-to-digital converter.
The vernier caliper type time-to-digital converter adopts a delay chain consisting of delay units with different delay times, the time resolution precision of the vernier caliper type time-to-digital converter depends on the delay time difference of the two delay units, and the time resolution precision of a sub-gate level can be realized. However, the quantization bit number and the overall delay time are in a trade-off relationship, and high resolution and high operation rate cannot be achieved at the same time. The pulse-shrinking time-to-digital converter is also implemented based on a delay chain, except that the pulse width of the signal is reduced until the pulse disappears after each time the signal passes through a delay unit, so that the time difference is judged. The pulse-shrinking time-to-digital converter can also achieve higher time resolution, but the degree of pulse reduction at a time depends on the logic threshold of the delay unit and is easily affected by process fluctuation. An interpolation type time-to-digital converter sums signals having different rising times to generate a rising edge between two signal rising edges. After multiple interpolations, a series of delay times with high resolution can be generated. However, this structure uses more inverter units, and the circuit has larger power consumption and relatively complex design. In addition, the accuracy of the time-to-digital converters with the above three structures is very dependent on the matching of the circuit, and is easy to generate errors due to process mismatch, which is not favorable for high-accuracy time-to-digital converters.
The random time-to-digital converter utilizes the process mismatch characteristic of the time comparator, namely the characteristic that the judgment result is in Gaussian distribution along with the input time difference, so that the structure has stronger tolerance to process mismatch. The input signal is connected with a certain number of comparator arrays, and the output of the comparator arrays can show approximately linear variation trend when the time difference of the input signal is small, so that finer time resolution can be realized. However, since the gaussian distribution is itself a non-linear probability distribution, the linearity of the conventional random-type time-to-digital converter still needs to be improved.
In summary, a random-type time-to-digital converter is a structure that utilizes process mismatch and can achieve high time resolution, and the linearity thereof needs to be further enhanced.
Disclosure of Invention
The invention aims to solve the problem of low linearity of a random time-to-digital converter in the prior art, and provides a method for enhancing the linearity of the random time-to-digital converter, which has the characteristics of single-chip integration on a silicon-based standard CMOS (complementary metal oxide semiconductor) process, low sensitivity to process fluctuation, high time resolution and high linearity.
The technical content of the invention comprises:
a linearity enhancement method for a random time-to-digital converter includes the steps:
defining a transfer function of a time comparator in the random time-to-digital converter, wherein an x axis of the transfer function is a time difference before an input signal enters the time comparator, and a y axis of the transfer function is probability density of error voltage generated by the comparator;
when the input signal of the time comparator is input to a slope, the transfer function of the comparator is in a probability distribution curve like Gaussian distribution;
controlling the power supply voltage inside the comparator array to enable the probability distribution curve to respectively shift by 2 delta units leftwards or rightwards along the direction of an x axis, so as to respectively obtain two groups of transfer function probability distribution curves Group A and Group B, wherein the linear range of the input signal is [ -delta, delta ], [ delta ] is just the projection point of the probability density peak of the probability distribution curve Group A on the x axis, and [ delta ] is just the projection point of the probability density peak of the probability distribution curve Group B on the x axis;
at the moment, performing function superposition on the data of the probability distribution curve in [ -delta, delta ] to obtain a new transfer function;
the signals of the random-type time-to-digital converter are processed on the basis of the new transfer function.
Further, the method for shifting the probability distribution curve by 2 δ units to the left or the right along the x-axis direction respectively comprises: the exchange of internal supply voltages is performed by means of a random-type time-to-digital converter.
A random-type time-to-digital converter comprising:
the random comparator circuit CELLA is used for enabling a transfer function of an input signal to translate by 2 delta along the direction of an x axis on the basis of original Gaussian distribution to become a probability distribution curve Group A by controlling the internal power supply voltage of a comparator array, wherein the linear range of the input signal is [ -delta, delta ], [ delta ] is a projection point of a probability density peak value of the probability distribution curve Group A on the x axis;
the random comparator circuit CELLB is used for enabling a transfer function of a signal to be translated rightwards by 2 delta along the direction of an x axis on the basis of original Gaussian distribution to become a probability distribution curve GroupB by controlling the internal power supply voltage of a comparator array, wherein the linear range of an input signal is [ -delta, delta ], and delta is a projection point of a probability density peak value of the probability distribution curve GrouB on the x axis;
the encoder is used for performing function superposition on the data in the range of [ -delta, delta ] to obtain a new distribution function; the signal conversion of the random-type time-to-digital converter is performed based on the new distribution function.
Further, the random comparator circuit CELLA and the random comparator circuit CELLB each include: the device comprises an Arbiter array, a gating network, a power supply voltage exchange circuit and a reset calibration circuit;
the gating network is used for inputting the selected signal into the Arbiter array;
the Arbiter array is composed of a plurality of identical comparator units and used for transmitting digital codes to the reset calibration circuit;
the reset calibration circuit is used for carrying out time sequence judgment on the digital code and controlling whether the power supply voltage exchange circuit is started or not according to the output result of the reset calibration circuit;
and the power supply voltage switching circuit is used for feeding back an output result of the reset calibration circuit to the Arbiter array.
Further, the gating network includes: alternative circuit S 1 And one-out-of-two circuit S 2 ；
The alternative circuit S 1 The input terminals of the time difference signal receiving unit respectively receive the left edge S _ INP of the time difference signal actually needed to be calibrated and the left edge-5 ps of the standard time difference;
the alternative circuit S 2 The input ends of the calibration signal receiving unit respectively receive the right edge S _ INN of the time difference signal actually required to be calibrated and the right edge 0ps of the standard time difference;
wherein, according to the level of the gating network control signal Cal, the alternative circuit S 1 And the alternative circuit S 2 The signal TINP and the signal TINN are output as inputs to the Arbiter array, respectively.
Further, the power supply voltage switching circuit includes: alternative circuit S 3 Wherein the alternative circuit S is arranged for each jump of the control signal Swap of the power supply voltage switching circuit 3 Will be exchanged once.
Further, the reset calibration circuit includes: the transmission circuit comprises a transmission gate TG1, a transmission gate TG2 AND a gate logic AND1, wherein the input end of the transmission gate TG2 is connected with the output end of the transmission gate TG1 AND is bridged between the input end AND the output end of the gate logic AND 1;
the input signal reaches the input end of the AND gate logic AND1 through the transmission gate TG1 controlled by the Reset calibration circuit control signal Cal AND the Reset calibration circuit control signal Reset together, AND the control signal Swap output by the AND gate logic AND1 is used for regulating AND controlling the power supply voltage exchange circuit.
The invention has the following advantages and positive effects:
1) The linearity is good: the distribution after calibration is adopted, so that the original linearity is greatly improved, and the method has profound significance to the field of digital-to-analog conversion;
2) Avoiding redundant algorithm calibration work: in the design process, the calibration is directly carried out from the circuit architecture, the complexity of the subsequent algorithm calibration is reduced to the greatest extent, and the realizability is high;
3) The silicon-based CMOS chip can be integrated on a single chip on a silicon-based standard CMOS process, and can also be integrated on a BiCMOS process; the module can be integrated with other circuits and systems on a single chip as a module, the cost is low, and the integration level of the system is greatly improved.
Drawings
Fig. 1 is a probability distribution curve of a time comparator.
Fig. 2 is a graph of the transmission characteristics of an array of N time comparators.
Figure 3 is a graph of the probability distribution curves for two sets of arrays with different offsets and their ensemble.
FIG. 4A is a schematic illustration of a folding of a Group A probability distribution curve.
FIG. 4B is a schematic illustration of a folding of a Group B probability distribution curve.
Figure 4C is the probability distribution curve of the entire array after the folding of the probability distribution curve.
Fig. 5 is an overall structure of a random-type time-to-digital converter demonstrated by the present invention.
Fig. 6A is a circuit configuration diagram of Group a.
Fig. 6B is a circuit configuration diagram of Group B.
Fig. 7 is a control signal timing diagram of the calibration process.
FIG. 8A is the results of a Monte Carlo simulation of an embodiment when not calibrated.
FIG. 8B is the results of Monte Carlo simulations of the calibrated embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is to be understood that the described embodiments are merely specific embodiments of the present invention, rather than all embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
For a random-type time-to-digital converter, an input signal is connected to an input terminal of a comparator array, and since an actual comparator generates random offset due to device mismatch, process, and the like, the offset degree satisfies a gaussian distribution as shown in fig. 1, the average value is 0, and the variance is inversely proportional to the area of the comparator array. Thus, when the input signal is ramped into the comparator, a digital code as shown in fig. 2 will be generated at the output of the comparator array, and then further fitting calibration will be performed on the range of the [ - δ, δ ] interval with the best linearity, but data outside the [ - δ, δ ] interval will be discarded.
Therefore, the invention discloses a linearity enhancement method of a random time-to-digital converter, and the calibration mode of the random time-to-digital comparator is to perform left shift and right shift operations on an original Gaussian function, thereby maximizing the utilization rate of a comparator array as much as possible, and enabling each offset value to be utilized as much as possible so as to increase the linearity. As shown in fig. 3, the gaussian distribution is shifted by δ units to the left and to the right, and then the distribution functions on both sides are superimposed, so that the utilization range of the original gaussian function is increased from the original [ - δ, δ ] to [ -2 δ,2 δ ]. According to the 3 delta principle of normal distribution, the operation can improve the utilization rate of the output data of the comparator from the original 65.26% to 95.44%, so that the fitted function is smoother, and the linearity is greatly improved.
The invention relates to a random time-digital comparator, which has the following specific calibration thought: by controlling the internal supply voltage of the comparator array to generate two sets of probability distribution curves in the form of gaussian functions of Group a and Group B, and then operating on the data on the left half of Group a, as shown in fig. 4A, the data on the left half is collectively shifted by 2 δ units to the dashed right line position by exchanging the internal supply voltage. Similarly, operating on the right data side of Group B as shown in FIG. 4B causes the right data side to shift to the position shown by the left dashed line by swapping its internal supply voltages. Then, the two exchanged functions are superimposed to obtain a new distribution function as shown in fig. 4C, thereby fully utilizing all comparators. Finally, the encoder performs signal conversion of the random-type time-to-digital converter based on the new distribution function.
The invention also discloses a random time-to-digital converter, which can realize the linearity enhancement method on a standard CMOS process or a standard BiCMOS process, and the specific structure of the random time-to-digital converter is shown in figures 5, 6A, 6B and 7.
As shown in fig. 5, the digital-to-time converter includes: a random comparator circuit Group a that outputs a <63 > digital code and a random comparator circuit Group B that outputs a <127 > < 64> digital code; the random comparator circuit Group A for outputting <63 > digital codes and the random comparator circuit Group B for outputting <127 > digital codes are both composed of an Arbiter array, a gating network, a power supply voltage exchange circuit, a reset calibration circuit and an addition operation circuit, wherein the Arbiter array is composed of 64 completely identical comparator units, the gating network is controlled by a clock, signals selected by the gating network are used as input to the inside of the Arbiter array, the Arbiter array transmits the obtained 64-bit digital codes to the reset calibration circuit, the reset calibration circuit carries out further time sequence judgment, whether the power supply voltage exchange circuit is started or not is controlled according to different output results, and then the power supply voltage exchange circuit feeds the output results back to the Arbiter array to complete a complete digital time sequence period and outputs the 64-bit digital codes. Finally, the two 64-bit digital codes are added through the encoder to form a 128-bit output.
The main body part of the gating network consists of two alternative circuits and a control signal Cal, the left and right edges S _ INP and S _ INN of a time difference signal which needs to be actually calibrated and the left and right edges-5 ps and 0ps of a standard time difference are respectively connected to the input end of the alternative circuit, and corresponding output signals TINP and TINN are obtained according to the level of the control signal Cal and are used as the input of the Arbiter array.
The power supply voltage exchange circuit is composed of an alternative circuit and a control signal Swap, and input signals VDD1 and VDD2 of the alternative circuit are exchanged once when the Swap signal jumps once.
The reset calibration circuit is shown in the dotted line blocks of fig. 6A AND 6B, AND includes a transmission gate TG1, a transmission gate TG2, AND gate logic AND1, AND a control signal
Cal, reset and Swap. The input signal passes through a transmission gate TG1 controlled by a signal Cal AND a control signal Reset to reach the input end of an AND gate logic AND1, the input end of a transmission gate TG2 is connected with the output end of TG1 AND is bridged between the input end AND the output end of AND1AND finally, outputting a control signal Swap through an AND gate AND1 to regulate AND control the power supply voltage exchange circuit.
FIG. 7 is a timing simulation diagram of the present invention. As can be seen from the figure, when Cal =1, reset =0, the circuit enters the stage (1), the gating network in Group a outputs-5ps, 0ps to the inputs TINP, TINN of arbiters respectively, at this time, since the Reset signal is 0, the swap signal is also 0, vdd1, VDD2 are not exchanged, and the Arbiter array generates gaussian distribution output with left-right symmetry; then Cal =1, reset =1, the circuit enters the evaluation stage as shown in (2), at this time, since the reset signal is 1, the size of the Swap signal depends ON the ON end of Group a and the OP end of Group B, and if the ON end of Group a and the OP end of Group B are 1, the Swap signal is set to 1, vdd1 is exchanged with VDD2, otherwise, no Swap is performed; then, cal =0, reset =1, the circuit enters (3) stage, the gating network outputs S _ INP and S _ INN to the input terminals TINP and TINN of the Arbiter array, at this time, because the reset signal is 1 and the swap signal is 1, the power supply voltage switching circuit does not jump, the circuit enters into latch state, and the value is not changed.
Fig. 8A and 8B are graphs showing actual simulation results of the present invention, wherein the two graphs respectively simulate the simulation results before and after calibration when the monte carlo point number is 10. It can be seen that the curve is smoother and more linear than without calibration, and the corresponding integrated non-linearity INL is reduced by 0.4 LSB.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but the equivalent variations of the present invention can be made by those skilled in the art, and the present invention should be included in the scope of the claims.
Claims (6)
1. A linearity enhancement method of a random time-to-digital converter comprises the following steps:
defining a transfer function of a time comparator in the random time-to-digital converter, wherein an x axis of the transfer function is a time difference before an input signal enters the time comparator, and a y axis of the transfer function is probability density of error voltage generated by the comparator;
when the input signal of the time comparator is input to a slope, the transfer function of the comparator is in a probability distribution curve like Gaussian distribution;
controlling the power supply voltage inside the comparator array to enable the probability distribution curve to respectively shift by 2 delta units leftwards or rightwards along the direction of an x axis, so as to respectively obtain two groups of transfer function probability distribution curves Group A and Group B, wherein the linear range of the input signal is [ -delta, delta ], [ delta ] is just the projection point of the probability density peak of the probability distribution curve Group A on the x axis, and [ delta ] is just the projection point of the probability density peak of the probability distribution curve Group B on the x axis;
at the moment, performing function superposition on the data of the probability distribution curve in [ -delta, delta ] to obtain a new transfer function;
the signals of the random-type time-to-digital converter are processed on the basis of the new transfer function.
2. A random-type time-to-digital converter implementing the linearity enhancement method of claim 1, comprising:
the random comparator circuit CELLA is used for enabling a transfer function of an input signal to translate by 2 delta along the direction of an x axis on the basis of original Gaussian distribution to become a probability distribution curve Group A by controlling the internal power supply voltage of a comparator array, wherein the linear range of the input signal is [ -delta, delta ], [ delta ] is a projection point of a probability density peak value of the probability distribution curve Group A on the x axis;
the random comparator circuit CELLB is used for enabling a transfer function of a signal to be translated rightwards by 2 delta along the direction of an x axis on the basis of original Gaussian distribution to become a probability distribution curve GroupB by controlling the internal power supply voltage of a comparator array, wherein the linear range of an input signal is [ -delta, delta ], and delta is a projection point of a probability density peak value of the probability distribution curve GrouB on the x axis;
the encoder is used for performing function superposition on the data in the range of [ -delta, delta ] to obtain a new distribution function; the signal conversion of the random-type time-to-digital converter is performed based on the new distribution function.
3. A random-type time-to-digital converter as claimed in claim 2, wherein said random comparator circuit CELLA and said random comparator circuit CELLB each comprise: the device comprises an Arbiter array, a gating network, a power supply voltage exchange circuit and a reset calibration circuit;
the gating network is used for inputting the selected signal into the Arbiter array;
the Arbiter array is composed of a plurality of identical comparator units and used for transmitting digital codes to the reset calibration circuit;
the reset calibration circuit is used for carrying out time sequence judgment on the digital code and controlling whether the power supply voltage exchange circuit is started or not according to the output result of the reset calibration circuit;
and the power supply voltage switching circuit is used for feeding back an output result of the reset calibration circuit to the Arbiter array.
4. The random-type time-to-digital converter of claim 3, wherein said gating network comprises: alternative circuit S 1 And alternative circuit S 2 ；
The alternative circuit S 1 The input terminals of the time difference signal receiving unit respectively receive the left edge S _ INP of the time difference signal actually needed to be calibrated and the left edge-5 ps of the standard time difference;
the alternative circuit S 2 The input ends of the calibration signal receiving unit respectively receive the right edge S _ INN of the time difference signal actually required to be calibrated and the right edge 0ps of the standard time difference;
wherein, according to the level of the gating network control signal Cal, the alternative circuit S 1 And the alternative circuit S 2 The signal TINP and the signal TINN are output as inputs to the Arbiter array, respectively.
5. The random-type time-to-digital converter of claim 3 wherein said supply voltage switching circuit comprises: alternative circuit S 3 Wherein the alternative circuit S is arranged for each jump of the control signal Swap of the power supply voltage switching circuit 3 Will be exchanged once.
6. The random-type time-to-digital converter of claim 3 wherein said reset calibration circuit comprises: the transmission circuit comprises a transmission gate TG1, a transmission gate TG2 AND a gate logic AND1, wherein the input end of the transmission gate TG2 is connected with the output end of the transmission gate TG1 AND is bridged between the input end AND the output end of the gate logic AND 1;
the input signal reaches the input end of the AND gate logic AND1 through the transmission gate TG1 controlled by the Reset calibration circuit control signal Cal AND the Reset calibration circuit control signal Reset together, AND the control signal Swap output by the AND gate logic AND1 is used for regulating AND controlling the power supply voltage exchange circuit.
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| CN102291138B (en) * | 2011-07-08 | 2013-11-27 | 东南大学 | Stochastic time-digital converter |
| US10061272B2 (en) * | 2016-06-12 | 2018-08-28 | Board Of Regents, The University Of Texas System | Pipelined SAR ADC using comparator as a voltage-to-time converter with multi-bit second stage |
| CN110880934B (en) * | 2019-12-06 | 2023-05-26 | 清华大学深圳国际研究生院 | Successive approximation type analog-to-digital converter and calibration method |
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| WO2001069328A2 (en) * | 2000-03-17 | 2001-09-20 | Vector 12 Corporation | High resolution time-to-digital converter |
| CN101753142A (en) * | 2008-12-01 | 2010-06-23 | 三星电子株式会社 | Time-to-digital convertoer and all-digital phase locked loop |
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