CN115000011A - 一种孔洞taper处金属偏薄或断线的改善方法 - Google Patents

一种孔洞taper处金属偏薄或断线的改善方法 Download PDF

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CN115000011A
CN115000011A CN202210722954.8A CN202210722954A CN115000011A CN 115000011 A CN115000011 A CN 115000011A CN 202210722954 A CN202210722954 A CN 202210722954A CN 115000011 A CN115000011 A CN 115000011A
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潜垚
李澈
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Fujian Huajiacai Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

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Abstract

本发明提供一种孔洞taper处金属偏薄或断线的改善方法,包括如下步骤:步骤S1、在基材上镀上第一金属膜层;步骤S2、沉积绝缘层,并进行图案化,得到带有孔洞的绝缘层;步骤S3、进行第一次PVD沉积得到第二金属膜层;步骤S4、对孔洞外的绝缘层上的第二金属膜层进行研磨,得到平整的绝缘层;步骤S5、进行电化学沉积,使得孔洞内第二金属膜层上覆盖一第三金属膜层;步骤S6、进行第二次PVD沉积得到第四金属膜层。采用本发明的工艺流程,可有效消除现有工艺中孔洞梯度面金属层过薄或出现断裂等问题,提高产品质量。

Description

一种孔洞taper处金属偏薄或断线的改善方法
技术领域
本发明涉及TFT技术领域,尤其涉及一种LCD Array面板上孔洞taper处金属偏薄或断线的改善方法。
背景技术
目前竞争最激烈的平板显示器有四个品种:1.场致发射平板显示器(FED);2.等离子体平板显示器(PDP);3.有机薄膜电致发光器(OLED);4.薄膜晶体管液晶平板显示器(TFT-LCD)。其中,液晶平板显示器,特别TFT-LCD,是目前唯一在亮度、对比度、功耗、寿命、体积和重量等综合性能上全面赶上和超过CRT的显示器件,它的性能优良、大规模生产特性好,自动化程度高,原材料成本低廉,发展空间广阔。TFT是在玻璃或塑料基板等非单晶片上(当然也可以在晶片上)通过溅射、化学沉积工艺形成制造电路必需的各种膜,通过对膜的加工制作大规模半导体集成电路(LSIC)。
在集成电路制作过程中,为了在LCD Array面板上制作足够的金属内连线及增加电路的集成度,大多采用多层内连线的立体架构方式,以完成各个电路的传导。因此,在导电层(金属层)间需要用介电层(绝缘层)来隔离各金属层,避免电路间非预期的导通,那为了预期的导通则会在绝缘层进行打洞用以连接上下金属层。现有的孔洞处理是直接在带有孔洞的板上进行PVD沉积金属膜层。这样做的结果是PVD沉积金属膜层过程中,由于一些孔洞存在倾斜面,金属的阶梯覆盖能力差,就容易出现元件断线或是阻抗的增加等情况,从而影响产品质量。
发明内容
本发明要解决的技术问题,在于提供一种孔洞taper处金属偏薄或断线的改善方法,可有效消除现有工艺中孔洞梯度面金属层过薄或出现断裂等问题。
本发明是这样实现的:一种孔洞taper处金属偏薄或断线的改善方法,包括如下步骤:
步骤S1、在基材上镀上第一金属膜层;
步骤S2、沉积绝缘层,并进行图案化,得到带有孔洞的绝缘层;
步骤S3、进行第一次PVD沉积得到第二金属膜层;
步骤S4、对孔洞外的绝缘层上的第二金属膜层进行研磨,得到平整的绝缘层;
步骤S5、进行电化学沉积,使得孔洞内第二金属膜层上覆盖一第三金属膜层;
步骤S6、进行第二次PVD沉积得到第四金属膜层。
进一步的,各个金属膜层为相同材质的金属层的叠加或不同材质的金属层的叠加组合。
进一步的,所述第一次PVD沉积得到的第二金属膜层的厚度为800A~5000A。
进一步的,所述第二次PVD沉积得到的第四金属膜层的厚度为800A~5000A。
进一步的,所述步骤S4中的绝缘层为平整的有机层或TEOS层或SiNx层或SiOx层或SiOxNx层或多膜层复合膜层,且厚度为2000A~10000A。
本发明具有如下优点:通过设置平坦的绝缘层以及磨平孔洞外层表面金属层之后,利用电化学沉积对孔洞内金属层进行适当加厚,之后再进行一次PVD沉积,有效改善孔洞内金属厚度,降低阻抗及量损,提高产品整体质量。
附图说明
下面参照附图结合实施例对本发明作进一步的说明。
图1为本发明方法执行流程图。
图2为本发明一具体实施例中采用本发明工艺执行得到的各步骤的效果示意图。
图3为本发明另一具体实施例中采用本发明工艺流程处理后得到的产品效果示意图。
图4为本发明又一具体实施例中采用本发明工艺流程处理后得到的产品效果示意图。
具体实施方式
如图1和图2所示,本申请一种孔洞taper处金属偏薄或断线的改善方法,包括如下步骤:
步骤S1、在基材上镀上第一金属膜层;
步骤S2、沉积绝缘层,并进行图案化,得到带有孔洞的绝缘层;
步骤S3、进行第一次PVD沉积得到第二金属膜层;
步骤S4、对孔洞外的绝缘层上的第二金属膜层进行研磨,得到平整的绝缘层;
步骤S5、进行电化学沉积,使得孔洞内第二金属膜层上覆盖一第三金属膜层;
步骤S6、进行第二次PVD沉积得到第四金属膜层。
较佳的,各个金属膜层为相同材质的金属层的叠加或不同材质的金属层的叠加组合。即各层金属材料不设限,均可为Au,Ag,Al,Cu,Mo,Ti等中任一一种,所有金属膜层可以是同一种金属层,比如图2中的各个M层均可以为Cu,或为不同材质的金属层的叠加组合,例如ITO/Ag/ITO,Mo/Al/Mo。
较佳的,所述第一次PVD沉积得到的第二金属膜层的厚度为800A~5000A。
较佳的,所述第二次PVD沉积得到的第四金属膜层的厚度为800A~5000A。
较佳的,所述步骤S4中的绝缘层为平整的有机层或TEOS层或SiNx层或SiOx层或SiOxNx层或多膜层复合膜层,且厚度为2000A~10000A,具体厚度依照相关绝缘层材料及其对应电容需求。
本发明工艺适用于带有孔洞的其它产品结构中。例如图3和图4所示产品中其中的M21层和M3层的铺设方式同样可以通过本发明的方法,在平坦层或绝缘层图案化后出现孔洞,先进行一次PVD沉积金属层,通过磨平处理之后再进行电化学沉积,增加相应金属层的厚度,之后再进行第二次PVD沉积,使得孔洞内斜面金属层的厚度达到需要的厚度,同时不影响外表层金属厚度,从而避免taper处金属偏薄或断线的现象。其中,图3和图4中的glass为玻璃层,SE为有源层,有源层可以为IGZO或者a-Si,或者LTPS(单晶硅)等半导体材料,图3中的金属层M21、图4中的金属层M0、金属层M1、金属层M2、金属层M3的材料不设限,即可为Au,Ag,Al,Cu,Mo,Ti等或为其叠加的任意组合,且金属层M0搭接在金属层M2上,图4中的未标符号的层均属于绝缘层。
本发明上述技术方案至少具备如下优点:设置平坦层或绝缘层以及磨平孔洞外层表面的金属层,利用电化学沉积对孔洞内金属层进行适当加厚,之火再进行一次PVD沉积,同时不影响孔洞外金属层的应有厚度,本发明通过改善孔洞内金属厚度,降低阻抗及量损,提高产品整体质量。
虽然以上描述了本发明的具体实施方式,但是熟悉本技术领域的技术人员应当理解,我们所描述的具体的实施例只是说明性的,而不是用于对本发明的范围的限定,熟悉本领域的技术人员在依照本发明的精神所作的等效的修饰以及变化,都应当涵盖在本发明的权利要求所保护的范围内。

Claims (5)

1.一种孔洞taper处金属偏薄或断线的改善方法,其特征在于:包括如下步骤:
步骤S1、在基材上镀上第一金属膜层;
步骤S2、沉积绝缘层,并进行图案化,得到带有孔洞的绝缘层;
步骤S3、进行第一次PVD沉积得到第二金属膜层;
步骤S4、对孔洞外的绝缘层上的第二金属膜层进行研磨,得到平整的绝缘层;
步骤S5、进行电化学沉积,使得孔洞内第二金属膜层上覆盖一第三金属膜层;
步骤S6、进行第二次PVD沉积得到第四金属膜层。
2.根据权利要求1所述的一种孔洞taper处金属偏薄或断线的改善方法,其特征在于:各个金属膜层为相同材质的金属层的叠加或不同材质的金属层的叠加组合。
3.根据权利要求1所述的一种孔洞taper处金属偏薄或断线的改善方法,其特征在于:所述第一次PVD沉积得到的第二金属膜层的厚度为800A~5000A。
4.根据权利要求1所述的一种孔洞taper处金属偏薄或断线的改善方法,其特征在于:所述第二次PVD沉积得到的第四金属膜层的厚度为800A~5000A。
5.根据权利要求1所述的一种孔洞taper处金属偏薄或断线的改善方法,其特征在于:所述步骤S4中的绝缘层为平整的有机层或TEOS层或SiNx层或SiOx层或SiOxNx层或多膜层复合膜层,且厚度为2000A~10000A。
CN202210722954.8A 2022-06-24 2022-06-24 一种孔洞taper处金属偏薄或断线的改善方法 Pending CN115000011A (zh)

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