CN114999943B - Interconnection method of microstructure array and device bonding structure - Google Patents

Interconnection method of microstructure array and device bonding structure Download PDF

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Publication number
CN114999943B
CN114999943B CN202210411908.6A CN202210411908A CN114999943B CN 114999943 B CN114999943 B CN 114999943B CN 202210411908 A CN202210411908 A CN 202210411908A CN 114999943 B CN114999943 B CN 114999943B
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layer
self
filler metal
brazing filler
multilayer film
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CN114999943A (en
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何锦华
王兢
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Jiangsu Borui Photoelectric Co ltd
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Jiangsu Borui Photoelectric Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Ceramic Products (AREA)
  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The invention provides an interconnection method of a microstructure array and a device bonding structure, which comprises the following steps: selecting a first substrate layer; spin-coating a first photoresist layer on the first substrate layer, and patterning the first photoresist layer; depositing a first solder layer on the first substrate layer; removing the first photoresist layer; selecting a second substrate layer; spin-coating a second photoresist layer on the second substrate layer, and patterning the second photoresist layer; depositing a second solder layer on the second substrate layer; depositing a self-propagating multilayer film on the second substrate layer; removing the second photoresist layer; aligning and assembling the first brazing filler metal layer and the second brazing filler metal layer; and igniting the self-propagating multilayer film to finish the connection of the first brazing filler metal layer and the second brazing filler metal layer. The invention realizes interconnection of the micro-size structural array through self-propagating micro-brazing, improves the assembly precision, reduces the false soldering rate and improves the reliability; by setting the melting point gradient distribution of the self-propagating brazing film, the problem of damage to the chip caused by the welding temperature in the prior art is solved.

Description

Interconnection method of microstructure array and device bonding structure
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a microstructure array interconnection method and a device bonding structure applying a self-propagating brazing film.
Background
In device fabrication, an insulating layer, a semiconductive layer, and a conductive layer are all formed on a substrate. These layers are patterned to create features and voids. The minimum dimension of the feature size (F) of the features and voids is dependent on the resolution of the lithography system. The features and voids are patterned to form devices such as transistors, capacitors, and resistors. These devices are then interconnected to achieve the desired electrical function, resulting in an Integrated Circuit (IC).
Device interconnects include depositing a layer of metal, such as Aluminum (AL), tungsten (W), or copper (Cu), or conductive material over a substrate containing the device and patterning to form conductors or "lines" interconnecting the devices as desired.
When the microstructure array is assembled or the bonding structure of the device is adopted, the metal layers are required to be connected in a welding mode, and due to the small size and high alignment precision requirement, the proportion of the virtual welding is high, and a novel microstructure array interconnection method or a novel bonding structure is required to be provided, so that the virtual welding rate is reduced, and the reliability of the product is improved.
Disclosure of Invention
The invention solves the technical problem of the background technology and provides an interconnection method of a microstructure array. Specifically, the technical scheme of the invention is as follows:
a method of interconnecting a microstructure array, comprising the steps of:
selecting a first substrate layer;
spin-coating a first photoresist layer on the first substrate layer, and patterning the first photoresist layer;
depositing a first solder layer on the first substrate layer;
removing the first photoresist layer;
selecting a second substrate layer;
spin-coating a second photoresist layer on the second substrate layer, and patterning the second photoresist layer;
depositing a second solder layer on the second substrate layer;
depositing a self-propagating multilayer film on the second substrate layer;
removing the second photoresist layer;
aligning and assembling the first brazing filler metal layer and the second brazing filler metal layer;
and igniting the self-propagating multilayer film to finish the connection of the first brazing filler metal layer and the second brazing filler metal layer.
Optionally, the self-propagating multilayer film comprises Ti-Al, al-Ni, ti-Ni, ni-Si, Nb-Si、 Al-CuO x One or more of Al-Pt films.
Optionally, the melting point of the first brazing filler metal layer and/or the second brazing filler metal layer is lower than the instantaneous reaction maximum temperature of the self-propagating multilayer film.
Optionally, the melting point of the first brazing filler metal layer and/or the second brazing filler metal layer is distributed in a gradient manner in a decreasing direction along a thickness direction away from the self-propagating multilayer film.
Optionally, the material of the first solder layer and/or the second solder layer includes tin-based, gold-based, lead-based, silver-based, zinc-based, bismuth-based, indium-based, aluminum-based or copper-based alloy.
Optionally, the material of the first solder layer and/or the second solder layer includes one or two of binary or ternary tin base, binary or ternary zinc base, binary or ternary gold base, binary or ternary bismuth base alloy.
Optionally, the melting point range of the contact area of the first brazing filler metal layer and/or the second brazing filler metal layer and the self-propagating multilayer film is 1100-400 ℃; the melting point range of the welding interface area of the first brazing filler metal layer and/or the second brazing filler metal layer is 100-400 ℃.
Optionally, the melting point range of the contact area of the first brazing filler metal layer and/or the second brazing filler metal layer and the self-propagating multilayer film is 1064 ℃ to 420 ℃, and the melting point range of the welding interface area of the first brazing filler metal layer and/or the second brazing filler metal layer is 196 ℃ to 381 ℃.
Alternatively, dry deposition or wet deposition is used to control the composition of the first and/or second solder layers to be graded in a direction away from the thickness of the self-propagating multilayer film, so as to obtain a graded distribution in which the melting point is reduced in a direction away from the thickness of the self-propagating multilayer film.
Optionally, the dry deposition includes setting deposition rates of different targets; or, the wet deposition comprises the steps of setting the concentration of a metal ion source in the electroplating liquid component or setting electroplating process parameters.
Optionally, the method further comprises the step of depositing a seed layer on the first substrate layer and on the second substrate layer.
The invention also provides an adhesive structure of the device, which comprises the device, the gasket and the bottom plate which are stacked in sequence, wherein:
the pad is arranged between the thermosensitive device and the bottom plate and is respectively bonded with the device and the bottom plate through a solder layer;
the solder layer comprises a first solder layer, a self-propagating multilayer film and a second solder layer which are stacked in sequence.
Optionally, the device comprises a laser diode.
Alternatively, the self-propagating multilayer film comprises Ti-Al, al-Ni, ti-Ni, ni-Si, nb-Si, al-CuO x One or more of Al-Pt films; and/or the number of the groups of groups,
the first brazing filler metal layer and/or the second brazing filler metal layer are/is made of tin-based, gold-based, lead-based, silver-based, zinc-based, bismuth-based, indium-based, aluminum-based or copper-based alloys;
and/or the number of the groups of groups,
the first solder layer and/or the second solder layer are/is made of one or two of binary or ternary tin base, binary or ternary zinc base, binary or ternary gold base and binary or ternary bismuth base alloy.
Optionally, the melting point of the first brazing filler metal layer and/or the second brazing filler metal layer is lower than the instantaneous reaction maximum temperature of the self-propagating multilayer film.
Optionally, the melting point of the first brazing filler metal layer and/or the second brazing filler metal layer is distributed in a gradient manner in a decreasing direction along a thickness direction away from the self-propagating multilayer film.
Optionally, the melting point range of the contact area of the first brazing filler metal layer and/or the second brazing filler metal layer and the self-propagating multilayer film is 1100-400 ℃; the melting point range of the welding interface area of the first brazing filler metal layer and/or the second brazing filler metal layer is 100-400 ℃.
Compared with the prior art, the invention has the beneficial effects that:
the invention realizes the interconnection and the device bonding of the micro-size structure array through the self-propagating micro-brazing, provides a new thought of the interconnection or the device bonding of the micro-structure array, improves the assembly precision, reduces the false soldering rate and improves the reliability; meanwhile, the problem of damage to the chip due to the welding temperature in the prior art is solved by setting gradient distribution of the melting point of the self-propagating brazing film.
Drawings
FIG. 1 is a schematic diagram of a method for interconnecting a microstructure array according to an embodiment of the invention;
FIG. 2 is a schematic illustration of a self-propagating brazing film according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a welding temperature distribution corresponding to a self-propagating brazing film according to an embodiment of the present invention;
fig. 4 is a schematic view of a device bonding structure according to an embodiment of the present invention.
Detailed Description
The invention and the method of practicing the same may be better understood by reference to the following detailed description of exemplary embodiments and the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Like reference numerals may refer to like elements throughout. In the drawings, the thickness of layers and regions may be exaggerated for clarity.
Example 1
A method of microstructure interconnection, as shown in fig. 1 and 3, comprising the steps of:
selecting a first substrate layer 1; the first base layer 1 comprises a wafer on which IC or MEMS devices have been formed;
spin-coating a first photoresist layer 2 on the first substrate layer 1, and patterning the first photoresist layer 2; the first photoresist layer 2 may be various photoresist layers applicable to the semiconductor field.
Depositing a first solder layer 3 on the first substrate layer 1; wherein further comprising sputtering a seed layer 301 on the first base layer 1 in advance; the deposition of the first solder layer 3 uses a general method of metal deposition.
Removing the first photoresist layer 2; obtaining a first substrate layer 1 with a first solder layer 3
Selecting a second substrate layer 4; the second base layer 4 may also be a wafer on which circuits or structures have been formed;
spin-coating a second photoresist layer 5 on the second substrate layer 4, and patterning the second photoresist layer 5;
according to the same method, a second solder layer 6 is deposited on said second substrate layer 4; wherein further comprising sputtering a seed layer 601 on the second base layer 4 in advance; the deposition of the second solder layer 6 uses a general method of metal deposition.
Depositing a self-propagating multilayer film 7 on the second substrate layer; it is of course also possible to deposit a self-propagating multilayer film 7 on the first substrate layer;
removing the second photoresist layer 5;
aligning and assembling the first brazing filler metal layer and the second brazing filler metal layer; the assembly can be completed by adopting an assembly fixture;
and igniting the self-propagating multilayer film to finish the connection of the first brazing filler metal layer 3 and the second brazing filler metal layer 6.
Further, as shown in fig. 2, the self-propagating brazing film includes a first brazing material layer 3, a self-propagating multilayer film 7, and a second brazing material layer 6 stacked in this order, the self-propagating multilayer film 7 includes one or more of Ti-Al, al-Ni, ti-Ni, ni-Si, nb-Si, al-CuOx, and Al-Pt thin films, wherein a melting point of the first brazing material layer 3 and/or the second brazing material layer 6 is lower than a transient reaction maximum temperature of the self-propagating multilayer film 7.
The self-propagating multilayer film 7 is, for example, an ABAB periodic structure, the thickness of a single layer is 10-100nm, the total thickness is 10-2000 mu m, the reaction speed of the self-propagating multilayer film is inversely proportional to the diffusion distance, namely, the smaller the thickness of the single layer is, the faster the combustion speed is, for example, an Al-Ni system, the reaction speed is 2-10 m/s, and the highest reaction temperature is above 1700 ℃.
The self-propagating multilayer film 7, for example, is a composite multilayer structure formed by alternately depositing two nanoscale thicknesses of elements having negative enthalpy of mixing (negative enthalpy of mixing) (e.g., one or more of Ti-Al, al-Ni, ti-Ni, ni-Si, nb-Si, al-CuOx, al-Pt films). The composite multilayer film material can release negative enthalpy heat (such as Ni-Al is 1381J/g) after being ignited, and can reach extremely high heating and quenching rates (100-K/s) instantaneously (within tens of milliseconds), so that local temperature of about 1500 ℃ is formed. The temperature at the final chip area or substrate can be less than 100 c, as shown in fig. 3, via the transfer of the first and second solder layers of the melting point gradient profile.
Further, the melting point of the first solder layer 3 and/or the second solder layer 6 is in a gradient distribution decreasing in a thickness direction away from the self-propagating multilayer film 7. The first brazing filler metal layer 3 and the second brazing filler metal layer 6 provided by the invention are solderable metals with melting points lower than the instantaneous local highest temperature of the combustion reaction of the self-propagating multilayer film at the far self-propagating multilayer film (namely, at the side close to the first substrate or the second substrate), and the materials of the first brazing filler metal layer and/or the second brazing filler metal layer comprise tin-based, gold-based, lead-based, silver-based, zinc-based, bismuth-based, indium-based, aluminum-based or copper-based alloys. In this embodiment, the first solder layer and the second solder layer are selected from the above metal base, so that adverse effects on the first substrate or the second substrate caused by the reaction temperature of the self-propagating multilayer film can be effectively avoided.
As a further preferred embodiment of the present invention, in order to further improve the solderability, the first solder layer and the second solder layer proposed by the present invention are, in a thickness direction away from the self-propagating multilayer film, that is: the melting point of the self-propagating multilayer film is gradually and gradually decreased from the near self-propagating multilayer film (on the side of the self-propagating multilayer film) to the far self-propagating multilayer film (on the side of the device/substrate). In the present invention, the melting point is a gradually decreasing gradient distribution, including a smoothly decreasing gradient distribution, such as a linearly decreasing gradient distribution or a convex/concave gradient distribution, and also including a stepwise decreasing gradient distribution.
The first solder layer and the second solder layer according to the invention are, for example, distributed in a component gradient in the thickness direction, so that their melting points are also distributed in a gradient. Specifically, a gradient of decreasing melting point is presented from one side of the self-propagating multilayer film to one side of the device/substrate, the lowest point of the melting point gradient is lower than the highest point which can be borne by the temperature-sensitive device (chip), and the highest point is lower than the highest instantaneous temperature of the self-propagating brazing so as to ensure that the welding spots are fully melted and the safety of the device between brazing process windows.
The transient response temperature profile of the self-propagating brazing film is shown in fig. 3. It can be seen from the temperature profile that the entire self-propagating brazing film produces a central high temperature and steep temperature region facing the adjacent region, leaving a very small heat affected zone (20-100 microns in depth). Thus, the thermal adaptation of the solder to self-propagating multilayer films and chips/devices/substrates can be greatly improved, as well as the thermal reliability of the entire solder joint.
Further, the first solder layer and/or the second solder layer are/is made of one or two of binary or ternary zinc-based alloy and binary or ternary bismuth-based alloy;
further, the melting point range of the contact area of the first brazing filler metal layer and/or the second brazing filler metal layer and the self-propagating multilayer film is 1100-400 ℃; the melting point range of the welding interface area of the first brazing filler metal layer and/or the second brazing filler metal layer is 250-380 ℃.
Further, the melting point range of the contact area of the first brazing filler metal layer and/or the second brazing filler metal layer and the self-propagating multilayer film is 1064 ℃ to 420 ℃, and the melting point range of the welding interface area of the first brazing filler metal layer and/or the second brazing filler metal layer is 196 ℃ to 381 ℃.
In particular, for high temperature or high power devices, the first and/or said second solder layer has a melting point in the range of 250 ℃ to 385 ℃, preferably 271 ℃ to 381 ℃, at the far self-propagating multilayer film, such as the contact area with the substrate, i.e. the welded interface area.
The gradient distribution gradually decreasing can be prepared by adopting dry deposition or wet deposition; when dry deposition is adopted, the different gradient distribution is realized by uniformly, variably or stepwise changing the deposition rates of different targets; when wet deposition is adopted, the electroplating process parameters are changed through uniform speed or variable speed to realize smooth decreasing gradient distribution, and the electroplating liquid components of different electroplating baths in the gantry line are arranged to realize stepped decreasing gradient distribution.
In addition, as another embodiment of the present invention, one of the first solder layer and the second solder layer may be selected as required, and the melting point of the one of the first solder layer and the second solder layer is set to be lower than the instantaneous reaction maximum temperature of the self-propagating multilayer film, for example, from the aspect of saving cost, if the substrate can withstand high temperature, the safety of the device between the brazing process windows is only ensured.
Example 2
As shown in fig. 4, this embodiment proposes that the self-propagating micro-brazing implements bonding between a device (for example, inP laser diode) or an IGBT device and a metallized ceramic carrier, so as to effectively solve the failure risk of the existing brazing system, for example, nano-sintering silver paste or solder paste, and due to its thixotropic property, poor coplanarity, that is, uneven thickness of a bonding line (bonding line), is easy to occur when the device is bonded, so that bonding failure occurs at a thinner portion of the bonding line due to stress concentration, while the self-propagating nano-film has excellent flatness and rapid welding performance, which can effectively avoid the risk and ensure coplanarity, and meanwhile, the damage to the thermosensitive device can be avoided by a smaller heat affected zone. Based on the application characteristics of the brazing, the final electrical performance and the thermal management characteristics of the integrated power module can be subjected to targeted bonding optimization, so that the light weight and the miniaturization of the module device are realized.
The device structure typically includes a device, a spacer, and a base plate stacked in sequence, wherein:
the pad is arranged between the device and the bottom plate and is respectively bonded with the device and the bottom plate through a solder layer;
the solder layer comprises a first solder layer, a self-propagating multilayer film and a second solder layer which are stacked in sequence.
Optionally, the device comprises a laser diode or an IGBT chip; the material selection and structure of the first solder layer, the self-propagating multilayer film, and the second solder layer are described in embodiment 1, and are not repeated here.
It is to be understood that the above-described embodiments are merely illustrative of the application of the principles of the present invention, but are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims (14)

1. A method of interconnecting a microstructure array, comprising the steps of:
selecting a first substrate layer;
spin-coating a first photoresist layer on the first substrate layer, and patterning the first photoresist layer;
depositing a first solder layer on the first substrate layer;
removing the first photoresist layer;
selecting a second substrate layer;
spin-coating a second photoresist layer on the second substrate layer, and patterning the second photoresist layer;
depositing a second solder layer on the second substrate layer;
depositing a self-propagating multilayer film on the second substrate layer;
removing the second photoresist layer;
aligning and assembling the first brazing filler metal layer and the second brazing filler metal layer;
igniting the self-propagating multilayer film to finish the connection of the first brazing filler metal layer and the second brazing filler metal layer; wherein,
the melting point of the first brazing filler metal layer and/or the second brazing filler metal layer is distributed in a gradient manner in a decreasing manner along the thickness direction far away from the self-propagating multilayer film.
2. The method of interconnecting a microstructure array of claim 1, wherein the self-propagating multilayer film comprises one or more of Ti-Al, al-Ni, ti-Ni, ni-Si, nb-Si, al-cuox, al-Pt thin films.
3. A method of interconnecting a microstructure array according to claim 1 or 2, wherein the first and/or second solder layers have a melting point below the instantaneous highest reaction temperature of the self-propagating multilayer film.
4. The method of claim 1, wherein the first and/or second solder layers comprise tin, gold, lead, silver, zinc, bismuth, indium, aluminum, or copper-based alloys.
5. The method of claim 4, wherein the first and/or second solder layers comprise one or both of binary or ternary tin-based, binary or ternary zinc-based, binary or ternary gold-based, binary or ternary bismuth-based alloys.
6. The method of interconnecting a microstructure array of claim 4, wherein the melting point range of the first and/or second solder layers and the self-propagating multilayer film contact area is 1100-400 ℃; the melting point range of the welding interface area of the first brazing filler metal layer and/or the second brazing filler metal layer is 100-400 ℃.
7. A method of interconnecting a microstructure array as claimed in claim 1, wherein dry deposition or wet deposition is used to control the composition of the first and/or second solder layers in a gradient manner in a thickness direction away from the self-propagating multilayer film to obtain a gradient distribution in which the melting point is decreased in a thickness direction away from the self-propagating multilayer film.
8. The method of interconnecting a microstructure array of claim 7, wherein the dry deposition includes setting deposition rates of different targets; or, the wet deposition comprises the steps of setting the concentration of a metal ion source in the electroplating liquid component or setting electroplating process parameters.
9. The method of interconnecting a microstructure array of claim 7, further comprising the step of depositing a seed layer on the first substrate layer and on the second substrate layer.
10. A microstructure array device bonding structure comprising a device, a spacer and a base plate stacked in sequence, wherein:
the pad is arranged between the device and the bottom plate and is respectively bonded with the device and the bottom plate through a solder layer;
the solder layer comprises a first solder layer, a self-propagating multilayer film and a second solder layer which are stacked in sequence; wherein,
the melting point of the first brazing filler metal layer and/or the second brazing filler metal layer is distributed in a gradient manner in a decreasing manner along the thickness direction far away from the self-propagating multilayer film.
11. The microstructure array device bonding structure of claim 10, wherein the device comprises a laser diode or an IGBT chip.
12. The microstructure array device bonding structure of claim 10, wherein the self-propagating multilayer film comprises one or more of Ti-Al, al-Ni, ti-Ni, ni-Si, nb-Si, al-cuox, al-Pt thin films; and/or the number of the groups of groups,
the first brazing filler metal layer and/or the second brazing filler metal layer are/is made of tin-based, gold-based, lead-based, silver-based, zinc-based, bismuth-based, indium-based, aluminum-based or copper-based alloys;
and/or the number of the groups of groups,
the first solder layer and/or the second solder layer are/is made of one or two of binary or ternary tin base, binary or ternary zinc base, binary or ternary gold base and binary or ternary bismuth base alloy.
13. The microstructure array device bonding structure of claim 10, wherein the first and/or second solder layers have a melting point lower than the instantaneous reaction maximum temperature of the self-propagating multilayer film.
14. The microstructure array device bonding structure of claim 10, wherein the melting point range of the contact area of the first and/or second solder layers and the self-propagating multilayer film is 1100-400 ℃; the melting point range of the welding interface area of the first brazing filler metal layer and/or the second brazing filler metal layer is 100-400 ℃.
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