CN114967816A - Low-temperature reference voltage source integrated circuit - Google Patents

Low-temperature reference voltage source integrated circuit Download PDF

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Publication number
CN114967816A
CN114967816A CN202210731711.0A CN202210731711A CN114967816A CN 114967816 A CN114967816 A CN 114967816A CN 202210731711 A CN202210731711 A CN 202210731711A CN 114967816 A CN114967816 A CN 114967816A
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mos transistor
mos
electrode
drain
source
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邵珠雷
张翼
冯志波
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Xuchang University
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Xuchang University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention relates to the technical field of integrated circuits, and provides a low-temperature reference voltage source integrated circuit which can normally and stably work in a low-temperature environment and output reference voltage. The invention comprises a low-temperature bias circuit and a low-temperature reference voltage generating circuit. The invention is provided with the low-temperature starting circuit, does not depend on leakage current in the circuit, and can quickly start the circuit in a low-temperature environment. The invention is provided with the frequency compensation circuit, thereby effectively increasing the frequency application range of the circuit. The invention sets the working area of the related MOS tube which generates the reference voltage, so that the output voltage is not influenced by the temperature change and is output as the reference voltage. The circuit of the invention has simple structure, and part of MOS tubes work in the weak inversion region, thus having lower power consumption.

Description

Low-temperature reference voltage source integrated circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-temperature reference voltage source integrated circuit.
Background
The reference voltage source integrated circuit is generally applied to a voltage regulating circuit, a complex digital-analog hybrid circuit and a system-on-chip circuit. However, most of the reference voltage source integrated circuits are generally applied to room temperature. When the reference voltage source integrated circuit operates in a low temperature environment, such as a thermodynamic temperature range of 230K to 4K, the low temperature effect of most MOS transistors is not negligible. Under the influence of low-temperature environment, working processes such as power-on starting of the reference voltage source integrated circuit, generation of reference voltage and the like cannot be normally completed through a traditional circuit structure, the application range of working frequency of the circuit is narrowed, and the stability of a system is obviously reduced.
Disclosure of Invention
The invention aims to provide a low-temperature reference voltage source integrated circuit which can normally and stably work in a low-temperature environment and output reference voltage.
The technical scheme of the invention is as follows:
a low-temperature reference voltage source integrated circuit includes a low-temperature bias circuit 1 and a low-temperature reference voltage generating circuit 2.
The low-temperature bias circuit 1 includes a low-temperature start circuit 11 and a bias voltage circuit 12.
The low-temperature start circuit 11 and the bias voltage circuit 12 are connected to each other, so that the bias voltage circuit 12 can start and normally operate in a low-temperature environment.
The low-temperature reference voltage generation circuit 2 includes a compensation bias circuit 21 and a reference voltage circuit 22.
The compensation bias circuit 21 and the reference voltage circuit 22 are connected with each other, so that the reference voltage circuit 22 is biased in a correct working area, the phase margin of a circuit system is increased, the frequency application range of the circuit system is expanded, and meanwhile, the stable operation of the circuit system is well maintained.
The low temperature bias circuit 1 includes ports VB1, VD1 and VH 1. The low-temperature reference voltage generating circuit 2 includes ports VB2, VD2, VH2, and OUT. The port VB1 is connected with the port VB2 and is used for transmitting a bias voltage V B . The port VD1 is connected with the port VD2 and is used for transmitting bias voltage V D . The port VH1 is connected with the port VH2 and is used for transmitting bias voltage V H 。
Since leakage current in an integrated circuit is almost non-existent in a low temperature environment, i.e., in the thermodynamic temperature range of 230K to 4K. The low-temperature bias circuit 1 enables the low-temperature bias circuit 1 to be powered on and started without depending on a leakage current loop in the circuit by arranging a low-temperature starting circuit. The low-temperature bias circuit 1 is mainly used for generating various bias voltages to ensure the normal working state of the low-temperature reference voltage generating circuit 2.
The low-temperature reference voltage generating circuit 2 generates and outputs reference voltages which are not affected by temperature changes in relevant branches by setting connection structures and working areas of relevant MOS tubes under the premise of considering the warping effect of the MOS tubes in a low-temperature environment. The low-temperature reference voltage generating circuit 2 maintains the stable operation of the system by arranging the frequency compensation circuit, and increases the frequency application range of the system.
Optionally, the low-temperature bias circuit 1 includes MOS transistors M1 to M16, resistors R1 to R3, a capacitor C1, a port VB1, a port VD1, and a port VH 1.
Optionally, the MOS transistors M1 to M6, the capacitor C1 and the resistor R1 are connected to form a low temperature start circuit 11.
Optionally, the source of the MOS transistor M1 is connected to a power supply VDD, the gate of the MOS transistor M1 is connected to the drain of the MOS transistor M1, and the drain of the MOS transistor M1 is connected to the source of the MOS transistor M2. The source electrode of the MOS transistor M2 is connected with the gate electrode of the MOS transistor M1, the gate electrode of the MOS transistor M2 is connected with the source electrode of the MOS transistor M4, and the drain electrode of the MOS transistor M2 is connected with the upper end of the resistor R1. The source electrode of the MOS transistor M3 is connected with the lower end of the resistor R1, the grid electrode of the MOS transistor M3 is connected with the drain electrode of the MOS transistor M3, and the drain electrode of the MOS transistor M3 is connected with a negative power supply VSS. The upper end of the capacitor C1 is connected with the grid of the MOS tube M5, and the lower end of the capacitor C1 is connected with a negative power supply VSS. The source electrode of the MOS transistor M4 is connected with the drain electrode of the MOS transistor M7, the gate electrode of the MOS transistor M4 is connected with the drain electrode of the MOS transistor M4, and the drain electrode of the MOS transistor M4 is connected with the source electrode of the MOS transistor M5. The source electrode of the MOS transistor M5 is connected with the gate electrode of the MOS transistor M4, the gate electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M3, and the drain electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M6. The source electrode of the MOS transistor M6 is connected with the drain electrode of the MOS transistor M5, the gate electrode of the MOS transistor M6 is connected with the drain electrode of the MOS transistor M6, and the drain electrode of the MOS transistor M6 is connected with a negative power supply VSS.
Optionally, the MOS transistors M7 to M16, the resistors R2 to R3, and the ports VB1, VD1, and VH1 are connected to form the bias voltage circuit 12.
Optionally, the source of the MOS transistor M7 is connected to a power supply VDD, the gate of the MOS transistor M7 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M7 is connected to the drain of the MOS transistor M8. The drain of the MOS transistor M8 is connected to the gate of the MOS transistor M10, the gate of the MOS transistor M8 is connected to the gate of the MOS transistor M11, and the source of the MOS transistor M8 is connected to the drain of the MOS transistor M9. The drain electrode of the MOS tube M9 is connected with the source electrode of the MOS tube M8, the gate electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M12, and the source electrode of the MOS tube M9 is connected with a negative power supply VSS. The source electrode of the MOS tube M10 is connected with a power supply VDD, the gate electrode of the MOS tube M10 is connected with the drain electrode of the MOS tube M7, and the drain electrode of the MOS tube M10 is connected with the drain electrode of the MOS tube M11. The drain of the MOS transistor M11 is connected to the drain of the MOS transistor M10, the gate of the MOS transistor M11 is connected to the drain of the MOS transistor M8, and the source of the MOS transistor M11 is connected to the upper end of the resistor R2. The upper end of the resistor R2 is connected with the grid electrode of the MOS tube M12, and the lower end of the resistor R2 is connected with the grid electrode of the MOS tube M9. The drain electrode of the MOS transistor M12 is connected with the lower end of the resistor R2, the gate electrode of the MOS transistor M12 is connected with the source electrode of the MOS transistor M6, and the source electrode of the MOS transistor M12 is connected with a negative power supply VSS. The source of the MOS transistor M13 is connected to a power supply VDD, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M13 is connected to the upper end of the resistor R3. The drain of the MOS transistor M14 is connected with the lower end of the resistor R3, the gate of the MOS transistor M14 is connected with the gate of the MOS transistor M11, and the source of the MOS transistor M14 is connected with the drain of the MOS transistor M15. The drain of the MOS transistor M15 is connected to the source of the MOS transistor M14, the gate of the MOS transistor M15 is connected to the upper end of the resistor R2, and the source of the MOS transistor M15 is connected to the source of the MOS transistor M16. The source electrode of the MOS tube M16 is connected with the source electrode of the MOS tube M15, the gate electrode of the MOS tube M16 is connected with the drain electrode of the MOS tube M16, and the drain electrode of the MOS tube M16 is connected with a negative power supply VSS. The port VB1 is connected with the gate of the MOS tube M13, the port VD1 is connected with the drain of the MOS tube M13, and the port VH1 is connected with the source of the MOS tube M14.
Optionally, the low-temperature reference power generating circuit 2 includes MOS transistors M17 to M30, resistors R4 to R6, capacitors C2 to C3, a port VB2, a port VD2, a port VH2, and a port OUT.
Optionally, the MOS transistors M17 to M25, the resistors R4 to R5, the capacitors C2 to C3, the port VB2, the port VD2, and the port VH2 are connected to form the compensation bias circuit 21.
Optionally, the source of the MOS transistor M17 is connected to a power supply VDD, the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M24, and the drain of the MOS transistor M17 is connected to the drain of the MOS transistor M18. The source electrode of the MOS transistor M18 is connected with the drain electrode of the MOS transistor M17, the gate electrode of the MOS transistor M18 is connected with the gate electrode of the MOS transistor M25, and the drain electrode of the MOS transistor M18 is connected with the upper end of the resistor R4. The upper end of the capacitor C2 is connected with the lower end of the resistor R4, and the lower end of the capacitor C2 is connected with a negative power supply VSS. The source electrode of the MOS tube M19 is connected with the port VD2, the gate electrode of the MOS tube M19 is connected with the gate electrode of the MOS tube M22, and the drain electrode of the MOS tube M19 is connected with the drain electrode of the MOS tube M20. The drain of the MOS transistor M20 is connected to the gate of the MOS transistor M19, the gate of the MOS transistor M20 is connected to the port VH2, and the source of the MOS transistor M20 is connected to the drain of the MOS transistor M21. The drain electrode of the MOS tube M21 is connected with the source electrode of the MOS tube M23, the gate electrode of the MOS tube M21 is connected with the drain electrode of the MOS tube M21, and the source electrode of the MOS tube M21 is connected with a negative power supply VSS. The source electrode of the MOS transistor M22 is connected with the source electrode of the MOS transistor M19, the gate electrode of the MOS transistor M22 is connected with the drain electrode of the MOS transistor M19, and the drain electrode of the MOS transistor M22 is connected with the drain electrode of the MOS transistor M23. The drain of the MOS transistor M23 is connected to the gate of the MOS transistor M26, the gate of the MOS transistor M23 is connected to the upper end of the resistor R5, and the source of the MOS transistor M23 is connected to the source of the MOS transistor M20. The source of the MOS transistor M24 is connected to a power supply VDD, the gate of the MOS transistor M24 is connected to the port VB2, and the drain of the MOS transistor M24 is connected to the source of the MOS transistor M25. The source electrode of the MOS transistor M25 is connected with the drain electrode of the MOS transistor M24, the gate electrode of the MOS transistor M25 is connected with the drain electrode of the MOS transistor M18, and the drain electrode of the MOS transistor M25 is connected with the upper end of the resistor R5. The upper end of the capacitor C3 is connected with the lower end of the resistor R5, and the lower end of the capacitor C3 is connected with a negative power supply VSS.
Optionally, the MOS transistors M26 to M30, the resistor R6, and the port OUT are connected to form the reference voltage circuit 22.
Optionally, the source of the MOS transistor M26 is connected to a power supply VDD, the gate of the MOS transistor M26 is connected to the gate of the MOS transistor M24, and the drain of the MOS transistor M26 is connected to the upper end of the resistor R6 and to the port OUT. The drain of the MOS transistor M27 is connected with the lower end of the resistor R6, the gate of the MOS transistor M27 is connected with the upper end of the resistor R5, and the source of the MOS transistor M27 is connected with the drain of the MOS transistor M28. The drain of the MOS transistor M28 is connected to the source of the MOS transistor M27, the gate of the MOS transistor M28 is connected to the gate of the MOS transistor M27, and the source of the MOS transistor M28 is connected to the drain of the MOS transistor M29. The drain electrode of the MOS transistor M29 is connected with the source electrode of the MOS transistor M28, the gate electrode of the MOS transistor M29 is connected with the gate electrode of the MOS transistor M28, and the source electrode of the MOS transistor M29 is connected with a negative power supply VSS. The drain electrode of the MOS tube M30 is connected with the drain electrode of the MOS tube M27, the gate electrode of the MOS tube M30 is connected with the gate electrode of the MOS tube M29, and the source electrode of the MOS tube M30 is connected with a negative power supply VSS.
Compared with the prior art, the low-temperature reference voltage source integrated circuit provided by the invention can normally work in a low-temperature environment and output the reference voltage which is not influenced by temperature change. The invention is provided with the low-temperature starting circuit, does not depend on leakage current in the circuit, and can quickly start the circuit in a low-temperature environment. The invention is provided with the frequency compensation circuit, thereby effectively increasing the frequency application range of the circuit. The invention sets the working area of the related MOS tube which generates the reference voltage, so that the output voltage is not influenced by the temperature change and is output as the reference voltage. The circuit of the invention has simple structure, and part of MOS tubes work in the weak inversion region, thus having lower power consumption.
Drawings
FIG. 1 is a system block diagram of a low-temperature reference voltage source integrated circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a low temperature bias circuit according to an embodiment of the present invention;
fig. 3 is a circuit configuration diagram of the low-temperature reference voltage generating circuit according to the embodiment of the present invention.
Description of reference numerals:
1-a low temperature reference voltage source integrated circuit; 11-a low temperature start-up circuit; 12-a bias voltage circuit; 2-a low temperature reference voltage generating circuit; 21-compensation bias circuit; 22-reference voltage circuit.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
In the description herein, references to the terms "an embodiment," "one embodiment," and "one implementation," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or implementation is included in at least one embodiment or example implementation of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or implementation. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or implementations.
In order to solve the above technical problem, with reference to fig. 1, an embodiment of the present invention provides a low-temperature reference voltage source integrated circuit, which can overcome the influence of a low-temperature environment on the integrated circuit, operate normally in the low-temperature environment, and output a reference voltage.
A low-temperature reference voltage source integrated circuit includes a low-temperature bias circuit 1 and a low-temperature reference voltage generating circuit 2.
The low-temperature bias circuit 1 includes a low-temperature start circuit 11 and a bias voltage circuit 12.
The low-temperature start circuit 11 and the bias voltage circuit 12 are connected to each other, so that the bias voltage circuit 12 can start and normally operate in a low-temperature environment.
The low-temperature reference voltage generation circuit 2 includes a compensation bias circuit 21 and a reference voltage circuit 22.
It should be noted that, the compensation bias circuit 21 and the reference voltage circuit 22 are connected to each other, so that the reference voltage circuit 22 is biased in a correct working area, the phase margin of the circuit system is increased, the frequency application range of the circuit system is expanded, and the stable operation of the circuit system is better maintained.
The low temperature bias circuit 1 includes ports VB1, VD1, and VH 1. The low-temperature reference voltage generating circuit 2 includes ports VB2, VD2, VH2, and OUT. The port VB1 is connected with the port VB2 and is used for transmitting bias voltage V B . The port VD1 is connected with the port VD2 and is used for transmitting bias voltage V D . The port VH1 is connected with the port VH2 and is used for transmitting bias voltage V H 。
It should be noted that, since the leakage current in the integrated circuit is almost absent in a low temperature environment, i.e., in the thermodynamic temperature range of 230K to 4K. The low-temperature bias circuit 1 enables the low-temperature bias circuit 1 to be powered on and started without depending on a leakage current loop in the circuit by arranging a low-temperature starting circuit. The low-temperature bias circuit 1 is mainly used for generating various bias voltages to ensure the normal working state of the low-temperature reference voltage generating circuit 2.
The low-temperature reference voltage generating circuit 2 generates and outputs a reference voltage that is not affected by a temperature change in the relevant branch by providing a connection structure and an operating region of the relevant MOS transistor, in consideration of a warpage effect of the MOS transistor in a low-temperature environment. The low-temperature reference voltage generating circuit 2 maintains the stable operation of the system by arranging the frequency compensation circuit, and increases the frequency application range of the system.
In an embodiment of the present invention, as shown in fig. 2, the low temperature bias circuit 1 includes MOS transistors M1 to M16, resistors R1 to R3, a capacitor C1, a port VB1, a port VD1, and a port VH 1.
The MOS transistors M1-M6, the capacitor C1 and the resistor R1 are connected to form a low temperature starting circuit 11.
The source electrode of the MOS tube M1 is connected with a power supply VDD, the gate electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M1, and the drain electrode of the MOS tube M1 is connected with the source electrode of the MOS tube M2. The source electrode of the MOS transistor M2 is connected with the gate electrode of the MOS transistor M1, the gate electrode of the MOS transistor M2 is connected with the source electrode of the MOS transistor M4, and the drain electrode of the MOS transistor M2 is connected with the upper end of the resistor R1. The source electrode of the MOS transistor M3 is connected with the lower end of the resistor R1, the grid electrode of the MOS transistor M3 is connected with the drain electrode of the MOS transistor M3, and the drain electrode of the MOS transistor M3 is connected with a negative power supply VSS. The upper end of the capacitor C1 is connected with the gate of the MOS tube M5, and the lower end of the capacitor C1 is connected with a negative power supply VSS. The source electrode of the MOS transistor M4 is connected with the drain electrode of the MOS transistor M7, the gate electrode of the MOS transistor M4 is connected with the drain electrode of the MOS transistor M4, and the drain electrode of the MOS transistor M4 is connected with the source electrode of the MOS transistor M5. The source electrode of the MOS transistor M5 is connected with the gate electrode of the MOS transistor M4, the gate electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M3, and the drain electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M6. The source electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M5, the gate electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M6, and the drain electrode of the MOS tube M6 is connected with a negative power supply VSS.
It should be noted that, after the system is powered on, based on the related circuit connection structure of the MOS transistor M3 and the capacitor C1, the gate voltage of the MOS transistor M5 is pulled low first, and the branch where the drain and source electrodes of the MOS transistors M4, M5, and M6 are located is turned on. Based on the related circuit connection structure of the MOS transistors M1 and M4, the MOS transistor M2 is turned on and operates in a saturation region, so as to provide a bias voltage for the gate of the MOS transistor M5, and the MOS transistor M5 also operates in the saturation region. When the MOS transistor M5 works in a saturation region, the gate-source voltage of the MOS transistor M6 serves as a bias voltage to provide gate bias for the MOS transistor M12, and the gate-source voltage of the MOS transistor M4 serves as a bias voltage V B And gate bias is provided for the MOS transistors M7, M10 and M13, and the gate bias is output through the port VB 1.
The MOS tubes M7 to M16, the resistors R2 to R3, the ports VB1, VD1 and VH1 are connected to form a bias voltage circuit 12.
The source electrode of the MOS tube M7 is connected with a power supply VDD, the gate electrode of the MOS tube M7 is connected with the gate electrode of the MOS tube M10, and the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8. The drain of the MOS transistor M8 is connected to the gate of the MOS transistor M10, the gate of the MOS transistor M8 is connected to the gate of the MOS transistor M11, and the source of the MOS transistor M8 is connected to the drain of the MOS transistor M9. The drain electrode of the MOS tube M9 is connected with the source electrode of the MOS tube M8, the gate electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M12, and the source electrode of the MOS tube M9 is connected with a negative power supply VSS. The source electrode of the MOS tube M10 is connected with a power supply VDD, the gate electrode of the MOS tube M10 is connected with the drain electrode of the MOS tube M7, and the drain electrode of the MOS tube M10 is connected with the drain electrode of the MOS tube M11. The drain of the MOS transistor M11 is connected to the drain of the MOS transistor M10, the gate of the MOS transistor M11 is connected to the drain of the MOS transistor M8, and the source of the MOS transistor M11 is connected to the upper end of the resistor R2. The upper end of the resistor R2 is connected with the grid electrode of the MOS tube M12, and the lower end of the resistor R2 is connected with the grid electrode of the MOS tube M9. The drain electrode of the MOS transistor M12 is connected with the lower end of the resistor R2, the gate electrode of the MOS transistor M12 is connected with the source electrode of the MOS transistor M6, and the source electrode of the MOS transistor M12 is connected with a negative power supply VSS. The source of the MOS transistor M13 is connected to a power supply VDD, the gate of the MOS transistor M13 is connected to the gate of the MOS transistor M10, and the drain of the MOS transistor M13 is connected to the upper end of the resistor R3. The drain electrode of MOS pipe M14 is connected the lower extreme of resistance R3, the grid connection of MOS pipe M14 the grid of MOS pipe M11, the source electrode of MOS pipe M14 is connected the drain electrode of MOS pipe M15. The drain of the MOS transistor M15 is connected to the source of the MOS transistor M14, the gate of the MOS transistor M15 is connected to the upper end of the resistor R2, and the source of the MOS transistor M15 is connected to the source of the MOS transistor M16. The source electrode of the MOS tube M16 is connected with the source electrode of the MOS tube M15, the gate electrode of the MOS tube M16 is connected with the drain electrode of the MOS tube M16, and the drain electrode of the MOS tube M16 is connected with a negative power supply VSS. The port VB1 is connected with the gate of the MOS tube M13, the port VD1 is connected with the drain of the MOS tube M13, and the port VH1 is connected with the source of the MOS tube M14.
It should be noted that, based on the related circuit connection structure of the MOS transistors M7 to M11, the MOS transistors M8 and M11 are biased to operate in the weak inversion region, and the gate-source voltage of the MOS transistor M8 is used as the MOS transistor M14The MOS transistor M14 is operated in a weak inversion region, and the voltage V at the upper end of the resistor R3 connected with the drain of the MOS transistor M14 D As a bias voltage, output through the port VD 1. The gate-source voltage of the MOS transistor M12 is used as the gate bias voltage of the MOS transistor M15, so that the MOS transistor M15 works in a weak inversion region, and the drain voltage of the MOS transistor M15 is used as the bias voltage V H And output through the port VH 1.
In an embodiment of the present invention, as shown in fig. 3, the low-temperature reference power generating circuit 2 includes MOS transistors M17 to M30, resistors R4 to R6, capacitors C2 to C3, a port VB2, a port VD2, a port VH2, and a port OUT.
MOS tubes M17-M25, resistors R4-R5, capacitors C2-C3, a port VB2, a port VD2 and a port VH2 are connected to form the compensation bias circuit 21.
The source electrode of the MOS tube M17 is connected with a power supply VDD, the gate electrode of the MOS tube M17 is connected with the gate electrode of the MOS tube M24, and the drain electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M18. The source electrode of the MOS transistor M18 is connected with the drain electrode of the MOS transistor M17, the gate electrode of the MOS transistor M18 is connected with the gate electrode of the MOS transistor M25, and the drain electrode of the MOS transistor M18 is connected with the upper end of the resistor R4. The upper end of the capacitor C2 is connected with the lower end of the resistor R4, and the lower end of the capacitor C2 is connected with a negative power supply VSS. The source electrode of the MOS tube M19 is connected with the port VD2, the gate electrode of the MOS tube M19 is connected with the gate electrode of the MOS tube M22, and the drain electrode of the MOS tube M19 is connected with the drain electrode of the MOS tube M20. The drain of the MOS transistor M20 is connected to the gate of the MOS transistor M19, the gate of the MOS transistor M20 is connected to the port VH2, and the source of the MOS transistor M20 is connected to the drain of the MOS transistor M21. The drain electrode of the MOS tube M21 is connected with the source electrode of the MOS tube M23, the gate electrode of the MOS tube M21 is connected with the drain electrode of the MOS tube M21, and the source electrode of the MOS tube M21 is connected with a negative power supply VSS. The source electrode of the MOS transistor M22 is connected with the source electrode of the MOS transistor M19, the gate electrode of the MOS transistor M22 is connected with the drain electrode of the MOS transistor M19, and the drain electrode of the MOS transistor M22 is connected with the drain electrode of the MOS transistor M23. The drain of the MOS transistor M23 is connected to the gate of the MOS transistor M26, the gate of the MOS transistor M23 is connected to the upper end of the resistor R5, and the source of the MOS transistor M23 is connected to the source of the MOS transistor M20. The source of the MOS transistor M24 is connected to a power supply VDD, the gate of the MOS transistor M24 is connected to the port VB2, and the drain of the MOS transistor M24 is connected to the source of the MOS transistor M25. The source electrode of the MOS transistor M25 is connected with the drain electrode of the MOS transistor M24, the gate electrode of the MOS transistor M25 is connected with the drain electrode of the MOS transistor M18, and the drain electrode of the MOS transistor M25 is connected with the upper end of the resistor R5. The upper end of the capacitor C3 is connected with the lower end of the resistor R5, and the lower end of the capacitor C3 is connected with a negative power supply VSS.
It should be noted that the circuit connection structures related to the MOS transistor M17, the MOS transistor M18, the MOS transistor M24, the MOS transistor M25, the resistor R4, the resistor R5, the capacitor C2, and the capacitor C3 have a frequency compensation function. The gates of the MOS transistor M17 and the MOS transistor M24 receive a bias voltage V through the port VB2 B And enabling the MOS transistor M17, the MOS transistor M18, the MOS transistor M24, the MOS transistor M25, the resistor R4, the resistor R5, the capacitor C2 and the capacitor C3 to work in a normal working state. The resistor R4, the resistor R5, the capacitor C2 and the capacitor C3 eliminate the loop internal pole of the low-temperature reference power generation circuit system, the output pole frequency of the drain node of the MOS transistor M18 is higher than that of the drain node of the MOS transistor M25, the phase margin of the circuit system is increased, the frequency application range of the circuit system is expanded, and meanwhile the stable operation of the circuit system is well maintained.
It should be noted that the related circuit connection structures of the MOS transistors M19 to M23 have the function of stabilizing voltage. The source electrode of the MOS transistor M19 and the source electrode of the MOS transistor M22 obtain a bias voltage V through the port VD2 D . The port VH2 is connected with the drain of the MOS transistor M18 and the gate of the MOS transistor M20, so that the voltage of the drain node of the MOS transistor M18 is equal to the bias voltage H V . The drain of the MOS transistor M22 is connected to the gate of the MOS transistor M24, the drain of the MOS transistor M24 is connected to the source of the MOS transistor M25, and the drain of the MOS transistor M25 is connected to the gate of the MOS transistor M23. The above connection constitutes a negative feedback path F1. Based on the related circuit connection structure of the MOS transistors M19-M23 and the negative feedback path F1, the MOThe voltage of the drain node of the S-shaped transistor M25 is equal to the voltage of the drain node of the MOS transistor M18, i.e. the voltage of the drain node of the MOS transistor M25 is equal to the bias voltage H V 。
The MOS transistors M26 to M30, the resistor R6, and the port OUT are connected to constitute the reference voltage circuit 22.
The source electrode of the MOS tube M26 is connected with a power supply VDD, the gate electrode of the MOS tube M26 is connected with the gate electrode of the MOS tube M24, and the drain electrode of the MOS tube M26 is connected with the upper end of the resistor R6 and is connected with a port OUT. The drain of the MOS transistor M27 is connected with the lower end of the resistor R6, the gate of the MOS transistor M27 is connected with the upper end of the resistor R5, and the source of the MOS transistor M27 is connected with the drain of the MOS transistor M28. The drain of the MOS transistor M28 is connected to the source of the MOS transistor M27, the gate of the MOS transistor M28 is connected to the gate of the MOS transistor M27, and the source of the MOS transistor M28 is connected to the drain of the MOS transistor M29. The drain electrode of the MOS transistor M29 is connected with the source electrode of the MOS transistor M28, the gate electrode of the MOS transistor M29 is connected with the gate electrode of the MOS transistor M28, and the source electrode of the MOS transistor M29 is connected with a negative power supply VSS. The drain electrode of the MOS tube M30 is connected with the drain electrode of the MOS tube M27, the gate electrode of the MOS tube M30 is connected with the gate electrode of the MOS tube M29, and the source electrode of the MOS tube M30 is connected with a negative power supply VSS.
The gates of the MOS transistors M27, M28, M29, and M30 are connected together to form an equipotential node a. The equipotential node A is connected with the drain pole of the MOS transistor M25 to make the equipotential node voltage equal to the voltage V H . The gate of the MOS transistor M26 is connected with the gate of the MOS transistor M24 to obtain a bias voltage V B . The MOS transistor M26 provides a bias voltage V for the drain node of the MOS transistor M27 through a resistor R6 26 . Based on the connection structure of the MOS transistors M27-M30 and the resistor R6, and considering the warping effect of the MOS transistors in the low-temperature environment, the voltage V at the upper end of the resistor R6 O The expression of (c) is as follows.
Figure BDA0003713883260000111
Wherein R6 is the resistance of the resistor R6, R5 is the resistance of the resistor R5, V TH0 Is a threshold voltage constant of the MOS transistor model at the thermodynamic temperature of 0K,eta is threshold voltage temperature coefficient, T is ambient temperature value, Q is velocity saturation factor, S is electron mobility temperature index, T 0 The temperature constant value is the temperature constant value when the reciprocal of the gate-source voltage temperature of the MOS tube is zero.
By adjusting the bias voltage V H And V 26 The MOS transistors M27 to M30 can be operated at the boundary operating point between the linear region and the saturation region. At this time, the speed saturation factor Q of the MOS tube is equal to the temperature index S of the electron mobility. Voltage V O The expression of (b) is simplified as follows.
Figure BDA0003713883260000112
From the above formula, when the MOS transistors M27 to M30 operate at the boundary operating point between the linear region and the saturation region, the voltage V O Is not affected by the ambient temperature T. Voltage V O As a reference voltage and output through port OUT.
Although the present disclosure has been described above, the scope of the present disclosure is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the spirit and scope of the present disclosure, and these changes and modifications are intended to be within the scope of the present disclosure.

Claims (7)

1. A low-temperature reference voltage source integrated circuit is characterized by comprising a low-temperature bias circuit 1 and a low-temperature reference voltage generating circuit 2;
the low-temperature bias circuit 1 comprises ports VB1, VD1 and VH 1;
the low-temperature reference voltage generating circuit 2 includes ports VB2, VD2, VH2, and OUT;
the port VB1 is connected with the port VB2 and is used for transmitting bias voltage V B (ii) a The port VD1 is connected with the port VD2 and is used for transmitting bias voltage V D (ii) a The port VH1 is connected with the port VH2 and is used for transmitting bias voltage V H ；
The low-temperature bias circuit 1 is mainly used for generating various bias voltages so as to ensure the normal working state of the low-temperature reference voltage generating circuit 2;
the low-temperature reference voltage generating circuit 2 generates and outputs reference voltage which is not affected by temperature change in a relevant branch by setting a connection structure and a working area of a relevant MOS tube.
2. The integrated circuit of claim 1, wherein the low-temperature bias circuit 1 comprises a low-temperature start circuit 11 and a bias voltage circuit 12;
the low-temperature start circuit 11 and the bias voltage circuit 12 are connected to each other, so that the bias voltage circuit 12 can start and normally operate in a low-temperature environment.
3. The integrated circuit of claim 2, wherein the low temperature start-up circuit 11 comprises the MOS transistors M1-M6, the capacitor C1 and the resistor R1;
the source electrode of the MOS tube M1 is connected with a power supply VDD, the gate electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M1, and the drain electrode of the MOS tube M1 is connected with the source electrode of the MOS tube M2; the source electrode of the MOS transistor M2 is connected with the gate electrode of the MOS transistor M1, the gate electrode of the MOS transistor M2 is connected with the source electrode of the MOS transistor M4, and the drain electrode of the MOS transistor M2 is connected with the upper end of the resistor R1; the source electrode of the MOS transistor M3 is connected with the lower end of the resistor R1, the gate electrode of the MOS transistor M3 is connected with the drain electrode of the MOS transistor M3, and the drain electrode of the MOS transistor M3 is connected with a negative power supply VSS; the upper end of the capacitor C1 is connected with the grid electrode of the MOS tube M5, and the lower end of the capacitor C1 is connected with a negative power supply VSS; the source electrode of the MOS transistor M4 is connected with the drain electrode of the MOS transistor M7, the gate electrode of the MOS transistor M4 is connected with the drain electrode of the MOS transistor M4, and the drain electrode of the MOS transistor M4 is connected with the source electrode of the MOS transistor M5; the source electrode of the MOS transistor M5 is connected with the gate electrode of the MOS transistor M4, the gate electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M3, and the drain electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M6; the source electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M5, the gate electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M6, and the drain electrode of the MOS tube M6 is connected with a negative power supply VSS.
4. The low-temperature reference voltage source integrated circuit of claim 2, wherein the bias voltage circuit 12 comprises the MOS transistors M7 to M16, the resistors R2 to R3, the ports VB1, VD1 and VH 1;
the source electrode of the MOS tube M7 is connected with a power supply VDD, the gate electrode of the MOS tube M7 is connected with the gate electrode of the MOS tube M10, and the drain electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M8; the drain of the MOS transistor M8 is connected with the gate of the MOS transistor M10, the gate of the MOS transistor M8 is connected with the gate of the MOS transistor M11, and the source of the MOS transistor M8 is connected with the drain of the MOS transistor M9; the drain electrode of the MOS transistor M9 is connected with the source electrode of the MOS transistor M8, the gate electrode of the MOS transistor M9 is connected with the drain electrode of the MOS transistor M12, and the source electrode of the MOS transistor M9 is connected with a negative power supply VSS; the source electrode of the MOS tube M10 is connected with a power supply VDD, the gate electrode of the MOS tube M10 is connected with the drain electrode of the MOS tube M7, and the drain electrode of the MOS tube M10 is connected with the drain electrode of the MOS tube M11; the drain of the MOS transistor M11 is connected with the drain of the MOS transistor M10, the gate of the MOS transistor M11 is connected with the drain of the MOS transistor M8, and the source of the MOS transistor M11 is connected with the upper end of the resistor R2; the upper end of the resistor R2 is connected with the grid electrode of the MOS tube M12, and the lower end of the resistor R2 is connected with the grid electrode of the MOS tube M9; the drain electrode of the MOS transistor M12 is connected with the lower end of the resistor R2, the gate electrode of the MOS transistor M12 is connected with the source electrode of the MOS transistor M6, and the source electrode of the MOS transistor M12 is connected with a negative power supply VSS; the source electrode of the MOS tube M13 is connected with a power supply VDD, the gate electrode of the MOS tube M13 is connected with the gate electrode of the MOS tube M10, and the drain electrode of the MOS tube M13 is connected with the upper end of the resistor R3; the drain of the MOS transistor M14 is connected with the lower end of the resistor R3, the gate of the MOS transistor M14 is connected with the gate of the MOS transistor M11, and the source of the MOS transistor M14 is connected with the drain of the MOS transistor M15; the drain of the MOS transistor M15 is connected with the source of the MOS transistor M14, the gate of the MOS transistor M15 is connected with the upper end of the resistor R2, and the source of the MOS transistor M15 is connected with the source of the MOS transistor M16; the source electrode of the MOS tube M16 is connected with the source electrode of the MOS tube M15, the gate electrode of the MOS tube M16 is connected with the drain electrode of the MOS tube M16, and the drain electrode of the MOS tube M16 is connected with a negative power supply VSS; the port VB1 is connected with the gate of the MOS tube M13, the port VD1 is connected with the drain of the MOS tube M13, and the port VH1 is connected with the source of the MOS tube M14.
5. The integrated circuit of claim 1, wherein the low-temperature reference voltage generation circuit 2 comprises a compensation bias circuit 21 and a reference voltage circuit 22;
the compensation bias circuit 21 and the reference voltage circuit 22 are connected to each other, so that the reference voltage circuit 22 is biased in a correct working area, the phase margin of the circuit system is increased, the frequency application range of the circuit system is expanded, and meanwhile, the stable operation of the circuit system is well maintained.
6. The low-temperature reference voltage source integrated circuit of claim 5, wherein the compensation bias circuit 21 comprises MOS transistors M17-M25, resistors R4-R5, capacitors C2-C3, a port VB2, a port VD2 and a port VH 2;
the source electrode of the MOS tube M17 is connected with a power supply VDD, the gate electrode of the MOS tube M17 is connected with the gate electrode of the MOS tube M24, and the drain electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M18; the source electrode of the MOS transistor M18 is connected with the drain electrode of the MOS transistor M17, the gate electrode of the MOS transistor M18 is connected with the gate electrode of the MOS transistor M25, and the drain electrode of the MOS transistor M18 is connected with the upper end of the resistor R4; the upper end of the capacitor C2 is connected with the lower end of the resistor R4, and the lower end of the capacitor C2 is connected with a negative power supply VSS; the source electrode of the MOS tube M19 is connected with the port VD2, the gate electrode of the MOS tube M19 is connected with the gate electrode of the MOS tube M22, and the drain electrode of the MOS tube M19 is connected with the drain electrode of the MOS tube M20; the drain of the MOS transistor M20 is connected with the gate of the MOS transistor M19, the gate of the MOS transistor M20 is connected with the port VH2, and the source of the MOS transistor M20 is connected with the drain of the MOS transistor M21; the drain electrode of the MOS transistor M21 is connected with the source electrode of the MOS transistor M23, the gate electrode of the MOS transistor M21 is connected with the drain electrode of the MOS transistor M21, and the source electrode of the MOS transistor M21 is connected with a negative power supply VSS; the source electrode of the MOS transistor M22 is connected with the source electrode of the MOS transistor M19, the gate electrode of the MOS transistor M22 is connected with the drain electrode of the MOS transistor M19, and the drain electrode of the MOS transistor M22 is connected with the drain electrode of the MOS transistor M23; the drain of the MOS transistor M23 is connected with the gate of the MOS transistor M26, the gate of the MOS transistor M23 is connected with the upper end of the resistor R5, and the source of the MOS transistor M23 is connected with the source of the MOS transistor M20; the source of the MOS transistor M24 is connected with a power supply VDD, the gate of the MOS transistor M24 is connected with the port VB2, and the drain of the MOS transistor M24 is connected with the source of the MOS transistor M25; the source electrode of the MOS transistor M25 is connected with the drain electrode of the MOS transistor M24, the gate electrode of the MOS transistor M25 is connected with the drain electrode of the MOS transistor M18, and the drain electrode of the MOS transistor M25 is connected with the upper end of the resistor R5; the upper end of the capacitor C3 is connected with the lower end of the resistor R5, and the lower end of the capacitor C3 is connected with a negative power supply VSS.
7. The integrated circuit of claim 5, wherein the reference voltage circuit 22 comprises MOS transistors M26-M30, a resistor R6 and a port OUT;
the source electrode of the MOS tube M26 is connected with a power supply VDD, the gate electrode of the MOS tube M26 is connected with the gate electrode of the MOS tube M24, and the drain electrode of the MOS tube M26 is connected with the upper end of the resistor R6 and is connected with a port OUT; the drain of the MOS transistor M27 is connected with the lower end of the resistor R6, the gate of the MOS transistor M27 is connected with the upper end of the resistor R5, and the source of the MOS transistor M27 is connected with the drain of the MOS transistor M28; the drain of the MOS transistor M28 is connected with the source of the MOS transistor M27, the gate of the MOS transistor M28 is connected with the gate of the MOS transistor M27, and the source of the MOS transistor M28 is connected with the drain of the MOS transistor M29; the drain electrode of the MOS transistor M29 is connected with the source electrode of the MOS transistor M28, the gate electrode of the MOS transistor M29 is connected with the gate electrode of the MOS transistor M28, and the source electrode of the MOS transistor M29 is connected with a negative power supply VSS; the drain electrode of the MOS tube M30 is connected with the drain electrode of the MOS tube M27, the gate electrode of the MOS tube M30 is connected with the gate electrode of the MOS tube M29, and the source electrode of the MOS tube M30 is connected with a negative power supply VSS.
CN202210731711.0A 2022-06-25 2022-06-25 Low-temperature reference voltage source integrated circuit Withdrawn CN114967816A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115756073A (en) * 2022-12-09 2023-03-07 深圳市中新力电子科技有限公司 Small-size band-gap reference voltage source integrated circuit applied to intelligent mobile device power supply system
CN117492507A (en) * 2023-10-19 2024-02-02 华芯科技(恩施)有限公司 Second-order compensation low-temperature coefficient reference voltage integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115756073A (en) * 2022-12-09 2023-03-07 深圳市中新力电子科技有限公司 Small-size band-gap reference voltage source integrated circuit applied to intelligent mobile device power supply system
CN115756073B (en) * 2022-12-09 2024-03-01 深圳市中新力电子科技有限公司 Small-volume band gap reference voltage source integrated circuit applied to intelligent mobile equipment power supply system
CN117492507A (en) * 2023-10-19 2024-02-02 华芯科技(恩施)有限公司 Second-order compensation low-temperature coefficient reference voltage integrated circuit

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