CN114927864A - Self-duplex antenna - Google Patents
Self-duplex antenna Download PDFInfo
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- CN114927864A CN114927864A CN202210495013.5A CN202210495013A CN114927864A CN 114927864 A CN114927864 A CN 114927864A CN 202210495013 A CN202210495013 A CN 202210495013A CN 114927864 A CN114927864 A CN 114927864A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q13/00—Waveguide horns or mouths; Slot antennas; Leaky-waveguide antennas; Equivalent structures causing radiation along the transmission path of a guided wave
- H01Q13/10—Resonant slot antennas
- H01Q13/18—Resonant slot antennas the slot being backed by, or formed in boundary wall of, a resonant cavity ; Open cavity antennas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q5/00—Arrangements for simultaneous operation of antennas on two or more different wavebands, e.g. dual-band or multi-band arrangements
- H01Q5/20—Arrangements for simultaneous operation of antennas on two or more different wavebands, e.g. dual-band or multi-band arrangements characterised by the operating wavebands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q5/00—Arrangements for simultaneous operation of antennas on two or more different wavebands, e.g. dual-band or multi-band arrangements
- H01Q5/50—Feeding or matching arrangements for broad-band or multi-band operation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention provides a self-duplex antenna, which comprises a stacked structure formed by an upper medium substrate and a lower medium substrate, a metal layer arranged between the upper medium substrate and the lower medium substrate, and a square copper-clad area arranged on the upper surface of the upper medium substrate, wherein the square copper-clad area is etched with a strip-shaped gap and a metal through hole array, the strip-shaped gap is parallel to the diagonal line of the square copper-clad area, one end of the strip-shaped gap is open, the other end of the strip-shaped gap is closed, and the metal through hole array is distributed on two sides of the square copper-clad area far away from the strip-shaped gap; the 1/4 mode substrate integrated waveguide is formed by the strip-shaped slots and the metal through hole arrays, and compared with other self-duplex antennas designed based on SIW and HMSIW structures, the size of the antenna can be effectively reduced.
Description
Technical Field
The application belongs to the technical field of communication, and particularly relates to a self-duplex antenna.
Background
With the rapid development of modern wireless communication technology, in wireless transceiving equipment, a dual-frequency antenna with high isolation of transceiving frequency bands and miniaturization is more and more emphasized. However, in order to achieve the isolation of the transmitting and receiving frequency bands, the antenna and the duplexer are required to be cascaded, which results in larger energy loss and structural size. The self-duplex antenna has the function of transmitting and receiving electromagnetic waves by the antenna and the isolation characteristic of the duplexer, so that the mode of cascading the antenna and the duplexer can be replaced, and the compact structure size is kept. Self-duplex antennas are generally based on microstrip structures and SIW (Substrate Integrated Waveguide) structures.
In order to reduce the size, self-duplex antennas based on HMSIW (Half-Mode Substrate Integrated Waveguide) structure are often used in the prior art. Compared with the self-duplex antenna based on the complete SIW structure, the self-duplex antenna based on the HMSIW structure can be reduced by nearly half, but the self-duplex antenna based on the HMSIW structure still has difficulty in meeting the miniaturization requirement.
Disclosure of Invention
In view of this, the present invention provides a self-duplex antenna, which aims to solve the problem that the self-duplex antenna in the prior art is difficult to satisfy the miniaturization requirement.
A first aspect of an embodiment of the present invention provides a self-duplex antenna, including:
a stacked structure formed by an upper dielectric substrate and a lower dielectric substrate;
the upper dielectric substrate and the lower dielectric substrate are stacked through metal layers, and the metal layers are used for realizing the common grounding of the upper dielectric substrate and the lower dielectric substrate;
recording one surface of the upper dielectric substrate, which is far away from the lower dielectric substrate, as the upper surface of the upper dielectric substrate, and recording one surface of the lower dielectric substrate, which is far away from the upper dielectric substrate, as the lower surface of the lower dielectric substrate;
the upper surface of the upper-layer dielectric substrate is provided with a square copper-clad area, a strip-shaped gap is etched in the square copper-clad area, the strip-shaped gap is parallel to the diagonal line of the square copper-clad area, and one end of the strip-shaped gap is open and the other end is closed; recording a vertex adjacent to the closed position of the strip-shaped gap in the square copper-clad area as a first vertex, wherein two edges of the square copper-clad area, which penetrate through the first vertex, are respectively provided with a metal through hole array penetrating through the square copper-clad area;
marking two vertexes adjacent to the first vertex in the square copper-clad area as a second vertex and a third vertex respectively, wherein the stacking structure is provided with two through holes penetrating through the stacking structure; the positions of the two through holes are both in the square copper-clad area and respectively correspond to the position of the second vertex and the position of the third vertex;
a circular area which can cover the via hole is etched in the metal layer at the position corresponding to the via hole so as to realize the isolation between the metal layer and the via hole;
recording an edge passing through the first vertex and the second vertex as a first edge, and recording an edge passing through the first vertex and the third vertex as a second edge; two vertically arranged strip lines are arranged on the lower surface of the lower-layer dielectric substrate, wherein one strip line starts from one side of the lower-layer dielectric substrate corresponding to the first side and ends at a through hole of the lower-layer dielectric substrate corresponding to the second vertex; the other strip line starts from one side of the lower dielectric substrate corresponding to the second side and ends at a via hole of the lower dielectric substrate corresponding to the third vertex; and a metal probe is arranged in each through hole, one end of each metal probe is connected with one strip line, and the other end of each metal probe is connected with the square copper-clad area through the through hole.
In some possible implementations, a distance between the via corresponding to the second vertex and the opposite side of the second edge is equal to a distance between the via corresponding to the third vertex and the opposite side of the first edge;
the distance between the via hole corresponding to the second vertex and the first edge is greater than the distance between the via hole corresponding to the third vertex and the second edge.
In some possible implementations, the distance between the array of metal vias on the first side and the opposite side of the first side is 17.72 mm; the distance between the metal through hole array on the second edge and the opposite edge of the second edge is 17.735 mm.
In some possible implementations, the diameter of the metal vias in the two rows of metal via arrays is 0.8 mm; the distance between the adjacent metal through holes in each row of metal through hole array is 1.2 mm.
In some possible implementations, a distance between the via corresponding to the second vertex and the opposite side of the second edge and a distance between the via corresponding to the third vertex and the opposite side of the first edge are both 0.9 mm;
the distance between the via hole corresponding to the second vertex and the first edge is 1.4 mm;
and the distance between the via hole corresponding to the third vertex and the second edge is 1.3 mm.
In some possible implementations, the length of the longest side of the slot is 23.84mm, the slot width is 1.203mm, and the distance between the open end of the slot and the second side is 16.003 mm.
In some possible implementations, the radius of the circular area is 2.33 times the via.
In some possible implementations, the dielectric constants of the upper dielectric substrate and the lower dielectric substrate are the same, and the thickness ratio is 3: 1.
in some possible implementations, the upper dielectric substrate has a thickness of 1.524mm, and the lower dielectric substrate has a thickness of 0.508 mm.
In some possible implementations, the dielectric constant of each of the upper dielectric substrate and the lower dielectric substrate is 3.55.
The self-duplex antenna provided by the embodiment of the invention comprises a stacking structure formed by an upper medium substrate and a lower medium substrate, a metal layer arranged between the upper medium substrate and the lower medium substrate, and a square copper-clad area arranged on the upper surface of the upper medium substrate, wherein the square copper-clad area is etched with a strip-shaped gap and a metal through hole array, the strip-shaped gap is parallel to the diagonal line of the square copper-clad area, one end of the strip-shaped gap is open, the other end of the strip-shaped gap is closed, and the metal through hole array is distributed on two sides of the square copper-clad area, which are far away from the strip-shaped gap; the 1/4 mode substrate integrated waveguide is formed by the strip-shaped slots and the metal through hole arrays, and compared with other self-duplex antennas designed based on SIW and HMSIW structures, the size of the antenna can be effectively reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a self-duplex antenna provided in an embodiment of the present invention;
FIG. 2 is a diagram illustrating simulation and test results of scattering parameters provided by an exemplary embodiment of the present invention;
fig. 3 is a schematic diagram comparing radiation patterns of port 1 when phi is 90 deg;
fig. 4 is a schematic diagram comparing radiation patterns of port 1 at phi ═ 0 deg;
fig. 5 is a schematic diagram comparing radiation patterns of port 2 when phi is 0 deg;
fig. 6 is a schematic diagram comparing radiation patterns of port 2 at phi of 90 deg.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
Fig. 1 is a schematic structural diagram of a self-duplex antenna according to an embodiment of the present invention. As shown in fig. 1, in this embodiment, the self-duplex antenna includes:
a stacked structure formed of an upper dielectric substrate 11 and a lower dielectric substrate 12;
the upper dielectric substrate 11 and the lower dielectric substrate 12 are stacked through a metal layer 13, and the metal layer 13 is used for realizing the common ground of the upper dielectric substrate 11 and the lower dielectric substrate 12;
the surface of the upper dielectric substrate 11 far away from the lower dielectric substrate 12 is taken as the upper surface of the upper dielectric substrate 11, and the surface of the lower dielectric substrate 12 far away from the upper dielectric substrate 11 is taken as the lower surface of the lower dielectric substrate 12;
a square copper-clad area 14 is arranged on the upper surface of the upper-layer dielectric substrate 11, a strip-shaped gap is etched in the square copper-clad area 14, the strip-shaped gap is parallel to a diagonal line of the square copper-clad area 14, and one end of the strip-shaped gap is open and the other end is closed; marking the vertex of the square copper-clad area 14 adjacent to the closed position of the strip-shaped gap as a first vertex, and respectively arranging metal through hole arrays penetrating through the square copper-clad area 14 on two edges of the square copper-clad area 14, which penetrate through the first vertex;
respectively marking two vertexes, adjacent to the first vertex, in the square copper-clad area 14 as a second vertex and a third vertex, wherein the stacking structure is provided with two through holes penetrating through the stacking structure; the positions of the two via holes are both in the square copper-clad area 14 and respectively correspond to the position of the second vertex and the position of the third vertex;
a circular area which can cover the via hole is etched in the position, corresponding to the via hole, of the metal layer 13 so as to realize isolation between the metal layer and the via hole;
recording an edge passing through the first vertex and the second vertex as a first edge, and recording an edge passing through the first vertex and the third vertex as a second edge; two vertically arranged strip lines are arranged on the lower surface of the lower dielectric substrate 12, wherein one strip line starts from one side of the lower dielectric substrate 12 corresponding to the first side and ends at a through hole of the lower dielectric substrate 12 corresponding to the second vertex; the other strip line starts from one side of the lower dielectric substrate 12 corresponding to the second side and ends at a via hole of the lower dielectric substrate 12 corresponding to the third vertex; a metal probe is arranged in each through hole, one end of each metal probe is connected with one strip line, and the other end of each metal probe is connected with the square copper-clad area 14 through the through hole.
In this embodiment, the upper dielectric substrate 11 and the lower dielectric substrate 12 are rectangular and have the same length and width, and share the middle metal surface. The sides of the square copper-clad region 14 are parallel or perpendicular to the sides of the upper dielectric substrate 11. As shown in fig. 1, when etching a stripe-shaped gap, a diagonal line of a square copper clad is translated in the positive direction of the y-axis by g, and then the diagonal line is used as the central line of the stripe-shaped gap to etch the stripe-shaped gap with a width w, an open end and a short circuit at one end. Two sides of the square, which are perpendicular to each other and are far away from the strip-shaped gap, are respectively provided with a row of metal through hole arrays which are periodically arranged, a through hole pitch p and a diameter d. An 1/4 Mode Substrate Integrated Waveguide (QMSIW) radiating cavity is formed by placing an array of strip slots and metal vias in a square copper clad region 14. The metal probes in the two via holes arranged in the stacked structure and the two strip lines on the lower surface of the lower-layer dielectric substrate 12 form a feed circuit, and the feed circuits respectively feed two feed ports on the corresponding square copper-clad area 14, and the two feed ports respectively correspond to different working frequency bands of the antenna.
In this embodiment, the self-duplex antenna includes a stacked structure formed by an upper dielectric substrate 11 and a lower dielectric substrate 12, a metal layer 13 disposed between the upper dielectric substrate 11 and the lower dielectric substrate 12, and a square copper-clad area 14 disposed on the upper surface of the upper dielectric substrate 11, the square copper-clad area 14 is etched with a strip-shaped slot and a metal through hole array, the strip-shaped slot is parallel to a diagonal of the square copper-clad area 14, one end of the strip-shaped slot is open, and the other end of the strip-shaped slot is closed, and the metal through hole array is distributed on two sides of the square copper-clad area 14 away from the strip-shaped slot; the 1/4 mode substrate integrated waveguide radiation cavity is formed by the strip-shaped slots and the metal through hole array, and compared with other self-duplex antennas designed based on SIW and HMSIW structures, the size of the antenna can be effectively reduced.
In some embodiments, the distance between the via corresponding to the second vertex and the opposite side of the second edge is equal to the distance between the via corresponding to the third vertex and the opposite side of the first edge;
the distance between the via hole corresponding to the second vertex and the first edge is greater than the distance between the via hole corresponding to the third vertex and the second edge.
As shown in FIG. 1, in the present embodiment, S 1 ＝S 4 ，S 2 >S 3 。S 1 And S 2 The corresponding port is port 1, S 3 And S 4 The corresponding port is port 2. A slot etched into the QMSIW radiation cavity can introduce hybrid coupling, creating a zero point between the two ports, thereby improving port isolation.
In some embodiments, the distance between the array of metal vias on the first side and the opposite side of the first side is 17.72 mm; the distance between the array of metal vias on the second side and the opposite side of the second side is 17.735 mm.
As shown in FIG. 1, in the present embodiment,/ 1 ＝17.72mm，l 2 ＝17.735mm。
In some embodiments, the diameter of the metal vias in both rows of the metal via arrays is 0.8 mm; the distance between the adjacent metal through holes in each row of metal through hole array is 1.2 mm.
As shown in fig. 1, in the present embodiment, d is 0.8mm, and p is 1.2 mm.
In some embodiments, the distance between the via corresponding to the second vertex and the opposite side of the second edge and the distance between the via corresponding to the third vertex and the opposite side of the first edge are both 0.9 mm;
the distance between the via hole corresponding to the second vertex and the first edge is 1.4 mm;
the distance between the via hole corresponding to the third vertex and the second edge is 1.3 mm.
As shown in FIG. 1, in the present embodiment, S 1 ＝S 4 ＝0.9mm，S 2 ＝1.4mm，S 3 ＝1.3mm。
In some embodiments, the length of the longest side of the slot is 23.84mm, the slot width is 1.203mm, and the distance between the open end of the slot and the second side is 16.003 mm.
As shown in FIG. 1, in the present embodiment,/ 4 ＝23.84mm，w＝1.203mm，l 3 ＝16.003mm。
In some embodiments, the radius of the circular area is 2.33 times the radius of the via.
In some embodiments, the dielectric constants of the upper dielectric substrate 11 and the lower dielectric substrate 12 are the same, and the thickness ratio is 3: 1.
in this embodiment, the upper dielectric substrate 11 and the lower dielectric substrate 12 are dielectric substrates made of the same material.
In some embodiments, the upper dielectric substrate 11 has a thickness of 1.524mm and the lower dielectric substrate 12 has a thickness of 0.508 mm.
In some embodiments, the dielectric constant of both the upper dielectric substrate 11 and the lower dielectric substrate 12 is 3.55.
The self-duplex antenna of the present invention is further illustrated by the following embodiment, but is not limited thereto. In this example of implementation, the dimensions of the self-duplex antenna are as follows:
TABLE 1 antenna size parameters
Fig. 2 is a diagram illustrating simulation and test results of scattering parameters provided by an embodiment of the present invention. As shown in fig. 2, in the present embodiment, the size of the self-duplex antenna is shown as a dotted line to represent the simulation result, and a solid line to represent the test result. The port 1 corresponds to a lower working frequency band, and the actually measured matching working frequency band is 2.983-3.023 GHz. The port 2 corresponds to a higher working frequency band, and the actually measured matching working frequency band is 3.278-3.318 GHz. The relative bandwidth of both ports is about 13%. The measured port isolation is better than-25 dB.
Fig. 3 is a schematic diagram comparing radiation patterns of port 1 at phi of 90 deg. Fig. 4 is a schematic diagram comparing radiation patterns of the port 1 when phi is 0 deg. As shown in fig. 3 and 4, the achievable gain for the port 1 test was 4.05 dBi.
Fig. 5 is a schematic diagram comparing radiation patterns of port 2 when phi is 0 deg. Fig. 6 is a schematic diagram comparing radiation patterns of port 2 when phi is 90 deg. As shown in fig. 5 and 6, the achievable gain for the port 2 test was 4.31 dBi.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
It should be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional units and modules is only used for illustration, and in practical applications, the above function distribution may be performed by different functional units and modules as needed, that is, the internal structure of the device is divided into different functional units or modules, so as to perform all or part of the above described functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal and method may be implemented in other ways. For example, the above-described apparatus/terminal embodiments are merely illustrative, and for example, a module or a unit may be divided into only one logical function, and may be implemented in other ways, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method according to the embodiments of the present invention may also be implemented by a computer program instructing related hardware, and the computer program may be stored in a computer readable storage medium, and when executed by a processor, the computer program may implement the steps of the above-described embodiments of the method. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer-readable medium may contain suitable additions or subtractions depending on the requirements of legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer-readable media excludes electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A self-duplex antenna, comprising:
a stacked structure formed by an upper dielectric substrate and a lower dielectric substrate;
the upper dielectric substrate and the lower dielectric substrate are stacked through metal layers, and the metal layers are used for realizing the common grounding of the upper dielectric substrate and the lower dielectric substrate;
recording one surface of the upper dielectric substrate, which is far away from the lower dielectric substrate, as the upper surface of the upper dielectric substrate, and recording one surface of the lower dielectric substrate, which is far away from the upper dielectric substrate, as the lower surface of the lower dielectric substrate;
the upper surface of the upper-layer dielectric substrate is provided with a square copper-clad area, a strip-shaped gap is etched in the square copper-clad area, the strip-shaped gap is parallel to the diagonal line of the square copper-clad area, and one end of the strip-shaped gap is open and the other end is closed; recording a vertex adjacent to the closed position of the strip-shaped gap in the square copper-clad area as a first vertex, wherein two edges of the square copper-clad area, which penetrate through the first vertex, are respectively provided with a metal through hole array penetrating through the square copper-clad area;
marking two vertexes adjacent to the first vertex in the square copper-clad area as a second vertex and a third vertex respectively, wherein the stacking structure is provided with two through holes penetrating through the stacking structure; the positions of the two through holes are both in the square copper-clad area and respectively correspond to the positions of the second vertex and the third vertex;
a circular area which can cover the via hole is etched in the metal layer at the position corresponding to the via hole so as to realize the isolation between the metal layer and the via hole;
recording an edge passing through the first vertex and the second vertex as a first edge, and recording an edge passing through the first vertex and the third vertex as a second edge; the lower surface of the lower dielectric substrate is provided with two vertically arranged strip lines, wherein one strip line starts from one side of the lower dielectric substrate corresponding to the first side and ends at a through hole of the lower dielectric substrate corresponding to the second vertex; the other strip line starts from one side of the lower dielectric substrate corresponding to the second side and ends at a via hole of the lower dielectric substrate corresponding to the third vertex; and a metal probe is arranged in each through hole, one end of each metal probe is connected with one strip line, and the other end of each metal probe is connected with the square copper-clad area through the through hole.
2. The self-duplex antenna of claim 1, wherein the distance between the via corresponding to the second vertex and the opposite side of the second edge is equal to the distance between the via corresponding to the third vertex and the opposite side of the first edge;
the distance between the via hole corresponding to the second vertex and the first edge is greater than the distance between the via hole corresponding to the third vertex and the second edge.
3. The self-duplex antenna according to claim 2, wherein the distance between the array of metal vias on the first edge and the opposite edge of the first edge is 17.72 mm; the distance between the metal through hole array on the second edge and the opposite edge of the second edge is 17.735 mm.
4. The self-duplex antenna according to claim 3, wherein the diameter of the metal vias in both rows of the metal via arrays is 0.8 mm; the distance between the adjacent metal through holes in each row of metal through hole array is 1.2 mm.
5. The self-duplex antenna of claim 3, wherein the distance between the via corresponding to the second vertex and the opposite side of the second edge and the distance between the via corresponding to the third vertex and the opposite side of the first edge are both 0.9 mm;
the distance between the via hole corresponding to the second vertex and the first edge is 1.4 mm;
and the distance between the via hole corresponding to the third vertex and the second edge is 1.3 mm.
6. The self-duplex antenna of claim 3, wherein the slot longest side has a length of 23.84mm, the slot width is 1.203mm, and the slot open end is 16.003mm from the second side.
7. The self-duplex antenna of claim 1 wherein the radius of the circular area is 2.33 times the via.
8. The self-duplex antenna of claim 1, wherein the dielectric constants of the upper dielectric substrate and the lower dielectric substrate are the same, and the thickness ratio is 3: 1.
9. the self-duplex antenna of claim 8, wherein the upper dielectric substrate has a thickness of 1.524mm and the lower dielectric substrate has a thickness of 0.508 mm.
10. The self-duplex antenna of claim 8, wherein the dielectric constant of the upper dielectric substrate and the dielectric constant of the lower dielectric substrate are both 3.55.
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