CN114927495A - Packaging method, packaging structure and electronic equipment - Google Patents

Packaging method, packaging structure and electronic equipment Download PDF

Info

Publication number
CN114927495A
CN114927495A CN202210532286.2A CN202210532286A CN114927495A CN 114927495 A CN114927495 A CN 114927495A CN 202210532286 A CN202210532286 A CN 202210532286A CN 114927495 A CN114927495 A CN 114927495A
Authority
CN
China
Prior art keywords
layer
packaging
resistance silicon
silicon substrate
impedance adjusting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210532286.2A
Other languages
Chinese (zh)
Inventor
刘凤
彭祎
任超
方梁洪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ningbo Chipex Semiconductor Co ltd
Original Assignee
Ningbo Chipex Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ningbo Chipex Semiconductor Co ltd filed Critical Ningbo Chipex Semiconductor Co ltd
Priority to CN202210532286.2A priority Critical patent/CN114927495A/en
Publication of CN114927495A publication Critical patent/CN114927495A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to the field of semiconductor packaging technologies, and in particular, to a packaging method, a packaging structure, and an electronic device. The method comprises the following steps: obtaining a substrate to be packaged; the substrate to be packaged comprises a high-resistance silicon substrate; the high-resistance silicon substrate is provided with a packaging surface, and welding spots are arranged on the packaging surface; the surface of the welding spot, which is far away from the high-resistance silicon substrate, is provided with a surface oxidation layer 7; manufacturing an impedance adjusting layer on the surface of the package; the impedance adjusting layer is used for reducing the surface resistivity of the high-resistance silicon substrate; and etching to remove the surface oxide layer 7 to obtain the packaging structure. According to the packaging method, the impedance adjusting layer is arranged on the packaging surface of the substrate, and the impedance adjusting layer can reduce the resistivity of the surface layer of the high-resistance silicon substrate so as to improve the self-bias voltage during radio frequency etching, so that the surface oxidation layer 7 of the welding spot can be completely removed. The method can reduce the requirement of the high-resistance silicon packaging process on etching equipment, and the high-resistance silicon packaging process can be adapted to the existing silicon wafer packaging process production line, so that the production cost is reduced.

Description

Packaging method, packaging structure and electronic equipment
Technical Field
The present invention relates to the field of semiconductor packaging technologies, and in particular, to a packaging method, a packaging structure, and an electronic device.
Background
Integrated Passive Device (IPD) technology can integrate discrete Passive devices within a substrate to improve Device Q and system integration. Because the high-resistance substrate has good radio frequency characteristics, the inductor with the Q value of more than 70 can be prepared by the high-resistance silicon IPD technology. The high-resistance silicon IPD has the characteristics of high precision, high integration level and the like based on the thin film technology, and can reduce the characteristic size of a passive device by one order of magnitude. Meanwhile, a mature silicon process platform can be utilized, so that the cost is reduced by mass production. In addition, the high-resistance Silicon IPD technology can be compatible with a Through Silicon Via (TSV) technology, and three-dimensional laminated packaging can be realized. Analysis shows that the high-resistance silicon IPD technology has wide application prospect in system integration.
The high resistance silicon IPD relates to the copper bump process when packaging. The copper bump process is to process the wafer to complete the substrate circuit, and then to manufacture the copper-tin bumps on the surface of the chip by using the manufacturing techniques of sputtering, gluing, yellow light, electroplating, etching and the like, thereby providing the point connection between the chips and between the chip and the substrate. When the copper bump is manufactured, the surface oxide layer on the surface of the welding spot needs to be removed through plasma etching, so that the reliability of connection between the copper bump and the wafer is ensured. At present, most of plasma etching equipment is radio frequency plasma etching equipment, and a high-resistance silicon wafer has a relatively low radio frequency self-bias voltage due to a relatively high resistance value during radio frequency etching, so that a surface oxidation layer on the surface of a welding spot cannot be completely removed, and the conductivity of a copper bump and a chip is influenced.
Disclosure of Invention
The invention provides a packaging method, a packaging structure and electronic equipment.
In a first aspect, an embodiment of the present application discloses a packaging method, including:
obtaining a substrate to be packaged; the substrate to be packaged comprises a high-resistance silicon substrate; the high-resistance silicon substrate is provided with a packaging surface, and welding spots are arranged on the packaging surface; the surface of the welding spot, which is far away from the high-resistance silicon substrate, is provided with a surface oxidation layer;
manufacturing an impedance adjusting layer on the surface of the package; the impedance adjusting layer is used for reducing the surface resistivity of the high-resistance silicon substrate;
and etching to remove the surface oxide layer to obtain the packaging structure.
Further, the resistivity of the impedance adjusting layer is smaller than that of the high-resistance silicon substrate.
Furthermore, the material of the impedance adjusting layer is polyimide.
Further, the thickness of the resistance adjustment layer is 5 μm to 10 μm.
Further, the manufacturing of the impedance adjusting layer on the package surface includes:
coating a polyimide photoresist layer on the packaging surface;
carrying out graphical processing on the polyimide photoresist layer;
and curing the polyimide photoresist layer after the patterning treatment to obtain the impedance adjusting layer.
Further, after the etching is performed to remove the surface oxide layer to obtain the package structure, the method further includes:
and manufacturing a metal electrode on the surface of the welding spot after the surface oxide layer is removed.
Further, the manufacturing of the metal electrode on the surface of the welding spot after the removal of the surface oxide layer includes:
manufacturing a metal connecting layer on the surface of the welding spot after the surface oxide layer is removed;
and manufacturing the metal electrode on the metal connecting layer.
Furthermore, the metal connecting layer is made of titanium or a composite of titanium and copper.
In a second aspect, an embodiment of the present application discloses a package structure, where the package structure is obtained by using the above-described package method.
In a third aspect, an embodiment of the present application discloses an electronic device, which includes the package structure described above.
By adopting the technical scheme, the packaging method, the packaging structure and the electronic equipment have the following beneficial effects:
according to the packaging method, when the substrate to be packaged with the high-resistance silicon substrate is packaged, the impedance adjusting layer is arranged on the packaging surface of the substrate, and can reduce the impedance of the surface layer of the high-resistance silicon substrate, so that the self-bias voltage during radio frequency etching is improved, and the oxide layer on the surface of the welding spot can be completely removed. The method can reduce the requirement of the high-resistance silicon packaging process on etching equipment, and the high-resistance silicon packaging process can be adapted to the existing silicon wafer packaging process production line, thereby reducing the production cost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of a packaging method according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a package substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a package structure according to an embodiment of the present disclosure.
The following is a supplementary description of the drawings:
1-a high-resistance silicon substrate; 2-a protective layer; 3-a resistance adjusting layer; 4-welding spots; 5-a metal connection layer; 6-copper bumps; 7-surface oxide layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
The high-resistance silicon wafer has high impedance, and the resistivity of the high-resistance silicon wafer reaches 2000 omega cm. High-resistance silicon wafers pose a great challenge to existing silicon wafer level packaging production lines due to their high impedance. As the resistance value of the high-resistance silicon wafer is higher, actual tests show that the etching self-bias voltage is lower and is only about half of that of a common silicon wafer when the oxide layer on the surface of the welding spot is removed by radio frequency etching. In addition, in the radio frequency etching process of the high-resistance silicon wafer, the etching amount is low, the etching process is interrupted, and the like. The method is limited by the existing etching equipment, and the radio frequency etching cannot completely remove the surface oxide layer on the surface of the welding spot, so that the adhesion and the conductivity between the copper bump prepared on the surface of the welding spot in the subsequent copper bump processing and the welding spot are low, the conductivity between the copper bump and a chip is influenced, and the reliability of a product is influenced.
In view of this, embodiments of the present disclosure provide a packaging method, in which an impedance adjusting layer is formed on a surface of a high-resistance silicon wafer to reduce the surface impedance of the high-resistance silicon wafer, so as to increase a self-bias voltage during rf etching, thereby completely removing an oxide layer on a surface of a solder joint.
Fig. 1 is a schematic flowchart of a packaging method provided in an embodiment of the present application, and as shown in fig. 1, the method includes:
s101: obtaining a substrate to be packaged; the substrate to be packaged comprises a high-resistance silicon substrate; the high-resistance silicon substrate is provided with a packaging surface, and welding spots are arranged on the packaging surface; the surface of the welding spot, which is far away from the high-resistance silicon substrate, is provided with a surface oxidation layer.
In the embodiment of the application, the substrate to be packaged can be a semi-finished product obtained in an IPD production process, and the semi-finished product is obtained by processing based on a high-resistance silicon substrate. The substrate to be packaged can be prepared by related processing technology, or can be directly obtained in the market. The preparation method of the substrate to be packaged is not a focus of the embodiments of the present application, and is not described herein again.
In the embodiment of the present application, fig. 2 is a schematic structural diagram of a package substrate provided in the embodiment of the present application, and as shown in fig. 2, the package substrate includes a high-resistance silicon substrate 1. Generally, a protective layer 2 is disposed on the surface of the high-resistance silicon substrate 1 to protect the high-resistance silicon substrate 1. The material of the protection layer 2 may be nitride, oxide, or a composite of nitride and nitride, for example, silicon nitride, silicon oxide, or a composite of silicon nitride and silicon oxide. The high-resistance silicon substrate 1 has two opposite surfaces, one of which is a packaging surface on which a bonding pad is disposed, and the bonding pad includes a plurality of solder joints 4. The surface of the solder joint 4 has a surface oxide layer 7, which surface oxide layer 7 functions to a certain extent to protect the structure of the solder joint 4. However, when the substrate to be packaged having the high-resistance silicon substrate is packaged, the surface oxide layer 7 needs to be removed in order to ensure the connection reliability of the copper bump and the solder joint 4.
S103: manufacturing an impedance adjusting layer on the surface of the package; the impedance adjusting layer is used for reducing the surface resistivity of the high-resistance silicon substrate.
In the embodiment of the application, the surface oxide layer 7 of the welding spot 4 is etched and removed by using a radio frequency etching device. The radio frequency etching equipment etches the surface oxidation layer 7 by generating radio frequency plasma. The etching efficiency of the radio frequency etching equipment is related to the radio frequency self-bias voltage of the radio frequency plasma. To a certain extent, the higher the radio frequency self-bias voltage is, the higher the etching efficiency of the radio frequency etching equipment is. For most semiconductor processing manufacturers, the owned rf facilities are adapted to the common silicon wafer packaging process, and it is difficult to process high-resistance silicon wafers. According to the method, the impedance adjusting layer 3 is manufactured on the packaging surface of the high-resistance silicon substrate 1 to adjust the surface resistivity of the high-resistance silicon substrate 1, so that the high-resistance silicon substrate 1 can be adapted to the existing silicon wafer packaging equipment.
In the embodiment of the present application, the resistivity of the impedance adjusting layer 3 is smaller than the resistivity of the high-resistance silicon substrate 1. Optionally, the resistivity of the resistance adjusting layer 3 is 10 -5 Omega cm-1000 omega cm. Alternatively, the material of the impedance adjusting layer 3 may be a metal or a non-metal material. In order to reduce the cost, the resistance adjusting layer 3 may be made of a photoresist material with a low cost, such as polyimide, SU8, and the like. The photoresist material can reduce the surface layer resistivity of the high-resistance silicon substrate 1, and can improve the radio frequency self-bias voltage when the radio frequency etching equipment etches the high-resistance silicon substrate 1. In addition, the photoresist material has flexibility, and can play a role in increasing buffer and improving the stability of the chip in the later process of high-resistance silicon processing. Optionally, the thickness of the resistance adjustment layer 3 is 5 μm to 10 μm. The specific method can be determined according to the selected material.
In the embodiment of the present application, when the impedance adjusting layer 3 is manufactured, the impedance adjusting layer 3 covering the entire surface may be manufactured on the surface of the package and the surface of the surface oxide layer 7, and then the impedance adjusting layer on the solder joint is removed by the exposure, development, and other processes, so as to form an opening on the impedance adjusting layer, so that the surface oxide layer 7 of the solder joint is exposed, and the etching device etches the surface oxide layer 7. In some embodiments, when the impedance adjusting layer 3 is manufactured, a mask may be first manufactured above the solder joint, then the impedance adjusting layer covering the entire surface is manufactured on the package surface and the surface of the mask, and then the mask is removed to form an opening on the impedance adjusting layer, so that the surface oxide layer 7 of the solder joint is exposed.
As an alternative embodiment, a method for manufacturing the resistance adjustment layer 3 will be described below, taking polyimide as an example of a material of the resistance adjustment layer 3. The method for manufacturing the resistance adjustment layer 3 made of other materials can be referred to this embodiment. A polyimide film may be formed on the package formation surface by coating a polyimide photoresist on the high-resistance silicon substrate 1, and then the resistance adjustment layer may be formed by thermal curing. The solidified polyimide has flexibility, high temperature resistance and acid and alkali resistance. The polyimide can be used as an impedance adjusting layer to protect the welding spot structure. When polyimide is used to fabricate the impedance adjusting layer 3, polyimide photoresist is coated on the surface of the package and the surface of the surface oxide layer 7 to form a polyimide film, and the coating method may be spin coating. Then, the polyimide film was subjected to patterning, and the polyimide film after the patterning was cured to obtain the resistance adjusting layer 3. Specifically, after a layer of photoresist is coated on the packaging surface of the high-resistance silicon substrate 1 and the surface of the surface oxide layer 7, the pattern on the mask is transferred to the photoresist of the high-resistance silicon substrate 1 through an exposure machine table. And then dissolving the soluble part of the exposed photoresist by using a developing solution, wherein the process is the development of the photoresist and mainly aims to accurately copy the pattern on the mask plate to the photoresist. And finally, curing in an oxygen-free curing oven to form the impedance adjusting layer 3 on the surface of the package.
S105: and etching to remove the surface oxide layer 7 to obtain the packaging structure.
In the embodiment of the present application, after the impedance adjusting layer 3 is fabricated on the package surface, the surface oxide layer 7 is etched to remove the surface oxide layer 7 on the solder joint 4, so as to obtain the package structure. Specifically, the substrate to be packaged with the impedance adjusting layer 3 is placed into an etching cavity of the radio frequency etching equipment for operation, and the etched radio frequency self-bias data is tested. After the impedance adjusting layer is manufactured on the packaging surface, actual tests show that the radio frequency self-bias data of the high-resistance silicon substrate 1 with the impedance adjusting layer 3 are normal and can meet the etching requirements, so that the etching equipment can normally etch the oxide layer on the surface of the welding spot 4.
In this embodiment of the application, etching removes surface oxide layer 7 on solder joint 4, after obtaining packaging structure, still includes: and manufacturing a metal electrode on the surface of the welding spot 4 after the surface oxide layer 7 is removed. I.e. copper bumps 6 are made on the surface of the solder bumps 4. Specifically, a metal connection layer 5 is formed on the surface of the solder joint 4 from which the surface oxide layer 7 is removed, and a metal electrode is formed on the metal connection layer 5. Optionally, the metal connection layer 5 is a titanium layer or a composite metal layer of a titanium layer and a copper layer. The titanium layer can improve the binding force of the copper and the high-resistance silicon substrate 1, plays a role of an adhesion layer, can effectively prevent mutual diffusion between the material of the convex welding point 4 and aluminum and silicon, avoids forming bad intermetallic compounds, and plays a role of a diffusion barrier layer. A copper layer is formed on the titanium layer, and the copper layer can be used as a plating seed layer to conduct electricity.
As an optional implementation manner, the surface oxide layer 7 on the welding point 4 is removed by etching, so as to ensure the adhesion and the conductivity between the metal connecting layer 5 and the welding point 4, and then manufacturing technologies such as glue coating, yellow light, electroplating and etching processes are performed to manufacture a copper bump on the surface of the chip, so that the conductivity on the surface of the welding point 4 is ensured, and the reliability of the product is increased. Specifically, the high-resistance silicon substrate 1 with the resistance adjusting layer 3 is first subjected to pre-plating. In order to obtain a clean and fresh metal surface, increase hydrophilicity and bonding force, and prepare for obtaining a high-quality plating layer, the surface oxide layer 7 of the welding spot 4 is subjected to plasma etching. Then, a metal connection layer 5 is formed on the surface of the impedance adjusting layer 3 and the surface of the solder joint 4. Alternatively, the method for forming the metal connection layer 5 includes, but is not limited to, magnetron sputtering, electroplating, evaporation, deposition, and the like. And then removing the metal connecting layer 5 sputtered on the whole surface by using a chemical agent, only keeping the metal connecting layer 5 at the welding point 4, and finally performing reflow soldering to obtain the copper bump 6 on the welding point 4.
In some embodiments, after the copper bump 6 is processed, a thinning process is performed on the package structure. Specifically, a protective film is pasted on one surface of the surface with the package to protect the front surface of the chip, then the package structure is placed on a grinding machine, the thick sheet is thinned to the target thickness, and finally the protective film is removed to obtain the thinned wafer.
In some embodiments, after the copper bump 6 process is completed, a dicing process is further performed on the package structure. Specifically, a scribing film is pasted on the surface of the high-resistance silicon substrate 1 far away from the packaging surface, and then the whole wafer is cut into single chips by a scribing knife through a scribing machine.
In some embodiments, after the copper bump 6 process is completed, a Flip-chip FC process is performed on the package structure. Specifically, the Die is picked up from the high-resistance silicon substrate 1wafer by the chip flip-chip tool, is attached to the substrate pad by turning 180 degrees, and is reflowed by reflow soldering, so that the bumps of the chip are soldered to the substrate pad.
In the embodiment of the present application, after the high-resistance silicon substrate 1 is packaged, a reliability experiment is usually required to verify the reliability and related parameters of the product, so as to ensure that the product test data meets the requirements of various aspects. The reliability experiments included high and low temperature tests. As an alternative embodiment, the specific test procedure is as follows: the temperature parameter range of the high-temperature and low-temperature experiments is-65-150 ℃, and the chip is impacted for preset times through a cold-hot impact tester, wherein the preset times are 1000cys optionally. Performing according to an operation standard book of a cold and hot impact testing machine, taking a plurality of pretreated chips, placing the chips on a grid plate in a cold and hot impact box, setting experiment parameters of-65 ℃/150 ℃ and 1000cys, rapidly heating from-65 ℃ to 150 ℃ at room temperature, heating to 150 ℃ within 5min, keeping for 10min, then cooling to room temperature within 5min at 150 ℃, cooling to 5min to-65 ℃ at room temperature, keeping for 10min, and circulating for 1000 times. Generally, in a high and low temperature test of a chip, a high-resistance silicon wafer often has a structural delamination problem, and after a layer of impedance adjusting layer 3 is manufactured on a packaging surface of a high-resistance silicon substrate 1, the impedance adjusting layer can be used as a buffer layer to suppress internal stress of the high-resistance silicon wafer, so that the structural delamination problem of the high-resistance silicon wafer in the high and low temperature test of the chip is improved, and the reliability of the high-resistance silicon chip is improved.
The embodiment of the application provides a packaging structure, and the packaging structure is obtained by packaging with the packaging method.
In the embodiment of the application, the packaging structure is prepared by the packaging method. Fig. 3 is a schematic structural diagram of a package structure provided in an embodiment of the present application, and as shown in fig. 3, the package structure includes a high-resistance silicon substrate 1, where a pad is disposed on the high-resistance silicon substrate 1, and the pad includes a plurality of solder joints 4. The surface of the high-resistance silicon substrate 1 is also provided with a protective layer 2, the protective layer 2 is provided with a protective layer 2 opening, and the protective layer 2 opening is used for exposing the welding spot 4 out of the protective layer 2. The protective layer 2 is provided with a resistance adjustment layer 3, and optionally, the thickness of the resistance adjustment layer 3 is 5 μm to 10 μm. The impedance adjusting layer 3 is used for adjusting the surface layer resistivity of the high-resistance silicon substrate 1, and can improve the radio frequency self-bias voltage when the radio frequency etching equipment etches the high-resistance silicon substrate 1. An opening of the impedance adjusting layer 3 is formed in the impedance adjusting layer 3, and the opening of the impedance adjusting layer 3 is used for enabling the welding spot 4 to be exposed out of the protective layer 2. The solder joint 4 is provided with a copper bump 6 for electrical connection with other chip structures.
An embodiment of the present application provides an electronic device, which includes the package structure described above.
In the embodiment of the present application, the electronic device is a device having an integrated passive device, and the integrated passive device is a high-resistance silicon integrated passive device, that is, the integrated passive device includes the package structure as described above.
According to the packaging method, the packaging structure and the electronic equipment, the impedance adjusting layer is firstly covered on the surface of the high-resistance silicon substrate, so that the etching of the surface oxidation layer 7 of the welding spot is guaranteed, the adhesion between the copper bump layer and the welding spot is improved, the electric conductivity between the copper bump and the chip is guaranteed, the reliability of the chip is improved, and the packaging of the high-resistance silicon wafer is realized. Moreover, the surface of the high-resistance silicon substrate is covered with the impedance adjusting layer made of soft materials, so that the buffer effect is increased in the later process procedure, and the stability of the chip is improved. In addition, the impedance adjusting layer is added in the packaging structure of the high-resistance silicon substrate, so that the problem of structural layering of a high-resistance silicon wafer in a high-low temperature experiment of a chip can be solved, and the reliability of the high-resistance silicon chip is improved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method of packaging, comprising:
obtaining a substrate to be packaged; the substrate to be packaged comprises a high-resistance silicon substrate (1); the high-resistance silicon substrate (1) is provided with a packaging surface, and welding spots (4) are arranged on the packaging surface; the surface of the welding spot (4) far away from the high-resistance silicon substrate (1) is provided with a surface oxidation layer (7);
manufacturing an impedance adjusting layer (3) on the surface of the package; the impedance adjusting layer (3) is used for reducing the surface resistivity of the high-resistance silicon substrate (1);
and etching to remove the surface oxidation layer (7) to obtain the packaging structure.
2. The encapsulation method according to claim 1, wherein the resistivity of the impedance adjustment layer (3) is smaller than the resistivity of the high-resistance silicon substrate (1).
3. The method according to claim 2, wherein the material of the impedance adjusting layer (3) is polyimide.
4. The encapsulation method according to claim 3, wherein the thickness of the resistance adjustment layer (3) is 5 μm to 10 μm.
5. The encapsulation method according to claim 3, wherein the fabricating of the impedance adjusting layer (3) on the encapsulation surface comprises:
coating a polyimide photoresist layer on the packaging surface;
carrying out graphical processing on the polyimide photoresist layer;
and curing the polyimide photoresist layer after the patterning treatment to obtain the impedance adjusting layer (3).
6. The packaging method according to claim 1, wherein after the etching to remove the surface oxide layer (7) and obtain the package structure, the method further comprises:
and manufacturing a metal electrode on the surface of the welding spot (4) after the surface oxidation layer (7) is removed.
7. The packaging method according to claim 6, wherein the step of forming a metal electrode on the surface of the solder joint (4) after removing the surface oxide layer (7) comprises:
manufacturing a metal connecting layer (5) on the surface of the welding spot (4) after the surface oxidation layer (7) is removed;
and manufacturing the metal electrode on the metal connecting layer (5).
8. The encapsulation method according to claim 7, wherein the metal connection layer (5) is made of titanium or a composite of titanium and copper.
9. A package structure, characterized in that the package structure is obtained by packaging according to the packaging method of any one of claims 1 to 9.
10. An electronic device, characterized in that the electronic device comprises the encapsulation structure according to claim 9.
CN202210532286.2A 2022-05-09 2022-05-09 Packaging method, packaging structure and electronic equipment Pending CN114927495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210532286.2A CN114927495A (en) 2022-05-09 2022-05-09 Packaging method, packaging structure and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210532286.2A CN114927495A (en) 2022-05-09 2022-05-09 Packaging method, packaging structure and electronic equipment

Publications (1)

Publication Number Publication Date
CN114927495A true CN114927495A (en) 2022-08-19

Family

ID=82808932

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210532286.2A Pending CN114927495A (en) 2022-05-09 2022-05-09 Packaging method, packaging structure and electronic equipment

Country Status (1)

Country Link
CN (1) CN114927495A (en)

Similar Documents

Publication Publication Date Title
US11488878B2 (en) Packaging mechanisms for dies with different sizes of connectors
TWI229890B (en) Semiconductor device and method of manufacturing same
JP3895595B2 (en) Method for vertically integrating electrical components by back contact
US9893047B2 (en) Manufacture of wafer—panel die package assembly technology
US8012798B2 (en) Method of fabricating stacked semiconductor chips
US20120119391A1 (en) Semiconductor package and manufacturing method thereof
US20080105952A1 (en) Manufacturing method of semiconductor chips and semiconductor device having the semiconductor chips
JP2003347441A (en) Semiconductor element, semiconductor device, and method for producing semiconductor element
TW200830502A (en) Structure of super thin chip scale package and method of the same
TW200419737A (en) Method of making electronic element-mounted substrate
JP4115326B2 (en) Manufacturing method of semiconductor package
JP2021197430A (en) Method for manufacturing semiconductor device
TW201215269A (en) Wiring substrate manufacturing method
US9685376B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2015018870A (en) Semiconductor device manufacturing method
TW202201673A (en) Semiconductor devices and methods of manufacturing semiconductor devices
JP2005353837A (en) Semiconductor device and its manufacturing method
CN114927495A (en) Packaging method, packaging structure and electronic equipment
Yoon et al. Reliability of a silicon stacked module for 3-D SiP microsystem
JP2004087661A (en) Chip-shaped electronic component and method for manufacturing the same and pseudo wafer used for its manufacturing and method for manufacturing the same, and mounting structure
JPH11145174A (en) Semiconductor and manufacture of the same
JPH09148333A (en) Semiconductor device and manufacturing method
JP7501133B2 (en) Semiconductor device manufacturing method
TW564530B (en) Circuit board for flip-chip semiconductor package and fabrication method thereof
JP7347440B2 (en) Manufacturing method of wiring board for semiconductor package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination