JP2021197430A - Method for manufacturing semiconductor device - Google Patents

Abstract

To provide a method capable of reducing bonding failures while finely bonding a semiconductor chip in three-dimensional mounting of the semiconductor chip.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: polishing at least one surface side of a first semiconductor substrate or one surface side of a second semiconductor substrate; individualizing the second semiconductor substrate and acquiring a plurality of semiconductor chips each of which includes an insulation film portion corresponding to a second insulation film and at least one second electrode; positioning the second electrode of at least one semiconductor chip among the plurality of semiconductor chips at the first electrode of the first semiconductor substrate; sticking the first insulation film of the first semiconductor substrate and the insulation film portion of the semiconductor chip to each other; and bonding the first electrode of the first semiconductor substrate and the second electrode of the semiconductor chip. At least one insulation film of the first insulation film and the second insulation film includes an organic material.SELECTED DRAWING: Figure 2

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an individualized semiconductor chip is bonded to a semiconductor substrate (another semiconductor chip, a semiconductor wafer, or the like).

In recent years, three-dimensional mounting has been studied in order to improve the degree of integration of LSI. Non-Patent Document 1 discloses an example of three-dimensional mounting of a semiconductor chip.

F.C. Chen et al., “Systemon Integrated Chips (SoIC TM) for 3D Heterogeneous Integration”, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), p.594-599 (2019)

When mounting such a semiconductor chip in three dimensions, it is possible to use the hybrid bonding technology used for Wafer-to-Wafer (W2W) bonding in order to finely bond the wiring between devices and prevent misalignment during bonding. It is being considered. However, when mounting a semiconductor chip three-dimensionally, unlike W2W, foreign matter (cutting debris) may be generated in the process of individualizing the semiconductor chip, and this foreign matter is the junction interface (hybrid) of the semiconductor chip or the like. There is a risk that it will adhere to the bonding insulating film). An inorganic material such as silicon oxide (SiO ₂ ) is generally used for this insulating film, but since it is a hard material, foreign matter adhered to the insulating film has a large void, for example, nearly 1000 times the height of the foreign matter. It creates a gap of diameter in the direction of the junction interface. Therefore, even if the hybrid bonding technique used for W2W is simply applied to three-dimensional mounting of a semiconductor chip, there is a possibility that such voids may cause bonding defects. On the other hand, when a clean room and equipment having high cleanliness are used in order to prevent these joining defects, a large amount of cost is required due to capital investment in a claim room and the like.

Therefore, an object of the present invention is to provide a method for reducing bonding defects while performing fine bonding of semiconductor chips in the case of three-dimensional mounting of semiconductor chips.

The method for manufacturing a semiconductor device according to one aspect of the present invention is a step of preparing a first semiconductor substrate having a first substrate main body and a first insulating film and a first electrode provided on one surface of the first substrate main body. And a step of preparing a second semiconductor substrate having a second substrate main body, a second insulating film provided on one surface of the second substrate main body, and a plurality of second electrodes, one surface side of the first semiconductor substrate, and A plurality of steps of polishing at least one side of the second semiconductor substrate, and a plurality of pieces of the second semiconductor substrate having an insulating film portion corresponding to the second insulating film and at least one second electrode. A step of acquiring a semiconductor chip, a step of aligning a second electrode of at least one semiconductor chip among a plurality of semiconductor chips with respect to a first electrode of the first semiconductor substrate, and a first step of the first semiconductor substrate. The present invention includes a step of bonding the insulating film and the insulating film portion of the semiconductor chip to each other, and a step of joining the first electrode of the first semiconductor substrate and the second electrode of the semiconductor chip. In this manufacturing method, at least one of the first insulating film and the second insulating film contains an organic material.

In the above manufacturing method, at least one insulating film of the insulating film of the first semiconductor substrate and the insulating film of the second semiconductor substrate (semiconductor chip) is configured to contain an organic material. Organic materials generally have a lower elastic modulus than inorganic materials, and by using such a soft material as the insulating film for hybrid bonding, foreign matter generated by dicing during individualization into semiconductor chips becomes the insulating film. Even if it adheres, the insulating film around the foreign matter is easily deformed, and the foreign matter can be included in the organic material without forming large voids in the insulating film. That is, it is possible to suppress the influence of foreign substances by the insulating film containing an organic material. Therefore, according to the above manufacturing method, it is possible to reduce bonding defects while performing fine bonding of semiconductor chips. Although the manufacturing method is not limited to this, the above method can reduce joining defects, so that it is not necessary to use a clean room and a device having high cleanliness to prevent joining defects. Therefore, the limitation of the manufacturing place of the above-mentioned semiconductor device becomes loose.

In the above manufacturing method, in the polishing step, a CMP method is used so that the surface of the first electrode has the same height as the surface of the first insulating film or is recessed with respect to the surface of the first insulating film. One side of the first semiconductor substrate may be polished. Further, in the polishing step, the CMP method is used so that each surface of the plurality of second electrodes has the same height as the surface of the second insulating film or is recessed with respect to the surface of the second insulating film. One side of the second semiconductor substrate may be polished. By performing such polishing, it is possible to prevent the first electrode and the second electrode from coming into contact with each other first in the step of bonding the insulating films, and the first insulating film of the first semiconductor substrate and the semiconductor chip are prevented from coming into contact with each other. It is possible to more reliably execute the step of bonding the insulating film portions of the above to each other.

In the above manufacturing method, in the bonding step, the insulating film portion of the semiconductor chip is used as the first insulating film of the first semiconductor substrate at a temperature at which the temperature difference between the semiconductor chip and the first semiconductor substrate is within 10 ° C. or at room temperature. It may be joined. In this case, the semiconductor chip can be bonded to the first semiconductor substrate while suppressing the positional deviation. Further, even if the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip are made of different materials, they can be bonded.

In the above manufacturing method, the elastic modulus of the organic material contained in at least one of the first insulating film and the second insulating film may be 7.0 GPa or less. In this case, even if foreign matter generated by dicing at the time of individualization into a semiconductor chip adheres to the bonding interface, these foreign substances are more reliably contained in the organic material without causing large voids, resulting in bonding failure. It can be further reduced. The elastic modulus of the above organic material is preferably 5.0 GPa or less, and more preferably 2.0 GPa or less. The elastic modulus here means Young's modulus.

In the above manufacturing method, the coefficient of thermal expansion in the thickness direction of the organic material contained in at least one of the first insulating film and the second insulating film may be 70 ppm / k or less, more preferably 50 ppm / k or less. You may. In this case, the coefficient of thermal expansion of the organic material becomes equal to or close to the coefficient of thermal expansion of the first electrode and the second electrode, and when heat is applied, the difference in thermal expansion between the insulating layer and the electrode becomes close. , Bonding defects can be further reduced. The organic material specified here may have the elastic modulus described above, or may have an elastic modulus different from the elastic modulus described above.

In the above manufacturing method, the organic material contained in the second insulating film may have a polishing rate of 5 times or less the polishing rate of the metal material constituting the second electrode. For example, when the polishing rate of the metal material constituting the second electrode is 50 nm / min, the polishing rate of the organic material contained in the second insulating film is preferably 200 nm / min or less (4 times or less). It is more preferably 100 nm / min or less (twice or less), and even more preferably 50 nm / min or less (equivalent or less). When there is such a polishing rate relationship, it becomes easy to perform the work of polishing the second insulating film containing the organic material and the second electrode, and the polishing process can be simplified. The relationship between the polishing rate of the first insulating film and the first electrode may be the same as described above.

In the above production method, the organic material contained in at least one of the first insulating film and the second insulating film is polyimide, a polyimide precursor (for example, polyimiamic ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), poly. It may contain benzoxazole (PBO), or PBO precursor. Further, the organic material contained in at least one of the first insulating film and the second insulating film may include a photosensitive resin, a thermosetting non-conductive film, or a thermosetting resin. When a photosensitive resin is used, it is possible to simplify the manufacturing process of the connection electrode. Further, when a thermosetting non-conductive film is used, it is possible to shorten the time required for the process of producing the insulating layer.

In the above manufacturing method, the thickness of the second insulating film may be thicker than the thickness of the first insulating film. In this case, most of the foreign matter adhering to the bonding interface when the semiconductor chip is fragmented or mounted on the chip can be included by the second insulating film, and the bonding failure can be further reduced. On the other hand, the thickness of the second insulating film may be thinner than the thickness of the first insulating film. In this case, the height of the mounted semiconductor chip can be reduced. The thickness of the first insulating film and the second insulating film may be determined according to the height of the corresponding electrodes.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a method for reducing bonding defects while performing fine bonding of semiconductor chips in the case of three-dimensional mounting of semiconductor chips.

FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram showing in order a method for manufacturing the semiconductor device shown in FIG. FIG. 3 is a diagram showing in more detail the joining method in the manufacturing method of the semiconductor device shown in FIG. FIG. 4 is a method for manufacturing the semiconductor device shown in FIG. 1, and is a diagram showing steps after the steps shown in FIG. 2 in order. FIG. 5 is a diagram showing an example in which the method for manufacturing a semiconductor device according to an embodiment of the present invention is applied to a Chip-to-Wafer (C2W).

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts will be designated by the same reference numerals, and duplicate description will be omitted. In addition, the positional relationship such as up, down, left, and right shall be based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the ratios shown.

(Semiconductor device configuration)
FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device manufactured by the manufacturing method according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 is an example of a semiconductor package, for example, a first semiconductor chip 10 (first semiconductor substrate), a second semiconductor chip 20 (semiconductor chip), a pillar portion 30, and a rewiring layer 40. , A substrate 50, and a circuit substrate 60.

The first semiconductor chip 10 is, for example, an LSI (Large scale Integrated Circuit) chip or a semiconductor chip such as a CMOS (Complementary Metal Oxide Semiconductor) sensor, and the second semiconductor chip 20 is in the vertical direction (lower side in the height direction). It has a three-dimensional mounting structure implemented in. The second semiconductor chip 20 is, for example, a semiconductor chip such as an LSI or a memory, and is a chip component having a smaller area in a plan view than the first semiconductor chip 10. The second semiconductor chip 20 is Chip-to-Chip (C2C) bonded to the back surface of the first semiconductor chip 10. The first semiconductor chip 10 and the second semiconductor chip 20 are finely bonded to each other by hybrid bonding, which will be described in detail later, so that the respective terminal electrodes and the insulating films around the terminal electrodes are firmly and without displacement.

The pillar portion 30 is a connecting portion in which a plurality of pillars 31 formed of, for example, copper (Cu) are sealed with a resin 32. The plurality of pillars 31 are conductive members extending from the upper surface to the lower surface of the pillar portion 30, and have, for example, a cylindrical shape having a diameter of 3 μm or more and 20 μm or less (in one example, a diameter of 5 μm), and have a central pitch between the pillars 31. May be arranged so as to be 15 μm or less. The plurality of pillars 31 flip-chip connect the lower terminal electrode of the first semiconductor chip 10 and the upper terminal electrode of the rewiring layer 40. By using the pillar portion 30, the semiconductor device 1 can form a connection electrode without using a technique called TMV (Through mold via) in which a hole is formed in a mold and soldered. The pillar portion 30 has, for example, a thickness similar to that of the second semiconductor chip 20, and is arranged on the lateral side of the second semiconductor chip 20 in the horizontal direction. The portion may be composed of a plurality of solder balls instead of the pillar portion 30, and the solder balls electrically connect the lower terminal electrode of the first semiconductor chip 10 and the upper terminal electrode of the rewiring layer 40. It may be configured to connect to.

The rewiring layer 40 is a wiring layer having a terminal pitch conversion function, which is a function of the package substrate, and is made of polyimide, copper wiring, or the like on the insulating film under the second semiconductor chip 20 and on the lower surface of the pillar portion 30. It is a layer in which a rewiring pattern is formed. The rewiring layer 40 is formed in a state where the first semiconductor chip 10 and the second semiconductor chip 20 are turned upside down (see (d) in FIG. 4). The rewiring layer 40 electrically connects the terminal electrodes on the lower surface of the second semiconductor chip 20 and the terminal electrodes of the first semiconductor chip 10 via the pillar portion 30 to the terminal electrodes of the substrate 50. The terminal pitch of the substrate 50 is wider than the terminal pitch of the first semiconductor chip 10 (pillar 31) and the second semiconductor chip 20. Various electronic components 51 may be mounted on the substrate 50. Further, if there is a large difference in the terminal pitch between the rewiring layer 40 and the substrate 50, an inorganic interposer or the like may be used here to electrically connect the rewiring layer 40 and the substrate 50.

The circuit board 60 mounts the first semiconductor chip 10 and the second semiconductor chip 20 on it, and is electrically connected to the board 50 connected to the first semiconductor chip 10, the second semiconductor chip 20, the electronic component 51, and the like. It is a substrate having a plurality of through electrodes to be formed inside. In the circuit board 60, the terminal electrodes of the first semiconductor chip 10 and the second semiconductor chip are electrically connected to the terminal electrodes 61 provided on the back surface of the circuit board 60 by these through electrodes.

(Manufacturing method of semiconductor device)
Next, the manufacturing method of the semiconductor device 1 will be described with reference to FIGS. 2 to 4. FIG. 2 is a diagram showing in order a method for manufacturing the semiconductor device shown in FIG. FIG. 3 is a diagram showing in more detail the bonding method (hybrid bonding) in the method for manufacturing the semiconductor device shown in FIG. 2. FIG. 4 is a method for manufacturing the semiconductor device shown in FIG. 1, and is a diagram showing steps after the steps shown in FIG. 2 in order.

The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (p).
(A) A step of preparing a first semiconductor substrate 100 corresponding to the first semiconductor chip 10.
(B) A step of preparing a second semiconductor substrate 200 corresponding to the second semiconductor chip 20.
(C) A step of polishing the first semiconductor substrate 100.
(D) A step of polishing the second semiconductor substrate 200.
(E) A step of disassembling the second semiconductor substrate 200 and acquiring a plurality of semiconductor chips 205.
(F) A step of aligning the terminal electrodes 203 of each of the plurality of semiconductor chips 205 with respect to the terminal electrodes 103 of the first semiconductor substrate 100.
(G) A step of bonding the insulating film 102 of the first semiconductor substrate 100 and the insulating film portions 202b of the plurality of semiconductor chips 205 to each other (see (b) in FIG. 3).
(H) A step of joining the terminal electrode 103 of the first semiconductor substrate 100 and the terminal electrode 203 of each of the plurality of semiconductor chips 205 (see (c) in FIG. 3).
(I) A step of forming a plurality of pillars 300 (corresponding to pillars 31) between a plurality of semiconductor chips 205 on the connection surface of the first semiconductor substrate 100.
(J) A step of molding a resin 301 on a connection surface of a first semiconductor substrate 100 so as to cover the semiconductor chip 205 and the pillar 300 to obtain a semi-finished product M1.
(K) A step of grinding and thinning the upper part of the semi-finished product M1 molded in the step (j) to obtain the semi-finished product M2.
(M) A step of forming a wiring layer 400 corresponding to the rewiring layer 40 on the semi-finished product M2 thinned in the step (k).
(N) A step of cutting the semi-finished product M3 on which the wiring layer 400 is formed in the step (m) along the cutting line A so as to be each semiconductor device 1.
(P) A step of inverting the semiconductor device 1a individualized in step (n) and installing it on the substrate 50 and the circuit board 60 (see FIG. 1).

[Step (a) and Step (b)]
The step (a) is a step of preparing a first semiconductor substrate 100, which is a silicon substrate corresponding to a plurality of first semiconductor chips 10 and in which an integrated circuit including semiconductor elements and wirings connecting them is formed. In the step (a), as shown in FIG. 2A, a plurality of terminal electrodes 103 (first electrodes) made of copper, aluminum, or the like are designated on one surface 101a of the first substrate main body 101 made of silicon or the like. An insulating film 102 (first insulating film) made of an organic material is provided at intervals. A plurality of terminal electrodes 103 may be provided after the insulating film 102 is provided on one surface 101a of the first substrate main body 101, or a plurality of terminal electrodes 103 may be provided on one surface 101a of the first substrate main body 101 and then the insulating film. 102 may be provided. A predetermined interval is provided between the plurality of terminal electrodes 103 in order to form the pillar 300 in a step described later, and another terminal electrode (not shown) connected to the pillar 300 is provided between the plurality of terminal electrodes 103. It is formed.

The step (b) is a step of preparing a second semiconductor substrate 200, which is a silicon substrate corresponding to a plurality of second semiconductor chips 20 and in which an integrated circuit including semiconductor elements and wirings connecting them is formed. In the step (b), as shown in FIG. 2A, a plurality of terminal electrodes 203 (a plurality of second electrodes) made of copper, aluminum, or the like are placed on one surface 201a of the second substrate body 201 made of silicon or the like. Is continuously provided and an insulating film 202 (second insulating film) made of an organic material is provided. A plurality of terminal electrodes 203 may be provided after the insulating film 202 is provided on one surface 201a of the second substrate main body 201, or a plurality of terminal electrodes 203 may be provided on one surface 201a of the second substrate main body 201 and then the insulating film 202. May be provided.

As described above, the insulating films 102 and 202 used in the steps (a) and (b) are made of an organic material. The organic material comprises, for example, polyimide, a polyimide precursor (eg, polyimiamic ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or PBO precursor. It has a lower elastic coefficient than inorganic materials such as silicon oxide (SiO _2). The elastic modulus of the organic material constituting the insulating films 102 and 202 is, for example, 7.0 GPa or less, preferably 5.0 GPa or less or 3.0 GPa or less, and more preferably 2.0 GPa or less or 1.5 GPa or less. be. The elastic modulus here means Young's modulus.

Further, the organic materials constituting the insulating films 102 and 202 preferably have a coefficient of thermal expansion of 70 ppm / k or less, and more preferably 50 ppm / k or less.

Further, the organic material constituting the insulating films 102 and 202 may have a polishing rate of 5 times or less the polishing rate of the metal material (for example, copper or aluminum) constituting the corresponding terminal electrode 103 or 203. For example, when the metal material constituting the terminal electrode 103 or 203 is copper and the polishing rate thereof is 50 nm / min, the polishing rate of the organic material constituting the insulating films 102 and 202 is 200 nm / min or less (4 times or less). ), More preferably 100 nm / min or less (twice or less), and even more preferably 50 nm / min or less (equivalent or less).

As the organic material constituting the insulating films 102 and 202, a photosensitive resin, a thermosetting non-conductive film (NCF), or a thermosetting resin may be used. This organic material may be an underfill material. Further, the organic material constituting the insulating films 102 and 202 may be a heat-resistant resin.

[Step (c) and Step (d)]
The step (c) is a step of polishing the first semiconductor substrate 100. In the step (c), as shown in FIG. 3A, the CMP is such that each surface 103a of the terminal electrode 103 is at an equivalent position or a slightly lower (recessed) position with respect to the surface 102a of the insulating film 102. The one side 101a, which is the surface of the first semiconductor substrate 100, can be polished by using the (Chemical Mechanical Polishing) method. In the step (c), the first semiconductor substrate 100 can be polished by the CMP method under the condition that the terminal electrode 103 made of, for example, copper or the like is selectively deeply cut. In the step (c), each surface 103a of the terminal electrode 103 may be polished by the CMP method so as to coincide with the surface 102a of the insulating film 102.

The step (d) is a step of polishing the second semiconductor substrate 200. In the step (d), as shown in FIG. 3A, each surface 203a of the terminal electrode 203 is at the same position or slightly lower (recessed) position with respect to the surface 202a of the insulating film 202. It is also possible to polish one side 201a, which is the surface of the second semiconductor substrate 200, by using the CMP method. In the step (d), the second semiconductor substrate 200 is polished by the CMP method under the condition that the terminal electrode 203 made of, for example, copper or the like is selectively deeply cut. In the step (d), each surface 203a of the terminal electrode 203 may be polished by the CMP method so as to coincide with the surface 202a of the insulating film 202.

In the steps (c) and (d), the insulating film 102 may be polished so that the thickness of the insulating film 102 and the thickness of the insulating film 202 are the same. For example, the thickness of the insulating film 202 is the thickness of the insulating film 102. It may be polished to be thicker than the halfbeak. On the other hand, the insulating film 202 may be polished so as to be thinner than the thickness of the insulating film 102. When the thickness of the insulating film 202 is thicker than the thickness of the insulating film 102, the insulating film 202 can contain most of the foreign matter adhering to the bonding interface when the semiconductor chip 205 is separated into pieces or when the chip is mounted. , Bonding defects can be further reduced. On the other hand, when the thickness of the insulating film 202 is thinner than the thickness of the insulating film 102, the height of the mounted semiconductor chip 205, that is, the semiconductor device 1 can be reduced.

[Step (e)]
The step (e) is a step of disassembling the second semiconductor substrate 200 and acquiring a plurality of semiconductor chips 205. In the step (e), as shown in FIG. 2B, the second semiconductor substrate 200 is separated into a plurality of semiconductor chips 205 by cutting means such as dicing. When dicing the second semiconductor substrate 200, the insulating film 202 may be coated with a protective material or the like, and then individualized. In the step (e), the insulating film 202 of the second semiconductor substrate 200 is divided into the insulating film portion 202b corresponding to each semiconductor chip 205. As a dicing method for individualizing the second semiconductor substrate 200, for example, plasma dicing, stealth dicing or laser dicing can be used. Further, as the surface protective material of the second semiconductor substrate 200 at the time of dicing, for example, a thin film such as an organic film that can be removed by water or TMAH or a carbon film that can be removed by plasma or the like may be provided.

[Step (f)]
The step (f) is a step of aligning the terminal electrodes 203 of each of the plurality of semiconductor chips 205 with respect to the terminal electrodes 103 of the first semiconductor substrate 100. In the step (f), as shown in FIG. 2 (c), the terminal electrodes 203 of the semiconductor chips 205 face each of the corresponding terminal electrodes 103 of the first semiconductor substrate 100. Perform alignment. For this alignment, an alliance mark or the like may be provided on the first semiconductor substrate 100.

[Step (g)]
The step (g) is a step of bonding the insulating film 102 of the first semiconductor substrate 100 and the insulating film portions 202b of the plurality of semiconductor chips 205 to each other. In step (g), after removing organic substances or metal oxides adhering to the surface of each semiconductor chip 205, the semiconductor chip 205 is aligned with the first semiconductor substrate 100 as shown in FIG. 2 (c). When this is completed, the insulating film portions 202b of each of the plurality of semiconductor chips 205 are bonded to the insulating film 102 of the first semiconductor substrate 100 as hybrid bonding (see (b) in FIG. 3). At this time, the insulating film portions of the plurality of semiconductor chips 205 and the insulating film 102 of the first semiconductor substrate 100 may be uniformly heated before joining. The temperature difference between the semiconductor chip 205 and the first semiconductor substrate 100 at the time of joining is preferably, for example, 10 ° C. or less. By heat bonding at such a uniform temperature, the insulating film 102 and the insulating film portion 202b are bonded to form an insulating bonding portion S1, and a plurality of semiconductor chips 205 are mechanically and firmly attached to the first semiconductor substrate 100. Will be. Further, since the heat bonding is performed at a uniform temperature, positional deviation or the like at the bonding portion is unlikely to occur, and high-precision bonding can be performed. At this mounting stage, the terminal electrode 103 of the first semiconductor substrate 100 and the terminal electrode 203 of the semiconductor chip 205 are separated from each other and are not connected (however, they are aligned). The semiconductor chip 205 may be bonded to the first semiconductor substrate 100 by another bonding method, for example, bonding at room temperature or the like.

[Step (h)]
The step (h) is a step of joining the terminal electrode 103 of the first semiconductor substrate 100 and the terminal electrode 203 of each of the plurality of semiconductor chips 205. In the step (h), as shown in (d) of FIG. 2, when the bonding of the step (g) is completed, a predetermined heat H and / or pressure is applied to the first semiconductor substrate 100 as hybrid bonding. The terminal electrode 103 of the above is bonded to each terminal electrode 203 of the plurality of semiconductor chips 205 (see (c) in FIG. 3). When the terminal electrodes 103 and 20 are made of copper, the annealing temperature in the step (g) is preferably 150 ° C. or higher and 400 ° C. or lower, and more preferably 200 ° C. or higher and 300 ° C. or lower. By such a bonding process, the terminal electrode 103 and the corresponding terminal electrode 203 are bonded to each other to form an electrode bonding portion S2, and the terminal electrode 103 and the terminal electrode 203 are mechanically and electrically firmly bonded. The electrode bonding in the step (h) is performed after the bonding in the step (g), but may be performed at the same time as the bonding in the step (g).

As described above, a plurality of semiconductor chips 205 are electrically and mechanically installed at predetermined positions on the first semiconductor substrate 100 with high accuracy. In addition, for example, a product reliability test (connection test or the like) may be performed at the stage of the semi-finished product shown in FIG. 2 (d), and only a non-defective product may be used in the subsequent steps. Subsequently, a manufacturing method of an example of a semiconductor device using such a semi-finished product will be described with reference to FIG.

[Step (i)]
The step (i) is a step of forming a plurality of pillars 300 between the plurality of semiconductor chips 205 on the connection surface 100a of the first semiconductor substrate 100. In step (i), as shown in FIG. 4A, a large number of pillars 300 made of copper, for example, are formed between the plurality of semiconductor chips 205. The pillars 300 can be formed from, for example, copper plating, conductor paste or copper pins. The pillar 300 is formed so that one end is connected to a terminal electrode of the terminal electrode of the first semiconductor substrate 100 that is not connected to the terminal electrode 203 of the semiconductor chip 205, and the other end extends upward. The pillar 300 has, for example, a diameter of 10 μm or more and 100 μm or less, and a height of 10 μm or more and 1000 μm or less. In addition, for example, one or more and 10,000 or less pillars 300 may be provided between the pair of semiconductor chips 205.

[Step (j)]
The step (j) is a step of molding the resin 301 on the connection surface 100a of the first semiconductor substrate 100 so as to cover the plurality of semiconductor chips 205 and the plurality of pillars 300. In the step (j), as shown in FIG. 4 (b), for example, an epoxy resin or the like is molded to cover the plurality of semiconductor chips 205 and the plurality of pillars 300 as a whole. As a molding method, for example, a compression mold or a transfer mold can be used, or a film-shaped epoxy film may be laminated. By this resin mold, the space between the plurality of pillars 300 and the space between the pillars 300 and the semiconductor chip 205 are filled with the resin. As a result, the semi-finished product M1 filled with the resin is formed. It should be noted that the curing treatment may be performed after molding the epoxy resin or the like. Further, when the step (i) and the step (j) are performed substantially at the same time, that is, when the pillar 300 is also formed at the timing of resin molding, the pillar is formed by using imprint which is a fine transfer and conductive paste or electrolytic plating. It may be formed.

[Step (k)]
The step (k) is a step of grinding and thinning the semi-finished product M1 composed of the resin 301 molded in the step (j), the plurality of pillars 300, and the plurality of semiconductor chips 205 to obtain the semi-finished product M2. In the step (k), as shown in FIG. 4 (c), the resin-molded first semiconductor substrate 100 or the like is thinned by polishing the upper part of the semi-finished product M1 with a grander or the like to obtain the semi-finished product M2. .. By polishing in the step (k), the thickness of the semiconductor chip 205, the pillar 300 and the resin 301 is reduced to, for example, about several tens of μm, the semiconductor chip 205 has a shape corresponding to the second semiconductor chip 20, and the pillar 300 and the resin 301 are formed. Has a shape corresponding to the pillar portion 30.

[Step (m)]
The step (m) is a step of forming the wiring layer 400 corresponding to the rewiring layer 40 on the semi-finished product M2 thinned in the step (k). In the step (m), as shown in (d) of FIG. 4, a rewiring pattern is formed on the second semiconductor chip 20 and the pillar portion 30 of the ground semi-finished product M2 with polyimide, copper wiring, or the like. As a result, a semi-finished product M3 having a wiring structure in which the terminal pitches of the second semiconductor chip 20 and the pillar portion 30 are widened is formed.

[Step (n) and Step (p)]
The step (n) is a step of cutting the semi-finished product M3 on which the wiring layer 400 is formed in the step (m) along the cutting line A so as to become each semiconductor device 1. In the step (n), as shown in FIG. 4D, the semiconductor device substrate is cut along the cutting line A so as to become each semiconductor device 1 by dicing or the like. After that, in the step (p), the semiconductor device 1a individualized in the step (n) is inverted and installed on the substrate 50 and the circuit board 60, and a plurality of the semiconductor devices 1 shown in FIG. 1 are acquired.

As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, the insulating film 102 of the first semiconductor substrate 100 and the insulating film 202 (insulating film portion 202b) of the second semiconductor substrate 200 (semiconductor chip 205) are organic. It is composed of materials. Organic materials generally have a lower elastic coefficient than inorganic materials, and by using such a soft material as the insulating film for hybrid bonding, it is generated by dicing when the second semiconductor substrate 200 is separated into the semiconductor chip 205. Even if the foreign matter adheres to the insulating film, the insulating film around the foreign matter is easily deformed, and the foreign matter can be contained in the organic material without forming a large void in the insulating film. That is, it is possible to suppress the influence of foreign substances by the insulating film containing an organic material. Therefore, according to the manufacturing method according to the present embodiment, it is possible to reduce bonding defects while performing fine bonding between the first semiconductor substrate 100 and the semiconductor chip 205. When the organic material used for the insulating film is made of a material having a low elastic modulus or has a highly tough resin composition, the semiconductor device 1 manufactured by the above manufacturing method is more reliably prevented from being damaged. be able to.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, in the polishing steps (c) and (d), each surface 103a of the plurality of terminal electrodes 103 has the same height as the surface 102a of the insulating film 102 or is insulated. The one side 101a side of the first semiconductor substrate 100 is polished by using the CMP method so that the position is recessed with respect to the surface 102a of the film 102. Further, the second semiconductor is used by the CMP method so that each surface 203a of the plurality of terminal electrodes 203 has the same height as the surface 202a of the insulating film 202 or is recessed with respect to the surface 202a of the insulating film 202. One side 201a side of the substrate 200 is polished. By performing such polishing, the step (g) of bonding the insulating film 102 of the first semiconductor substrate 100 and the insulating film portions 202b of the semiconductor chip 205 to each other is more reliably executed, and the bonding is performed by hybrid bonding. It is possible to prevent the positional deviation between the electrodes.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, in the bonding step (g), the semiconductor chip 205 is at a temperature at which the temperature difference between the semiconductor chip 205 and the first semiconductor substrate 100 is within 10 ° C., or at room temperature. The insulating film portion 202b of the above is bonded to the first insulating film 102 of the first semiconductor substrate 100. Since such temperature control is performed, it is possible to suppress the positional deviation and bond the plurality of semiconductor chips 205 to the first semiconductor substrate 100.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, the elastic modulus of the organic material constituting the insulating film 102 and the insulating film 202 may be 7.0 GPa or less. In this case, even if foreign matter adheres to the bonding interface at the time of individualization to the semiconductor chip 205 or when the chip is mounted, these foreign substances are included in the organic material without further forming large voids, and the bonding failure is further reduced. can do.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, the coefficient of thermal expansion of the organic material constituting the insulating film 102 and the insulating film 202 may be 70 ppm / k or less. In this case, even if the coefficient of thermal expansion of the organic material constituting the insulating film is equal to or close to the coefficient of thermal expansion of the terminal electrode 103 and the terminal electrode 203, and heat is generated when the semiconductor device 1 is used. The thermal expansion of the insulating layer and the terminal electrode is substantially the same, and damage to the semiconductor device 1 due to the difference in the coefficient of thermal expansion can be prevented.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, the organic material contained in the insulating film 102 may have a polishing rate of 5 times or less the polishing rate of the metal material constituting the terminal electrode 103, and is insulated. The organic material contained in the film 202 may have a polishing rate of 5 times or less the polishing rate of the metal material constituting the terminal electrode 203. In this case, the work in the steps (c) and (d) for polishing the insulating film and the terminal electrode can be facilitated, and the polishing steps (c) and (d) can be simplified.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment. For example, in the above embodiment, in the step shown in FIG. 4, after the step (i) of forming the pillar 300, the step (j) of molding the resin 301 and the step (k) of grinding and thinning the resin 301 and the like are performed. However, the step (j) of molding the resin 301 on the connection surface of the first semiconductor substrate 100 is first performed, and then the step (k) of grinding the resin 301 to a predetermined thickness to make it thinner. After that, the step (i) for forming the pillar 300 may be performed. In this case, the work of scraping the pillar 300 and the like can be reduced, and the material cost can be reduced because the scraped portion of the pillar 300 becomes unnecessary.

Further, in the above embodiment, the example of joining by C2C has been described, but the present invention may be applied to the joining by Chip-to-Wafer (C2W) shown in FIG. In C2W, the semiconductor wafer 410 (first electrode) having the substrate main body 411 (first substrate main body), the insulating film 412 (first insulating film) provided on one surface of the substrate main body 411, and a plurality of terminal electrodes 413 (first electrode). (1 semiconductor substrate) is prepared, and the substrate main body 421 (second substrate main body), the insulating film portion 422 (second insulating film) provided on one surface of the substrate main body 421, and a plurality of terminal electrodes 423 (second electrode) are prepared. A semiconductor substrate (second semiconductor substrate) before fragmentation of a plurality of semiconductor chips 420 having the above is prepared. Then, one side of the semiconductor wafer 410 and one side of the second semiconductor substrate before being fragmented into the semiconductor chip 420 are polished by the CMP method or the like in the same manner as in the above steps (c) and (d). .. After that, the same fragmentation process as in the step (e) is performed on the second semiconductor substrate to acquire a plurality of semiconductor chips 420.

Subsequently, as shown in FIG. 5A, the terminal electrode 423 of the semiconductor chip 420 is aligned with the terminal electrode 413 of the semiconductor wafer 410 (step (f)). Then, the insulating film 412 of the semiconductor wafer 410 and the insulating film portion 422 of the semiconductor chip 420 are bonded to each other (step (g)), and the terminal electrode 413 of the semiconductor wafer 410 and the terminal electrode 423 of the semiconductor chip 420 are bonded to each other. (Step (h)), the semi-finished product shown in FIG. 5 (b) is acquired. As a result, the insulating film 412 and the insulating film portion 422 are joined to form the insulating bonding portion S3, and the semiconductor chip 420 is mechanically firmly and highly accurately attached to the semiconductor wafer 410. Further, the terminal electrode 413 and the corresponding terminal electrode 423 are bonded to each other to form an electrode bonding portion S4, and the terminal electrode 413 and the terminal electrode 423 are mechanically and electrically firmly bonded to each other.

Then, as shown in FIGS. 5 (c) and 5 (d), the semiconductor device 401 is acquired by joining the plurality of semiconductor chips 420 to the semiconductor wafer 410, which is a semiconductor wafer, in the same manner. The plurality of semiconductor chips 420 may be bonded to the semiconductor wafer 410 one by one by hybrid bonding, but may be collectively bonded to the semiconductor wafer 410 by hybrid bonding.

Also in such a manufacturing method of the semiconductor device 401, the insulating film 412 of the semiconductor wafer 410 and the insulating film portion 422 of the semiconductor chip 420 are configured to include the organic material, as in the manufacturing method of the semiconductor device 1 described above. By using such a soft material for the insulating film of hybrid bonding, even if foreign matter generated by dicing at the time of individualization to the semiconductor chip 420 adheres to the insulating film, the insulating film around the foreign matter can be easily formed. Foreign matter can be contained in the organic material without being deformed and forming large voids in the insulating film. That is, it is possible to suppress the influence of foreign substances by the insulating film containing an organic material. Therefore, even in the above-mentioned manufacturing method according to C2W, it is possible to reduce bonding defects while finely bonding the semiconductor wafer 410 and the semiconductor chip 420, as in the case of C2C.

Further, in the above-mentioned method for manufacturing a semiconductor device, the insulating film 102 of the semiconductor substrate 110, the insulating film 202 of the semiconductor chip 205, and the like are made of organic materials, but some of these insulating films contain an inorganic material. You may. That is, as long as there is a portion of the organic material that can contain the above-mentioned foreign matter, the remaining portion of the insulating film may be formed of the inorganic material.

1,1a, 401 ... Semiconductor device, 10 ... First semiconductor chip, 20 ... Second semiconductor chip, 30 ... Pillar part, 40 ... Rewiring layer, 50 ... Board, 60 ... Circuit board, 61 ... Terminal electrode, 100 ... 1st semiconductor substrate, 101 ... 1st substrate main body, 101a ... 1 surface, 102 ... insulating film (1st insulating film), 103 ... terminal electrode (1st electrode), 103a ... surface, 200 ... 2nd semiconductor substrate, 201 ... 2nd substrate body, 201a ... one side, 202 ... insulating film (second insulating film), 203 ... terminal electrode (second electrode), 203a ... surface, 205 ... semiconductor chip, 300 ... pillar, 301 ... resin, 410 ... semiconductor Wafer (first semiconductor substrate), 411 ... substrate body (first substrate body), 412 ... insulating film (first insulating film), 413 ... terminal electrode (first electrode), 420 ... semiconductor chip (second semiconductor substrate) , 421 ... Substrate main body (second substrate main body), 422 ... Insulation film part (second insulating film), 423 ... Terminal electrode (second electrode), A ... Cutting wire, H ... Heat, M1 to M3 ... Semi-finished product, S1 ... Insulated joint portion, S2 ... Electrode joint portion, S3 ... Insulation joint portion, S4 ... Electrode joint portion.

Claims (11)

A step of preparing a first semiconductor substrate having a first substrate main body and a first insulating film and a first electrode provided on one surface of the first substrate main body.
A step of preparing a second semiconductor substrate having a second substrate main body, a second insulating film provided on one surface of the second substrate main body, and a plurality of second electrodes.
A step of polishing at least one of the one-sided side of the first semiconductor substrate and the one-sided side of the second semiconductor substrate.
A step of disassembling the second semiconductor substrate and acquiring a plurality of semiconductor chips each having an insulating film portion corresponding to the second insulating film and at least one second electrode.
A step of aligning the second electrode of at least one of the plurality of semiconductor chips with respect to the first electrode of the first semiconductor substrate.
A step of bonding the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip to each other.
A step of joining the first electrode of the first semiconductor substrate and the second electrode of the semiconductor chip is provided.
At least one of the first insulating film and the second insulating film contains an organic material.
Manufacturing method of semiconductor devices. In the polishing step, the CMP method is used so that the surface of the first electrode has the same height as the surface of the first insulating film or is recessed with respect to the surface of the first insulating film. Polishing the one side of the first semiconductor substrate,
The method for manufacturing a semiconductor device according to claim 1. In the polishing step, the CMP method is performed so that each surface of the plurality of second electrodes has the same height as the surface of the second insulating film or is recessed with respect to the surface of the second insulating film. Use to polish the one side of the second semiconductor substrate.
The method for manufacturing a semiconductor device according to claim 1 or 2. In the bonding step, the insulating film portion of the semiconductor chip is insulated from the first semiconductor substrate at a temperature at which the temperature difference between the semiconductor chip and the first semiconductor substrate is within 10 ° C. or at room temperature. Join to the film,
The method for manufacturing a semiconductor device according to any one of claims 1 to 3. The elastic modulus of the organic material contained in at least one of the first insulating film and the second insulating film is 7.0 GPa or less.
The method for manufacturing a semiconductor device according to any one of claims 1 to 4. The coefficient of thermal expansion of the organic material contained in at least one of the first insulating film and the second insulating film is 70 ppm / k or less.
The method for manufacturing a semiconductor device according to any one of claims 1 to 5. The organic material contained in the second insulating film has a polishing rate of 5 times or less the polishing rate of the metal material constituting the second electrode.
The method for manufacturing a semiconductor device according to any one of claims 1 to 6. The organic material contained in at least one of the first insulating film and the second insulating film includes polyimide, polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or PBO precursor. include,
The method for manufacturing a semiconductor device according to any one of claims 1 to 7. The organic material contained in at least one of the first insulating film and the second insulating film includes a photosensitive resin, a thermosetting non-conductive film, or a thermosetting resin.
The method for manufacturing a semiconductor device according to any one of claims 1 to 7. The thickness of the second insulating film is thicker than the thickness of the first insulating film.
The method for manufacturing a semiconductor device according to any one of claims 1 to 9. The thickness of the second insulating film is thinner than the thickness of the first insulating film.
The method for manufacturing a semiconductor device according to any one of claims 1 to 10.

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