CN114927112B - Control method and control circuit of display panel and display device - Google Patents
Control method and control circuit of display panel and display device Download PDFInfo
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- CN114927112B CN114927112B CN202210546701.XA CN202210546701A CN114927112B CN 114927112 B CN114927112 B CN 114927112B CN 202210546701 A CN202210546701 A CN 202210546701A CN 114927112 B CN114927112 B CN 114927112B
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- 230000001934 delay Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 17
- 239000010409 thin film Substances 0.000 description 14
- 239000000758 substrate Substances 0.000 description 11
- 239000004020 conductor Substances 0.000 description 10
- 230000003111 delayed effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 101150005295 GATA2 gene Proteins 0.000 description 1
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 1
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 1
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 1
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 1
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- 230000002452 interceptive effect Effects 0.000 description 1
- 230000002087 whitening effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Engineering & Computer Science (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a control method, a control circuit and a display device of a display panel. The control method of the display panel comprises the steps of adjusting and outputting a time sequence control signal; and delaying the corresponding gate driving signal according to the regulated time sequence control signal so as to enable the delay of the gate driving signal to be matched with the delay of the data signal output by the source driving circuit. By means of delay matching, the influence caused by delay difference between wires at two ends of the fan-shaped area and wires in the middle of the fan-shaped lead is reduced.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a control method and a control circuit for a display panel, and a display device.
Background
In the display device, data signals are transmitted to each pixel through a Chip On Film (COF) and a data line On an array substrate, so as to display an image.
Specifically, a flip chip film is connected to the data lines of the display area through a set of fan-shaped leads on the substrate. However, since the fan-shaped lead is fan-shaped as a whole, the length of the wires at the two ends of the fan-shaped lead is much longer than that of the wires in the middle of the fan-shaped lead, so that the resistance of the wires at the two ends is much greater than that of the wires in the middle, the waveforms of the data signals transmitted on the wires at the two ends are seriously distorted, color deviation is generated, pixels controlled by the wires at the two ends are in bright spots or dark spots, and the display effect of the display panel is affected.
Disclosure of Invention
The invention aims to provide a control method of a display panel, which aims to delay a corresponding gate driving signal by adjusting a time sequence control signal so as to enable the delay of the gate driving signal to be matched with the delay of a data signal output by a source driving circuit, reduce the influence caused by delay difference between leads at two ends of a sector area and leads in the middle of the sector area and improve the display effect of the display panel.
In order to achieve the above object, the present invention provides a control method of a display panel, the display panel is provided with a gate driving circuit and a pixel array, the gate driving circuit outputs a gate driving signal to the pixel array on the display panel through a scan line, the control method of the display panel comprises:
adjusting and outputting a time sequence control signal;
And delaying the corresponding gate driving signal according to the regulated time sequence control signal so as to enable the delay of the gate driving signal to be matched with the delay of the data signal output by the source driving circuit.
In one embodiment, the step of adjusting and outputting the timing control signal includes:
Maintaining the voltage value of the high level of the time sequence control signal unchanged, and reducing the voltage value of the low level of the time sequence control signal; or alternatively
The voltage value of the low level of the time sequence control signal is kept unchanged, and the voltage value of the high level of the time sequence control signal is reduced.
In one embodiment, the step of adjusting and outputting the timing control signal includes:
while lowering the voltage value of the high level and the voltage value of the low level of the timing control signal.
In an embodiment, after the voltage value of the low level of the timing control signal is reduced, the voltage value of the low level of the timing control signal is less than or equal to minus 5 volts and greater than or equal to minus 14 volts.
In an embodiment, after the voltage value of the high level of the timing control signal is reduced, the voltage value of the high level of the timing control signal is greater than or equal to 31 volts.
In one embodiment, the step of adjusting and outputting the timing control signal includes:
and adjusting the phase of the time sequence control signal to adjust the charging time of the data signal to the pixel unit.
In an embodiment, after the phase of the timing control signal is adjusted, the charging time of the pixel unit by the gate driving signal output by the gate driving circuit is greater than or equal to 1 microsecond and less than or equal to 1.1 microsecond.
The application also provides a control circuit of a display panel, the display panel is provided with a pixel array, the control circuit of the display panel comprises:
the source electrode driving circuit is connected with the pixel array and is used for outputting data signals to the pixel array;
A timing controller for adjusting and outputting a timing control signal;
And the grid driving circuit is connected with the time sequence controller and the pixel array, and delays the corresponding grid driving signal according to the adjusted time sequence control signal so as to enable the delay of the grid driving signal to be matched with the delay of the data signal output by the source driving circuit.
In an embodiment, the control circuit of the display panel further includes:
a gamma circuit configured to output first to nth gamma voltages to the source driving circuit; the difference between the gamma voltage of the N/2 th and the gamma voltage of the (N/2) +1 th is more than 0.5 volt and less than 3.0 volt.
The application also provides a display device, which comprises a display panel and the control circuit of the display panel; the control circuit of the display panel is used for controlling the display panel to work.
According to the application, the time sequence control signals are regulated, and the corresponding gate driving signals are delayed according to the regulated time sequence control signals, so that the delay of the gate driving signals is matched with the delay of the data signals output by the source driving circuit. The delay of the grid driving signal is between the delay of the data signal transmitted on the leads at the two ends of the sector area and the delay of the data signal transmitted on the lead in the middle of the sector area, so that the influence caused by the delay difference between the data signal transmitted on the leads at the two ends of the sector area and the data signal transmitted on the lead in the middle of the sector area is reduced, the influence caused by the fan-out area of the display panel is avoided on the basis of not increasing the size of the product, the display effect of the display panel is improved, the design of a narrow-frame large-screen display is facilitated, and the taste of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a control method of a display panel according to an embodiment of the invention;
FIG. 2 is a flow chart of a control method of a display panel according to an embodiment of the invention;
FIG. 3 is a waveform diagram showing time delay variation of gate driving signals and data signals of a control method of a display panel according to an embodiment of the invention;
FIG. 4 is a schematic flow chart of a control method of a display panel according to an embodiment of the invention;
FIG. 5 is a schematic diagram illustrating a charging time of a control method of a display panel according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a driving circuit of a display panel according to a second embodiment of the invention;
FIG. 7 is a gamma voltage waveform diagram of a driving circuit of a display panel according to an embodiment of the invention;
Fig. 8 is a schematic structural diagram of an embodiment of a third display device according to the present invention.
Reference numerals illustrate:
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In addition, descriptions as pertaining to "first," "second," etc. in this application are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Embodiment one:
the invention provides a control method of a display panel 20, which can reduce the influence caused by time delay difference between wires at two ends of a fan-shaped area and between wires in the middle of fan-shaped leads on the display panel, and improve the display effect of the display panel 20.
Referring to fig. 1, the control method of the display panel 20 includes:
s100, adjusting and outputting a time sequence control signal;
the time sequence control signal can be regulated and output by regulating the amplitude, the phase and other parameters of the time sequence control signal, and one parameter can be regulated independently, or a plurality of parameters can be regulated in a combined way, so long as the purpose of delaying the time sequence control signal can be achieved.
In this embodiment, the control method of the display panel 20 is applied to the control circuit of the display panel 20, and the control circuit of the display panel 20 includes a gate driving circuit 211, a source driving circuit 102 and a timing controller 101. The timing controller 101 outputs a timing control signal to control the gate driving circuit 211 to output a gate driving signal to control the pixel array to be opened row by row, and the timing controller 101 controls the source driving circuit 102 to output a data signal according to the video signal to charge the pixel array opened row by row, so as to finally drive the display panel 20 to work.
When the gate driving circuit 211 is an array substrate row driving circuit, the amplitude of the timing control signal can be adjusted by adjusting the level value output from the power management integrated circuit to the level shifter 103. When the gate driving circuit 211 is a gate driving integrated chip, the level value of the power management integrated circuit output to the gate driving integrated chip can be adjusted. The phase of the timing control signal can be adjusted by an internal program of the timing controller 101. The level shifter 103 is connected between the timing controller 101 and the gate driving circuit 211, and is used for level shifting of the timing control signal.
And S200, delaying a corresponding gate driving signal according to the regulated time sequence control signal so as to enable the delay of the gate driving signal to be matched with the delay of the data signal output by the source driving circuit 102.
The gate driving circuit 211 at least includes an output module including a thin film transistor. The gate driving circuit 211 receives the timing control signal, outputs the timing control signal as a gate driving signal, and adjusts the timing control signal, i.e., adjusts the delay of the gate driving signal. In this embodiment, the delay of the gate driving signal and the delay of the data signal are matched, which may be interpreted as that the delay of the gate driving signal is between the delay of the data signal transmitted on the conductors at both ends of the sector area and the delay of the data signal transmitted on the intermediate conductor, for example, taking the average value of the two. In practical application, the test may be performed according to different products, and the appropriate delay time may be selected according to the display effect of the display panel 20.
It should be noted that, because of the delay of the data signal transmitted on the conductors at both ends of the sector area, the delay is not matched with the delay of the gate driving signal originally set. This may result in the data signal not being written entirely or written excessively to the corresponding pixel cell in the pixel array, which in turn may result in a low gray scale green blackening or bluish picture whitening.
According to the application, the time sequence control signals are adjusted, and the corresponding gate driving signals are delayed according to the adjusted time sequence control signals, so that the time delay of the gate driving signals is matched with the time delay of the data signals output by the source driving circuit 102. The delay of the grid driving signal is between the delay of the data signal transmitted on the leads at the two ends of the sector area and the delay of the data signal transmitted on the lead in the middle of the sector area, so that the influence caused by the delay difference between the data signal transmitted on the leads at the two ends of the sector area and the data signal transmitted on the lead in the middle of the sector area is reduced, the influence caused by the fan-out area of the display panel 20 is avoided on the basis of not increasing the size of the product, the display effect of the display panel 20 is improved, the design of a narrow-frame large-screen display is facilitated, and the taste of the display panel 20 is improved.
Referring to fig. 2, in one embodiment, the step S100 of adjusting and outputting the timing control signal includes: s101, keeping a voltage value of a high level of the time sequence control signal unchanged, and reducing the voltage value of a low level of the time sequence control signal; or alternatively
Maintaining the voltage value of the low level of the time sequence control signal unchanged, and reducing the voltage value of the high level of the time sequence control signal; or alternatively
Simultaneously reducing the voltage value of the high level and the voltage value of the low level of the time sequence control signal
Wherein, for keeping the voltage value of the high level of the timing control signal unchanged, the explanation of reducing the voltage value of the low level of the timing control signal is as follows:
The gate driving circuit 211 receives the timing control signal, and outputs the timing control signal as a gate driving signal, and the gate driving signal drives the thin film transistor of the pixel unit.
Therefore, the lower the low level of the gate driving signal, the smaller the off-state current, i.e. the leakage current, of the thin film transistor of the pixel unit, and in some high-brightness items, the leakage current of the thin film transistor will increase under the irradiation of strong light, resulting in abnormal picture of the display panel. According to the embodiment, the leakage current of the thin film transistor of the pixel unit is reduced by reducing the low-level voltage value of the time sequence control signal, so that the problem of abnormal picture caused by strong light irradiation is solved.
And secondly, when the data signals charge one row of pixel units, the larger the on-state current of the thin film transistors of the pixel units in the row is, the smaller the off-state current of the thin film transistors of the pixel units in other rows is, the higher the charging rate of the charged pixel units is, the overall charging rate of the pixel units is improved, the difference between the data signals of the wires at the two ends of the fan-shaped area and the charging rate of the data signals transmitted on the middle wire can be relieved, and the problem of uneven display of the fan-out area is solved.
Therefore, in this embodiment, the voltage value of the high level of the timing control signal is kept unchanged, so as to ensure that the on-state current of the thin film transistor of the pixel unit in the on state is unchanged; and then, reducing the voltage value of the low level of the time sequence control signal to reduce the off-state current of the thin film transistors of other rows of pixel units, thereby solving the problem of uneven display of the fan-out area.
Finally, reducing the voltage value of the low level of the timing control signal can enable the delay of the gate driving signal to be matched with the delay of the Data signal output by the source driving circuit 102, so as to reduce the problem of uneven display of the fan-out area caused by the delay difference between the Data signal transmitted by the wires at the two ends of the fan-out area and the Data signal transmitted by the wires in the middle of the fan-out lead, and the specific principle is as shown in fig. 3, wherein Data1 in fig. 3 represents the Data signal without delay, namely the Data signal transmitted by the wires in the middle of the fan-out area; data2 represents the delayed Data signal, i.e. the Data signal transmitted on the conductors at both ends of the sector area, gata1 and Gata2 representing two adjacent gate drive signals.
When the voltage value of the low level of the timing control signal is reduced from the voltage value VGL1 to the voltage value VGL2, the voltage amplitude that the timing control signal needs to span from the high level to the low level is increased, so that the actual waveform of the gate driving signal is adjusted from the waveform L1 to the waveform L3, as can be seen from fig. 3, the falling edge of the waveform L3 arrives later, that is, the gate driving signal represented by the waveform L3 is delayed, so that the delay of the gate driving signal is between the delay of the Data signal transmitted on the conductors at both ends of the sector area and the delay of the Data signal transmitted on the intermediate conductor, thereby solving the problem of uneven display of the fan-out area, in particular, enabling the Data signal Data2 to have enough time to write Data, and solving the problem of blackening of the low-order grey green color of the picture.
With continued reference to fig. 2, for maintaining the voltage value of the low level of the timing control signal unchanged, the explanation of decreasing the voltage value of the high level of the timing control signal is as follows:
First, as the voltage value of the high level of the timing control signal is reduced, the power consumption of the display device is reduced, and the low power consumption design of the display device is realized.
Secondly, the voltage difference between the high level and the low level of the time sequence control signal is properly reduced, so that the stability of the low level of the time sequence control signal can be effectively improved. When the voltage difference between the high level and the low level of the timing control signal is too large, the low level of the timing control signal is pulled up after a period of time. For example, when the voltage difference is greater than 45 volts, a low level set to minus 13 volts will be pulled up to minus 11 volts after a few hours.
Therefore, the embodiment keeps the voltage value of the low level of the time sequence control signal unchanged, reduces the voltage value of the low level of the time sequence control signal, not only can reduce power consumption, but also can reduce the voltage difference between the high level and the low level, and improves the stability of the low level.
Finally, reducing the voltage value of the high level of the timing control signal may enable the delay of the gate driving signal to be matched with the delay of the data signal output by the source driving circuit 102, so as to reduce the problem of uneven display in the fan-out area caused by the delay difference between the data signal transmitted on the wires at two ends of the fan-out area and the data signal transmitted on the wires in the middle of the fan-out wire, referring to fig. 2, specifically, when the voltage value of the high level of the timing control signal is reduced from the voltage value VGH1 to the voltage value VGH2, when the thin film transistor of the output module of the gate driving circuit 211 is turned on, the high level of the timing control signal is reduced, so as to reduce the rise of the gate source voltage of the high level to the gate voltage of the thin film transistor through the gate source voltage of the thin film transistor, so that the gate driving signal output by the thin film transistor is more gentle, as shown in fig. 2, the actual waveform of the gate driving signal is adjusted to be the waveform L2, and the falling edge of the waveform L2 arrives more slowly, that is, the gate driving signal represented by the waveform L2 is delayed.
In practical application, the voltage values of the high level and the low level of the time sequence control signal can be adjusted according to the display effect of the display, so that the delay time of the gate driving signal is adjusted to be matched with the data signal, the display effect of the display is continuously tested, and the voltage values of the high level and the low level are proper values until the optimal display effect is obtained.
Referring to fig. 2, the explanation of simultaneously decreasing the voltage value of the high level and the voltage value of the low level of the timing control signal is as follows:
Practical tests show that the smaller the voltage values of the high level and the low level of the time sequence control signal are in the adjustable range of the time sequence control signal in a practical application product, the better the effect of relieving the uneven display of the fan-out area is, and the better the effect of the display device is. But the adjustable range of the voltage values of the high level and the low level is limited.
In order to achieve a better adjustment effect, the present embodiment reduces two parameters of the high-level voltage value and the low-level voltage value of the timing control signal at the same time, so that the delay time of the gate driving signal can be significantly increased to match the delay of the gate driving signal with the delay of the data signal, and the display effect of the display panel 20 is improved.
In addition, when a certain display quality is to be achieved, a low level or a high level of a single adjustment timing control signal may cause a larger adjustment amplitude, which may have a certain influence on the display effect, for example, excessively reducing a high level of the timing control signal may affect the driving capability of the corresponding gate driving signal.
The embodiment reduces the voltage values of the high level and the low level of the time sequence control signal at the same time, effectively reduces the adjustment amplitude caused by the low level or the high level, and ensures the display effect.
Referring to fig. 2, in some embodiments, the step S100 of adjusting and outputting the timing control signal includes simultaneously decreasing a high-level voltage value and a low-level voltage value of the timing control signal at the time of start-up to delay the corresponding gate driving signal; when the user triggers to improve the display brightness through a key or other interactive modes, the low-level voltage value of the time sequence control signal is reduced, and the high-level voltage value of the time sequence control signal is improved; the gate driving signals corresponding to the time sequence control signals are ensured to have enough driving capability, so that the charging rate of the data signals to the storage capacitor in the pixel unit can meet the brightness requirement.
In this embodiment, the voltage values of the high level and the low level of the normal timing control signal are recorded as the normal high level and the normal low level; the step of keeping the voltage value of the high level of the time sequence control signal unchanged, and reducing the voltage value of the low level of the time sequence control signal to be a first correction low voltage value; the step of simultaneously reducing the voltage values of the high level and the low level of the time sequence control signal to be a second correction high level and a second correction low level, wherein the first correction low voltage value is smaller than the second correction low level.
The timing controller in this embodiment may switch to a mode in which the voltage values of the high level and the low level of the timing control signal are the second correction high level and the second correction low level at the time of startup;
when the user triggers to increase the display brightness through a key or other interaction modes, the mode is switched to a mode that the high level of the time sequence control signal is a normal high level, and the voltage value of the low level of the time sequence control signal is a first correction low voltage value.
Therefore, the problem of uneven display of the fan-out area is solved, and meanwhile, the brightness adjustment requirement is met.
In an embodiment, in the step of reducing the low-level voltage value of the timing control signal, after reducing the low-level voltage value of the timing control signal, the low-level voltage value of the timing control signal is less than or equal to minus 5 volts and greater than or equal to minus 14 volts.
In this embodiment, the voltage value of the low level is less than or equal to minus 5 volts, so that it is avoided that the low level voltage of the corresponding gate driving signal is not low enough, and a certain leakage current still exists when the thin film transistor of the pixel unit is turned off by the gate driving signal. The voltage value of the low level is larger than or equal to minus 14 volts, so that the situation that when the low level voltage of the corresponding gate driving signal is too low, and the gate driving is jumped from the low level to the high level, the voltage is too large, and more time is needed for level jump, and the high level is delayed to arrive can be avoided. Thus, the delay matching of the gate driving signal and the data signal is ensured, and the function of the time sequence control signal is not influenced.
In an embodiment, after the voltage value of the high level of the timing control signal is reduced, the voltage value of the high level of the timing control signal is greater than or equal to 31 volts.
The voltage value of the high level is set to be greater than or equal to 31 volts, and the control circuit can be started in a low-temperature environment while the delay of the gate driving signal and the delay of the data signal are matched.
Referring to fig. 4, in one embodiment, step S100, adjusting and outputting the timing control signal includes:
S102, adjusting the phase of the time sequence control signal to adjust the charging time of the data signal to the pixel unit.
It should be noted that the basic function of the timing control signal is realized by a high level and a low level thereof, and is independent of the phase; compared with the scheme of reducing the high level and/or the low level of the time sequence control signal, the phase of the time sequence control signal is adjusted so as not to influence the basic function of the time sequence control signal, so that the phase of the time sequence control signal can be adjusted to a larger extent in a reasonable range, the charging time of the data signal to the pixel unit is better adjusted, and the problem of uneven display of a fan-out area is solved.
The principle of adjusting the charging time of the data signal to the pixel unit to solve the problem of uneven display in the fan-out area is as follows, referring to fig. 5, in fig. 5, T1 represents the charging time; t2 represents error proofing charging time; data represents a Data signal; d1 denotes a high level duration of the data signal.
In this embodiment, the phase of the timing control signal is adjusted so that the timing control signal is moved forward (in the direction of the dashed arrow a in fig. 5, i.e., the dashed arrow points forward from the rear), so that the corresponding gate driving signal is moved forward, i.e., the falling edge of the gate driving signal is delayed, so that the delay of the gate driving signal is matched with the delay of the data signal, so that the delayed data signal has enough charging time, and the problem that the display picture is blackened due to low-order grayish green is avoided.
In an embodiment, after the phase of the timing control signal is adjusted, the charging time of the data signal to the pixel unit is greater than or equal to 1 microsecond and less than or equal to 1.1 microsecond.
Tests have shown that the delay of the gate drive signal is between the delay of the data signal transmitted on the conductors at both ends of the sector and the delay of the data signal transmitted on the conductors in the middle of the sector when the charge time of the pixel cell is between 1 microsecond and 1.1 microsecond. The charging time of the data signals transmitted on the middle wires can be reduced, and the charging time of the data signals transmitted on the wires at the two ends of the sector area can be increased, so that the influence caused by the delay difference between the data signals transmitted on the wires at the two ends of the sector area and the data signals transmitted on the wires in the middle of the sector lead can be relieved.
Specifically, if the charging time of the pixel unit is less than 1 microsecond after the phase adjustment of the timing control signal, there is still a problem that the charging time is insufficient and the low-order gray green turns black. If the phase of the timing control signal is adjusted, the charging time of the pixel unit is longer than 1.1 microsecond, resulting in more serious delay of the gate driving signal than the delay of the data signal, and no longer being between the delay of the data signal transmitted on the conductors at both ends of the sector area and the delay of the data signal transmitted on the conductors in the middle of the sector leads, thereby bringing about new picture anomalies.
Embodiment two:
Referring to fig. 6, the present application also proposes a control circuit of a display panel 20, the display panel 20 being provided with a pixel array, the control circuit of the display panel 20 comprising: a source driving circuit 102 connected to the pixel array, the source driving circuit 102 being configured to output a data signal to the pixel array; a timing controller 101, the timing controller 101 being configured to adjust and output a timing control signal; the gate driving circuit 211 is connected to the timing controller 101 and the pixel array, and the gate driving circuit 211 delays a corresponding gate driving signal according to the adjusted timing control signal, so that the delay of the gate driving signal matches the delay of the data signal output by the source driving circuit 102.
The timing controller 101 may be disposed on a PCB board, the source driving circuit 102 may be disposed on a flexible circuit board connected to the PCB board and the display panel 20, the gate driving circuit 211 may be an array substrate row driving circuit, and disposed on a non-effective display area of the array substrate in the display panel 20.
The timing controller 101 described in this embodiment may combine with the level shifter 103 to implement amplitude adjustment of the timing control signal, and may implement phase adjustment by an internal program.
In this embodiment, the time sequence control signal is adjusted, and the corresponding gate driving signal is delayed according to the adjusted time sequence control signal, so that the delay of the gate driving signal is matched with the delay of the data signal output by the source driving circuit 102. The delay of the grid driving signal is between the delay of the data signal transmitted on the leads at the two ends of the sector area and the delay of the data signal transmitted on the lead in the middle of the sector area, so that the influence caused by the delay difference between the data signal transmitted on the leads at the two ends of the sector area and the data signal transmitted on the lead in the middle of the sector area is reduced, the influence caused by the fan-out area of the display panel 20 is avoided on the basis of not increasing the size of the product, the display effect of the display panel 20 is improved, the design of a narrow-frame large-screen display is facilitated, and the taste of the display panel 20 is improved.
Referring to fig. 6, in an embodiment, the control circuit of the display panel 20 further includes:
A gamma circuit 104, the gamma circuit 104 being configured to output first to nth gamma voltages to the source driving circuit 102; the difference between the gamma voltage of the N/2 th and the gamma voltage of the (N/2) +1 th is more than 0.5 volt and less than 3.0 volt. N can be valued according to actual requirements.
This embodiment is described by taking N equal to 14 as an example. When N is equal to 14, the gray scale voltage value of the gamma voltage before adjustment can be referred to the following table.
Referring to the table, before the adjustment, the N/2 th gamma voltage and the (N/2) +1 th gamma voltage are both 0 volts.
Referring to fig. 7, the present embodiment increases the voltage value of the seventh gamma voltage from the voltage value gamm7_1 to the voltage value gamm7_2, and at this time, the voltage values of the first to sixth gamma voltages are also adjusted accordingly. The voltage difference between the seventh gamma voltage and the fifth gamma voltage is reduced from the voltage across S1 to the voltage across S2, and the voltage across is reduced, at this time, the actual curve of the data signal is adjusted from the waveform L5 to the waveform L4, that is, the falling edge reaches faster, which is equivalent to reducing the delay of the data signal, so that the delay of the gate driving signal is matched with the delay of the data signal. Similarly, the voltage value of the eighth gamma voltage is reduced from the voltage value gamm8_1 to the voltage value gamm8_2, and the voltage values of the ninth to fourteenth gamma voltages are correspondingly adjusted. The voltage across the eighth to tenth gamma voltages is also reduced.
In addition, the loss of the data signals when the pixel array is charged is reduced, and the charging difference between the data signals transmitted on the leads at the two ends of the sector area and the data signals transmitted on the leads in the middle of the sector area is reduced, so that the abnormal picture is reduced. Compared with the method that the width of the leads at the two ends of the sector area is widened, the embodiment does not need to be changed, and the size of the product can be prevented from being increased.
In addition, in the present embodiment, the difference between the (N/2) +1st gamma voltage and the (N/2) +1st gamma voltage is greater than 0.5 volts and less than 3.0 volts. The difference between the N/2 th gamma voltage and the (N/2) +1 th gamma voltage is greater than 0.5 volt, which can ensure that the data signal reduces the delay to the greatest extent. The difference between the N/2 gamma voltage and the (N/2) +1 gamma voltage is smaller than 3.0 volts, so that overlarge difference setting can be effectively avoided, the difference between other gamma voltages is reduced, and the effect of gamma correction cannot be achieved.
Embodiment III:
Referring to fig. 8, the present application further provides a display device, which includes a display panel 20 and the control circuit of the display panel 20; the specific structure of the control circuit of the display panel 20 refers to the above embodiments, and since the display device adopts all the technical solutions of all the embodiments, at least has all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein. The control circuit of the display panel 20 is used for controlling the display panel 20 to work.
Referring to fig. 8, in an embodiment, the display panel 20 includes an array color film substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is arranged between the array substrate and the color film substrate; the array substrate comprises an effective display area and an inactive display area, and the inactive display area surrounds the periphery of the effective display area.
The gate driving circuit 211 is disposed in the inactive display area of the array substrate. The display device further includes a control board 10 of the display panel 20, and a gamma circuit 104, a source driving circuit 102, a power management integrated circuit, a timing controller 101, a level shifter 103, and the like in a control circuit of the display panel 20 are provided on the control board 10.
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all the equivalent structural changes made by the description of the present invention and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the invention.
Claims (9)
1. The control method of a display panel, there are gate drive circuit and pixel array on the said display panel, the said gate drive circuit outputs the gate drive signal to the pixel array on the display panel through the scanning line, characterized by, the said control method of the display panel includes:
adjusting and outputting a time sequence control signal;
According to the gate driving signals corresponding to the regulated time sequence control signal delays, so that the time delay of the gate driving signals is matched with the time delay of the data signals output by the source driving circuit, wherein the time delay of the gate driving signals is matched with the time delay of the data signals, namely the time delay of the gate driving signals is between the time delay of the data signals transmitted on leads at two ends of a sector area and the time delay of the data signals transmitted on a middle lead;
Wherein the step of adjusting and outputting the timing control signal includes:
Maintaining the voltage value of the high level of the time sequence control signal unchanged, and reducing the voltage value of the low level of the time sequence control signal; or alternatively
The voltage value of the low level of the time sequence control signal is kept unchanged, and the voltage value of the high level of the time sequence control signal is reduced.
2. The method of controlling a display panel according to claim 1, wherein the step of adjusting and outputting the timing control signal comprises:
while lowering the voltage value of the high level and the voltage value of the low level of the timing control signal.
3. The control method of a display panel according to claim 1 or 2, wherein,
After the voltage value of the low level of the time sequence control signal is reduced, the voltage value of the low level of the time sequence control signal is smaller than or equal to minus 5 volts and larger than or equal to minus 14 volts.
4. The control method of a display panel according to claim 1 or 2, wherein,
After the voltage value of the high level of the time sequence control signal is reduced, the voltage value of the high level of the time sequence control signal is larger than or equal to 31 volts.
5. The method of controlling a display panel according to claim 1, wherein the step of adjusting and outputting the timing control signal comprises:
and adjusting the phase of the time sequence control signal to adjust the charging time of the data signal to the pixel unit.
6. The method for controlling a display panel according to claim 5,
After the phase of the time sequence control signal is regulated, the charging time of the grid drive signal output by the grid drive circuit to the pixel unit is more than or equal to 1 microsecond and less than or equal to 1.1 microsecond.
7. A control circuit of a display panel provided with a pixel array, characterized in that the control circuit of the display panel comprises:
the source electrode driving circuit is connected with the pixel array and is used for outputting data signals to the pixel array;
the time sequence controller is used for adjusting and outputting a time sequence control signal, and also used for keeping the voltage value of the high level of the time sequence control signal unchanged and reducing the voltage value of the low level of the time sequence control signal; or keeping the voltage value of the low level of the time sequence control signal unchanged, and reducing the voltage value of the high level of the time sequence control signal;
The gate driving circuit is connected with the time schedule controller and the pixel array, and the gate driving circuit delays the corresponding gate driving signal according to the adjusted time schedule control signal so as to enable the delay of the gate driving signal to be matched with the delay of the data signal output by the source driving circuit, wherein the delay of the gate driving signal is matched with the delay of the data signal, namely, the delay of the gate driving signal is between the delay of the data signal transmitted on leads at two ends of the sector area and the delay of the data signal transmitted on the middle lead.
8. The control circuit of the display panel according to claim 7, wherein the control circuit of the display panel further comprises:
a gamma circuit configured to output first to nth gamma voltages to the source driving circuit; the difference between the gamma voltage of the N/2 th and the gamma voltage of the (N/2) +1 th is more than 0.5 volt and less than 3.0 volt.
9. A display device comprising a display panel and a control circuit of the display panel according to any one of claims 7 to 8; the control circuit of the display panel is used for controlling the display panel to work.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154367A (en) * | 2006-09-25 | 2008-04-02 | 卡西欧计算机株式会社 | Display driving apparatus and display apparatus comprising the same |
| CN103198803A (en) * | 2013-03-27 | 2013-07-10 | 京东方科技集团股份有限公司 | Drive control unit, drive circuit and drive control method of display substrate |
| CN106023935A (en) * | 2016-07-27 | 2016-10-12 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driving method thereof |
| CN114299843A (en) * | 2021-12-31 | 2022-04-08 | 昆山龙腾光电股份有限公司 | Display panel driving method, driving device and display device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100729778B1 (en) * | 2000-08-17 | 2007-06-20 | 삼성전자주식회사 | Liquid crystal display device with a prevention function of poor charging |
| US8441505B2 (en) * | 2009-12-04 | 2013-05-14 | Himax Technologies Limited | System and method of driving a liquid crystal display |
| CN102236188B (en) * | 2010-04-23 | 2014-07-02 | 北京京东方光电科技有限公司 | Gate driving method and circuit and liquid crystal display (LCD) panel |
| CN103886844A (en) * | 2013-12-31 | 2014-06-25 | 深圳市华星光电技术有限公司 | Display panel assembly and adjusting method thereof, and display device |
| CN104361878B (en) * | 2014-12-10 | 2017-01-18 | 京东方科技集团股份有限公司 | Display panel and driving method thereof as well as display device |
| CN108877639A (en) * | 2018-09-25 | 2018-11-23 | 京东方科技集团股份有限公司 | Driving method, driving circuit, display panel and the display device of display panel |
| CN109523965B (en) * | 2018-12-19 | 2021-07-23 | 惠科股份有限公司 | Drive circuit, drive circuit of display panel and display device |
| KR20200077812A (en) * | 2018-12-21 | 2020-07-01 | 엘지디스플레이 주식회사 | Display device and driving method |
| CN113516938B (en) * | 2021-06-23 | 2024-03-26 | 惠科股份有限公司 | Driving circuit and driving method of display panel and display device |
| CN114488593B (en) * | 2022-01-26 | 2023-10-10 | 长沙惠科光电有限公司 | Driving circuit of display panel, array substrate and display panel |
-
2022
- 2022-05-19 CN CN202210546701.XA patent/CN114927112B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154367A (en) * | 2006-09-25 | 2008-04-02 | 卡西欧计算机株式会社 | Display driving apparatus and display apparatus comprising the same |
| CN103198803A (en) * | 2013-03-27 | 2013-07-10 | 京东方科技集团股份有限公司 | Drive control unit, drive circuit and drive control method of display substrate |
| CN106023935A (en) * | 2016-07-27 | 2016-10-12 | 深圳市华星光电技术有限公司 | Liquid crystal display device and driving method thereof |
| CN114299843A (en) * | 2021-12-31 | 2022-04-08 | 昆山龙腾光电股份有限公司 | Display panel driving method, driving device and display device |
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