CN114488593B - Driving circuit of display panel, array substrate and display panel - Google Patents
Driving circuit of display panel, array substrate and display panel Download PDFInfo
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- CN114488593B CN114488593B CN202210064805.7A CN202210064805A CN114488593B CN 114488593 B CN114488593 B CN 114488593B CN 202210064805 A CN202210064805 A CN 202210064805A CN 114488593 B CN114488593 B CN 114488593B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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Abstract
The application discloses a driving circuit of a display panel, an array substrate and the display panel. The driving circuit of the display panel comprises a multi-stage cascade array substrate row driving unit, a time sequence signal transmission line and a time sequence controller. The time sequence controller is connected with the row driving units of each stage of array substrate through a time sequence signal transmission line. The timing controller is configured to: the array substrate row driving units are divided into first to N-th array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line from near to far, and first to N-th type time sequence signals are output to the first to N-th array substrate row driving groups so as to drive the first to N-th array substrate row driving groups to output grid driving signals with pulse widths reduced in sequence, so that the problem that the falling edge of the grid driving signals output by the array substrate row driving units is delayed due to parasitic delay circuits on the array substrate and display panel display abnormality is solved.
Description
Technical Field
The present application relates to the field of display driving technologies, and in particular, to a driving circuit of a display panel, an array substrate and a display panel.
Background
The GDL technology (Gate Driver less) is to use the original array process of the liquid crystal display panel to manufacture the driving circuit of the horizontal scanning line on the substrate around the display area, so as to replace the external integrated circuit board (Integrated Circuit, IC) to finish the driving of the horizontal scanning line.
It is noted that the array substrate row driving unit is actually loaded, and has capacitive and resistive characteristics. Therefore, the array substrate row driving unit can be equivalent to an RC delay circuit, and the RC delay circuit can generate a delay effect on the timing signals. In this way, the timing signal received by the array substrate row driving unit (the next-stage array substrate row driving unit) far from the input end of the timing signal transmission line is delayed by the previous-stage array substrate row driving unit, so that the gate driving signal output by the previous-stage array substrate row driving unit is delayed, and abnormal image display is caused. Particularly, as the size of the display panel increases and the resolution increases, the number of row driving units of the array substrate on the display panel increases, and the delay problem is more serious.
Disclosure of Invention
The application mainly aims to provide a driving circuit of a display panel, which aims to solve the delay effect of a row driving unit of an array substrate and enable the display panel to display well.
In order to achieve the above objective, the present application provides a driving circuit of a display panel, for driving a pixel array to work, including a multi-stage cascade array substrate row driving unit and a timing signal transmission line, where the timing signal transmission line is used for receiving a timing signal, and an output end of the timing signal transmission line is connected with each stage of the array substrate row driving unit;
the array substrate row driving units are divided into first to N array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line from near to far; the driving circuit of the display panel further includes: a timing controller connected to an input of the timing signal transmission line, the timing controller configured to: outputting first to nth types of timing signals to first to nth array substrate row driving groups to drive the first to nth array substrate row driving groups to output gate driving signals; the pulse width of the grid driving signals corresponding to the first-N time sequence signals is reduced in sequence, and N is smaller than or equal to the number of the array substrate row driving units.
In an embodiment, pulse widths of the first to nth types of timing signals decrease sequentially.
In an embodiment, the voltage differences between the high level and the low level of the first class timing signal and the voltage differences between the low level and the low level of the nth class timing signal are sequentially increased.
In one embodiment, the N is equal to two.
In one embodiment, the ratio of the pulse width of the first type of timing signal to the pulse width of the second type of timing signal is 4:3.
In an embodiment, the high level voltage values of the first to nth types of timing signals are sequentially increased; and/or the low-level voltage values of the first to N-th time sequence signals are gradually decreased.
In an embodiment, the driving circuit of the display panel further includes a source driving circuit and a plurality of data lines, an input end of each data line is connected to the source driving circuit, an output end of each data line is connected to a column of pixel units, and each column of pixel units is divided into a first to an Mth pixel unit groups according to a distance from an input end of a corresponding data line from near to far;
the source electrode driving circuit is respectively connected with each data line and is configured to: outputting the first to mth class data signals to the first to mth pixel cell groups through the data lines;
the pulse width of the first class data signal to the M class data signal is gradually decreased.
In one embodiment, the M is equal to two.
The application also provides an array substrate which comprises an effective display area and an inactive display area, wherein the inactive display area surrounds the periphery of the effective display area, and a multi-stage cascade array substrate row driving unit in a driving circuit of the display panel is arranged in the inactive display area of the array substrate.
The present application also proposes a display panel comprising: the liquid crystal display comprises a color film substrate, liquid crystal and the array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color film substrate.
The time schedule controller is configured to output first to nth types of time schedule signals to the first to nth array substrate row driving groups according to the time schedule signals received by the first to nth array substrate row driving groups are delayed, so as to drive the first to nth array substrate row driving groups to output grid driving signals; controlling the pulse width of the grid driving signals corresponding to the first-class to N-th-class time sequence signals to be sequentially reduced; the pulse width of the grid driving signal is reduced, so that the falling edge of the grid driving signal can reach in advance, and the problem that the image display is abnormal because the time sequence signal received by the array substrate row driving unit far away from the input end of the time sequence signal transmission line is delayed by the front-stage array substrate row driving unit is solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of a driving circuit of a display panel according to an embodiment of the application;
FIG. 2 is a schematic diagram of a multi-stage cascade array substrate row driving unit of a driving circuit of a display panel according to an embodiment of the application;
FIG. 3 is a schematic circuit diagram of a pixel unit according to a first embodiment of the application;
FIG. 4 is a schematic waveform diagram of a driving circuit of a display panel according to an embodiment of the application;
FIG. 5 is a schematic diagram of another waveform of a driving circuit of a display panel according to an embodiment of the application;
FIG. 6 is a schematic structural diagram of a second array substrate according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a display panel according to a third embodiment of the application.
Reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
Embodiment one:
referring to fig. 1, the present application provides a driving circuit of a display panel, which is used for driving a pixel array on the display panel to work, the driving circuit of the display panel includes a multi-stage cascade array substrate row driving unit 10 and a timing signal transmission line, the timing signal transmission line is used for receiving a timing signal, and an output end of the timing signal transmission line is connected with each stage of the array substrate row driving unit 10.
The array substrate row driving units 10 in multistage cascade connection are divided into first to N array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line from near to far;
the driving circuit of the display panel further includes:
a timing controller connected to an input of the timing signal transmission line, the timing controller configured to: outputting first to nth types of timing signals to first to nth array substrate row driving groups to drive the first to nth array substrate row driving groups to output gate driving signals; the pulse width of the grid driving signals corresponding to the first-N time sequence signals is reduced in sequence, and N is smaller than or equal to the number of the array substrate row driving units.
It can be understood that the driving circuit of the display panel of the present application includes multiple cascaded array substrate row driving units, and the specific number of the array substrate row driving units is set according to the actual driving requirement, for example 1080 stages. The row driving unit of each stage of array substrate can drive one row of pixel units or drive two rows of pixel units.
Dividing the multistage cascade array substrate row driving units 10 into first to N array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line from near to far; the number of the specific groups may be set correspondingly according to the number of the array substrate row driving units, the size of the display panel, the resolution ratio and other conditions in practical application, for example, two groups or three groups, where the number of the groups does not exceed the number of the array substrate row driving units at most, that is, each group of the array substrate row driving units at least includes one array substrate row driving unit. In addition, the number of array substrate row driving units inside the array substrate row driving groups of different groups can be different and can be the same, and the embodiment can be selected to be the same so as to reduce the difficulty of dividing the groups. For example, when the number of array substrate row driving units is 1080, taking N as an example equal to 2, the first array substrate row driving unit group includes 1 st to 540 th array substrate row driving units near the input end of the timing signal transmission line, and the second array substrate row driving group 12 includes 541 st to 1080 th array substrate row driving units far from the input end of the timing signal transmission line. Taking N as an example, 3 is taken as the N, the first array substrate row driving unit group includes 1 st to 360 th array substrate row driving units close to the input end of the timing signal transmission line, the second array substrate row driving unit 12 includes 361 st to 720 th array substrate row driving units, and the third array substrate row driving unit includes 721 rd to 1080 th array substrate row driving units far from the input end of the timing signal transmission line. When the number of the array substrate row driving units is other, and/or N is other, the analogy is only needed.
The timing driver may be disposed on a timing control board, and the timing control board is connected to a timing signal transmission line through a flexible circuit board or other signal transmission carriers, and the timing signal transmission line is connected to the array substrate row driving unit 10 in multi-stage cascade connection.
Referring to fig. 2, the first to nth types of timing signals may refer to different timings of the same timing signal, and the operation of driving the multi-stage cascaded array substrate row driving unit 10 by using 8CLK timing signals is exemplified by that each of the first to nth types of timing signals CLK1 to CLK8 is sequentially the first to nth types of timing signals. Taking N as an example, the timing signal CLK1 outputs a first type of timing signal to the first array substrate row driving group 11 and a second type of timing signal to the second array substrate row driving group 12.CLK2 through CLK8 are the same and are not described in detail herein. Here, 8CLK and N are equal to 2 as examples. In practical applications, the scheme can be applied to 4CLK, 10CLK or other numbers of CLK, and N can also take 3, 4 or other values. Fig. 2 to the row driving circuit of the array substrate showing a single side, which can be extended to a double side driving in practical application.
The method for sequentially reducing the pulse width of the gate driving signals corresponding to the first to nth types of time sequence signals can be realized by adjusting the pulse width, the high-low level voltage difference or other parameters of the first to nth types of time sequence signals. The degree to which the pulse widths of the gate driving signals corresponding to the first to nth types of timing signals are sequentially reduced may be determined according to an actual test, for example, sequentially reduced according to a certain difference.
Referring to fig. 3, when the gate driving signal gate is at a high level, the thin film transistor TFT is turned on, the level of the data signal data is timely represented by the levels of the storage capacitor and the pixel equivalent capacitor Clc, and the level of the data signal data is consistent with the level of the pixel equivalent capacitor Clc. When the gate driving signal gate is at a low level, the thin film transistor TFT is turned off, and at this time, when the data signal is at a high level, the level of the pixel equivalent capacitor Clc maintains a high level consistent with the level of the data signal data due to the storage capacitor Cst, and when the data signal is at a low level, the level of the pixel equivalent capacitor Clc maintains a low level consistent with the level of the data signal data.
That is, when the data signal is at the high level, the gate driving signal should have a falling edge in time, turn off the thin film transistor, and rely on the storage capacitor Cst, so that the level of the pixel equivalent capacitor Clc maintains the high level consistent with the level of the data signal data.
However, when the timing signal received by the array substrate row driving unit far from the input end of the timing signal transmission line is delayed by the pre-stage array substrate row driving unit, the output gate driving signal is also delayed, resulting in that the data signal is hopped to a low level before the falling edge of the gate driving signal comes, and the levels of the storage capacitor Cst and the pixel equivalent capacitor Clc are pulled down, so that the level of the pixel equivalent capacitor Clc maintains a high level consistent with the level of the data signal data, and thus resulting in abnormal display.
The timing controller of the present application is configured to: outputting first to nth types of time sequence signals to the first to nth array substrate row driving groups according to the time sequence signals received by the first to nth array substrate row driving groups are delayed so as to drive the first to nth array substrate row driving groups to output grid driving signals; controlling the pulse width of the grid driving signals corresponding to the first-class to N-th-class time sequence signals to be sequentially reduced; the pulse width of the gate driving signal is reduced, so that the falling edge of the gate driving signal arrives in advance, and then the falling edge of the gate driving signal arrives before the data signal jumps to the low level, so that the falling edge of the gate driving signal can occur in time when the data signal is at the high level, the thin film transistor is turned off, and the level of the pixel equivalent capacitor Clc can keep the high level consistent with the level of the data signal data by virtue of the action of the storage capacitor Cst, so that the display panel can display well.
Referring to fig. 4, in an embodiment, the pulse widths of the first to nth types of timing signals are sequentially decreased.
In this embodiment, the pulse widths of the first to nth types of timing signals decrease in order, so that the actual product can be set.
It is easy to understand that the output module in the row driving unit of each stage of array substrate has an input terminal connected to the timing signal and an output terminal outputting the gate driving signal, so that the pulse width of the gate driving signal can be changed by adjusting the pulse width of the timing signal.
Fig. 4 shows a waveform schematic diagram of one of the timing signals CLK1, and illustrates that N is equal to 2, CLKB1 and CLK1 are a pair of timing signals output to the array substrate row driving unit, which are opposite phase signals for controlling the pull-down node of the array substrate row driving unit. CLKB1 therefore also includes a first type of timing signal and a second type of timing signal as CLK 1. The timing signal CLK1 may be one of 4CLK, 8CLK, 10CLK or other timing signals.
The pulse signals of the timing signals CLK1 are sequentially outputted to the array substrate row driving units 10 of the multi-stage cascade, the first half of which is the first type of timing signals, and outputted to the first array substrate row driving group 11 (array substrate row driving group near the input end), the pulse width of which is half of the period of the timing signals (for example, the pulse width may be 4H as 8H). The second half is the second type of timing signal, which is output to the second array substrate row driving group 12, and the pulse width is three-eighths of the period of the timing signal (for example, the pulse width may be 3H).
The gate driving signals gata1 and gata2 are gate driving signals output from any two-stage array substrate row driving units in the first array substrate row driving group 11. The gate driving signals gata3 and gata4 are gate driving signals output from any two-stage array substrate row driving units in the second array substrate row driving group 12.
Since the first array substrate row driving group 11 is close to the input end of the timing signal transmission line, the falling edges of the gate driving signals gata1 and gata2 output by the first array substrate row driving group may arrive before the data signal data transitions to the low level, so that the levels pixel1 and pixel1 of the pixel equivalent capacitor Clc may maintain the high level consistent with the data signal, so that the picture is well displayed.
Since the second array substrate row driving unit is far from the input end of the timing signal transmission line, but since the pulse width of the second type of timing signal in the timing signal CLK1 is reduced to three-eighths of the period of the timing signal, the pulse widths of the gate driving signals gata3 and gata4 are lower than those of gate1 and gate2, so that the delayed gate driving signals gata3 and gata4 still arrive before the data signal data jumps to the low level, and the levels pixel3 and pixel4 of the pixel equivalent capacitor Clc can maintain the high level consistent with the data signal, so that the picture is well displayed.
In this embodiment, the pulse width of each path of timing signals, for example, the first to nth types of timing signals of the timing signal CLK1, decreases in sequence, so that the pulse width of the corresponding gate driving signal decreases in sequence, and further, the delay effect generated by the row driving unit of the front array substrate is eliminated, so that the falling edge of the gate driving signal arrives in time, and the picture is well displayed. Therefore, the driving circuit of the display panel in the present embodiment can be applied to a large-sized or high-fraction display panel.
Referring to fig. 5, in some embodiments, the high-low level voltage differences of the first to nth types of timing signals sequentially increase.
The high-low level voltage difference of the first to nth class time sequence signals is sequentially increased, or the high-level voltage value of the first to nth class time sequence signals is sequentially increased, or the low-level voltage value of the first to nth class time sequence signals is sequentially decreased, or the high-level voltage value of the first to nth class time sequence signals is sequentially increased while the low-level voltage value of the first to nth class time sequence signals is sequentially decreased. It is noted that the high level voltage values of the first to nth class timing signals are controlled to be sequentially increased while the low level voltage values of the first to nth class timing signals are controlled to be sequentially decreased. The modulation speed can be increased, and the effect of adjusting one of the high level and the low level independently can be achieved with a smaller voltage variation amount of the high level or the low level of the timing signal. It is apparent that reducing the amount of voltage variation can reduce the regulation loss.
In this embodiment, the high-low level differential voltage of the first to nth types of timing signals is sequentially increased, so that the actual product can be set up, for example, according to a preset differential value.
It is easy to understand that the input end of the output module in the array substrate row driving unit is connected with the time sequence signal, and the output end outputs the grid driving signal. And the output module may include at least one thin film transistor. When the time sequence signal is output to the thin film transistor of the output unit of the array substrate row driving unit, the voltage difference of the time sequence signal is larger, the gate source voltage of the thin film transistor can be improved due to the coupling effect of the gate source capacitance of the thin film transistor and the improvement of the voltage of the time sequence signal, so that the migration capability of the current carrier of the thin film transistor is improved, the output capability of the thin film transistor is improved, the time sequence signal is taken as the climbing time when the gate driving signal is output, and the purpose of outputting the falling edge of the gate driving signal more quickly is achieved. Accordingly, the pulse width of the gate driving signal may be changed by adjusting the high-low level voltage difference of the timing signal.
Fig. 5 shows a waveform schematic diagram of one of the timing signals CLK1, and illustrates that N is equal to 2, CLKB1 and CLK1 are a pair of timing signals output to the array substrate row driving unit, which are opposite phase signals for controlling the pull-down node of the array substrate row driving unit. CLKB1 therefore also includes a first type of timing signal and a second type of timing signal as CLK 1. The timing signal CLK1 may be one of 4CLK, 8CLK, 10CLK or other timing signals.
The pulse signals of the timing signals CLK1 are sequentially outputted to the array substrate row driving units 10 of the multi-stage cascade, the first half is the first type of timing signals, and outputted to the first array substrate row driving group 11 (array substrate row driving group near the input end), and the high-low level voltage difference is the first high level Vgh1 minus the first low level Vgl1. The second half is a second type of timing signal, and is output to the second array substrate row driving group 12 (array substrate row driving group near the input end), and the voltage difference between the high and low levels is the second high level Vgh2 minus the second low level Vgl2. In this embodiment, the second high level Vgh2 is greater than the first high level Vgh1, or the second low level Vgl2 is less than the first low level Vgl1. Or the second high level Vgh2 is greater than the first high level Vgh1 and the second low level Vgl2 is less than the first low level Vgl1.
The gate driving signals gata1 and gata2 are gate driving signals output from any two-stage array substrate row driving units in the first array substrate row driving group 11. The gate driving signals gata3 and gata4 are gate driving signals output from any two-stage array substrate row driving units in the second array substrate row driving group 12.
Since the first array substrate row driving group 11 is close to the input end of the timing signal transmission line, the falling edges of the gate driving signals gata1 and gata2 output by the first array substrate row driving group may arrive before the data signal data transitions to the low level, so that the levels pixel1 and pixel1 of the pixel equivalent capacitor Clc may maintain the high level consistent with the data signal, so that the picture is well displayed.
Since the second array substrate row driving unit is far away from the input end of the timing signal transmission line, but since the voltage difference between the high level and the low level of the second type of timing signal in the timing signal CLK1 is larger than the voltage difference between the high level and the low level of the first type of timing signal, the pulse widths of the gate driving signals gata3 and gata4 are lower than those of gate1 and gate2, so that the delayed gate driving signals gata3 and gata4 still arrive before the data signal data jumps to the low level, and the levels pixel3 and pixel4 of the pixel equivalent capacitor Clc can maintain the high level consistent with the data signal, so that the picture is well displayed.
In this embodiment, the pulse width of each path of timing signals, for example, the first to nth types of timing signals of the timing signal CLK1, decreases in sequence, so that the pulse width of the corresponding gate driving signal decreases in sequence, and further, the delay effect generated by the row driving unit of the front array substrate is eliminated, so that the falling edge of the gate driving signal arrives in time, and the picture is well displayed. Therefore, the driving circuit of the display panel in the present embodiment can be applied to a large-sized or high-fraction display panel.
In some embodiments, the pulse widths of the first through nth types of timing signals decrease sequentially and the differential pressure increases sequentially.
Referring to fig. 2, 4, and 5, in some embodiments, the N is equal to 2.
In this embodiment, N is 2, which can well solve the display problem caused by the delayed time sequence signal, and adapt to a display panel with large size or high resolution, and can avoid that one path of time sequence signal includes too many kinds of time sequence signals, which results in the complexity increase of hardware circuits and software programs and the stability decrease of the system.
Referring to FIG. 4, in some embodiments, the ratio of the pulse width of the first type of timing signal to the pulse width of the second type of timing signal is 4:3. For example, the pulse width of the first type of timing signal is one half of the timing signal period, and the pulse width of the second type of timing signal is three-eighths of the timing signal period. The ratio is 4:3, so that the delay problem of the array substrate row driving unit of most large-size displays and high-resolution displays at present can be well solved.
In some embodiments, the driving circuit of the display panel further includes a source driving circuit and a plurality of data lines, an input end of each data line is connected to the source driving circuit, an output end of each data line is connected to a column of pixel units, and each column of pixel units is divided into a first to an Mth pixel unit groups according to a distance from an input end of a corresponding data line from near to far;
the source electrode driving circuit is respectively connected with each data line and is configured to: outputting the first to mth class data signals to the first to mth pixel cell groups through the data lines;
the pulse width of the first to M-th data signals is gradually decreased, and M is smaller than or equal to the number of a row of pixel units.
The source electrode driving circuit can be arranged on the time sequence control board, and the time sequence control board is connected with the data line through the flexible circuit board or other signal transmission carriers.
The first to nth types of data signals may refer to different times of the same path of data signal. One path of data signal data transmitted on one data line can be first-class to N-class data signals in sequence.
It can be understood that each pixel unit can be equivalent to an RC delay circuit, and the data signal is delayed by the equivalent delay circuit of the pixel unit, which can cause the charging problem of the pixel unit such as data misplacement and the like, so as to avoid abnormal display.
In this embodiment, the first to mth pixel unit groups are output with the first to mth data signals according to the delay degree of the data signals received by the first to mth pixel unit groups. That is, by setting the pulse width of the data signal data to decrease in sequence (the decrease amount can be set according to actual needs), when the data signal is output to the pixel unit far away from the input end of the data line, the falling edge can still arrive in time under the influence of the delay effect of the equivalent delay circuit of the pixel unit, so that the display panel can display well, and the display panel is suitable for the display panel with high resolution and large size. Meanwhile, the embodiment only adjusts the pulse width of the data signal data to eliminate the delay effect of the pixel unit, so that the source electrode driving circuit can follow up the video data, control the voltage value of the data signal data, and further control the display panel to display the picture matched with the video data.
In some embodiments, the M is equal to 2.
In this embodiment, N is 2, which can well solve the problem of abnormal display caused by delayed data signals, and adapt to a large-size or high-resolution display panel, and can avoid that one path of data signal includes too many types of data signals, which results in increased complexity of hardware circuits and software programs and reduced stability of the system.
Embodiment two:
referring to fig. 6, the application discloses an array substrate, which comprises an effective display area 101 and an inactive display area, wherein the inactive display area surrounds the periphery of the effective display area 101, and the multi-stage cascade array substrate row driving unit 10 of the driving circuit of the display panel is manufactured on the inactive display area 102 by using the original array process of the liquid crystal display panel. The specific structure of the driving circuit of the display panel refers to the above embodiments, and since the array substrate adopts all the technical solutions of all the embodiments, the array substrate has at least all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
Embodiment III:
referring to fig. 7, a display panel is disclosed, the display panel includes an array substrate 100, a color film substrate 200, and a liquid crystal layer 300, the liquid crystal layer 300 is disposed between the array substrate 100 and the color film substrate 200; the specific structure of the array substrate 100 refers to the above embodiments, and since the display panel adopts all the technical solutions of all the embodiments, the display panel has at least all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
The foregoing description is only of the optional embodiments of the present application, and is not intended to limit the scope of the application, and all the equivalent structural changes made by the description of the present application and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the application.
Claims (10)
1. The driving circuit of the display panel is used for driving the pixel array to work and comprises a multi-stage cascade array substrate row driving unit and a time sequence signal transmission line, wherein the time sequence signal transmission line is used for receiving time sequence signals, and the output end of the time sequence signal transmission line is connected with each stage of array substrate row driving unit; the array substrate row driving unit is divided into first to N array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line from near to far;
the driving circuit of the display panel further includes:
a timing controller connected to an input of the timing signal transmission line, the timing controller configured to: outputting first to nth types of timing signals to first to nth array substrate row driving groups to drive the first to nth array substrate row driving groups to output gate driving signals; the pulse width of the grid driving signals corresponding to the first-N time sequence signals is reduced in sequence, and N is smaller than or equal to the number of the array substrate row driving units.
2. The driving circuit of a display panel according to claim 1, wherein pulse widths of the first to nth types of timing signals decrease in order.
3. The driving circuit of a display panel according to claim 1 or 2, wherein the voltage difference between the high and low levels of the first to nth types of timing signals increases sequentially.
4. The display panel driving circuit according to claim 1, wherein N is equal to two.
5. The driving circuit of the display panel according to claim 4, wherein a ratio of a pulse width of the first type of timing signal to a pulse width of the second type of timing signal is 4:3.
6. The driving circuit of a display panel according to claim 1, wherein high-level voltage values of the first to nth kinds of timing signals are sequentially increased; and/or the low-level voltage values of the first to N-th time sequence signals are gradually decreased.
7. The driving circuit of a display panel according to any one of claims 1 to 6, wherein the driving circuit of the display panel further comprises a source driving circuit and a plurality of data lines, an input end of each of the data lines is connected to the source driving circuit, an output end of each of the data lines is connected to a column of pixel units, and each column of pixel units is divided into first to M-th pixel unit groups according to a distance from an input end of a corresponding data line;
the source electrode driving circuit is respectively connected with each data line and is configured to: outputting first to mth data signals to the first to mth pixel unit groups through the data lines;
the pulse width of the first to M-th data signals is gradually decreased, and M is smaller than or equal to the number of a row of pixel units.
8. The display panel driving circuit according to claim 7, wherein M is equal to two.
9. An array substrate, wherein the array substrate comprises an effective display area and an inactive display area, the inactive display area surrounds the periphery of the effective display area, and a multi-stage cascade array substrate row driving unit in the driving circuit of the display panel according to any of claims 1-8 is disposed in the inactive display area of the array substrate.
10. A display panel, the display panel comprising: the color film substrate, the liquid crystal layer and the array substrate according to claim 9, wherein the liquid crystal layer is arranged between the array substrate and the color film substrate.
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| CN202210064805.7A CN114488593B (en) | 2022-01-26 | 2022-01-26 | Driving circuit of display panel, array substrate and display panel |
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| CN202210064805.7A CN114488593B (en) | 2022-01-26 | 2022-01-26 | Driving circuit of display panel, array substrate and display panel |
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| CN114927112A (en) * | 2022-05-19 | 2022-08-19 | 滁州惠科光电科技有限公司 | Control method and control circuit of display panel and display device |
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| CN114488593A (en) | 2022-05-13 |
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