KR20060119247A - Liquid crystal display and method for driving the same - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to secure a sufficient time for charging image data of a pixel positioned far apart from a data driver by gradually shortening the horizontal periods of gate driver clock signals for each gate line as the gate lines approach the data driver. A liquid crystal display includes a liquid crystal panel(200) having pixels formed in each crossing part of an n number of gate lines(G0~Gn) and an m number of data lines(D1~Dm); a gate driver(600) supplying a scan signal to the gate lines; a data driver(400) converting the input image data into an analog pixel signal and then supplying the analog pixel signal to the data lines; a timing controller(100) supplying gate driver clock signals corresponding to the gate lines, to the gate driver and a data control signal to the data driver; and a frame memory(110) storing image data of a frame unit in turn, and reading and supplying the image data to the data driver. A horizontal period of the gate driver clock signal for the farthest gate line from the data driver is the longest. The horizontal periods of the gate driver clock signals for each gate line get shorter as the gate lines get close to the data driver.

Description

Liquid crystal display and method for driving the same {Liquid Crystal Display and method for driving the same}

1 is a configuration diagram of a conventional liquid crystal display device.

FIG. 2 is a waveform diagram illustrating a gate driver clock signal provided for one frame period in the timing controller of FIG. 1.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a waveform diagram illustrating a gate driver clock signal provided for one frame period in the timing controller of FIG. 3.

5 is a configuration diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: timing controller 110: frame memory unit

120: line memory section 200: liquid crystal panel

400: data driver 600: gate driver

800: gamma voltage supply

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof. More particularly, the charging time of the image data of a pixel located far from the data driver is greater than the charging time of the image data of a pixel located near the data driver The present invention relates to a liquid crystal display device and a driving method thereof capable of effectively securing a charging time of data of a large-area liquid crystal display device by long allocation.

In today's information society, the role of electronic displays has become very important, and various electronic displays have been widely used in various industrial fields. In the electronic display device field, electronic display devices having new functions suitable for the demands of the information society, which have been continuously developed and diversified, are continuously being developed. In general, an electronic display device refers to a device that transmits various pieces of information to a human through vision. That is, an electronic display device refers to an electronic device that converts an electronic information signal output from various electronic devices into an optical information signal that can be recognized by a human eye, and is a device that plays a role of a bridge between humans and electronic devices. It can be said.

In such an electronic display device, when an optical information signal is displayed by a light emitting phenomenon, it is referred to as a light emitting display device, and when it is displayed by light modulation due to reflection, scattering, or interference phenomenon, it is called a light receiving display device. Light emitting displays, also called active display devices, include cathode ray tube (CRT), plasma display panel (PDP), organic electroluminescent display (OLD), and light emitting diodes (LED). Light Emitting Diode (LED) etc. can be mentioned. The light receiving display device, which is called a passive display device, may include a liquid crystal display (LCD), an electrophoretic image display (EPID), and the like.

Cathode ray tube display device, which is used for television and computer monitor, and has the longest history, has the highest market share in terms of economy, but has many disadvantages such as heavy weight, large volume and high power consumption. .

Recently, due to the rapid progress of semiconductor technology, there is a demand for a flat panel display device as an electronic display device suitable for a new environment in accordance with the trend of lowering and lowering power of various electronic devices and miniaturization, thinning, and lightening of electronic devices. It is rapidly increasing. Accordingly, flat panel display devices such as a liquid crystal display (LCD), a plasma display device (PDP), an organic EL display device (OELD), and the like have been developed, and among these flat panel display devices, it is easy to miniaturize, light weight, and thinner. In particular, liquid crystal display devices having low power consumption and low driving voltage are drawing attention.

1 and 2, a conventional liquid crystal display device and a driving method thereof will be described. 1 is a configuration diagram of a conventional liquid crystal display device. FIG. 2 is a waveform diagram illustrating a gate driver clock signal provided for one frame period in the timing controller of FIG. 1.

As shown in FIG. 1, a conventional liquid crystal display device has m * n liquid crystal cells Clc arranged in a matrix type and has m data lines D1 to Dm and n gate lines G1 to Gn. A pixel is formed at the intersection, a liquid crystal panel 20 having a thin film transistor TFT formed thereon, and a data driver 40 that provides a pixel signal to data lines D1 to Dm of the liquid crystal panel 20. A gate driver 60 providing a scan signal to the gate lines G1 to Gn, a gamma voltage supply unit 80 providing a gamma voltage to the data driver 40, a gate driver 60 and a data driver. A timing controller 10 for controlling 40 is provided.

The liquid crystal panel 20 includes a plurality of liquid crystal cells Clc disposed in a matrix at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn. Each of the thin film transistors TFT formed in the liquid crystal cell Clc transfers a pixel signal provided from the data lines D1 to Dm to the liquid crystal cell Clc in response to a scan signal provided to the gate lines G1 to Gn. Supply. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line or between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

The gamma voltage supply unit 80 provides a plurality of gamma voltages to the data driver 40 so that an analog pixel signal can be generated.

The timing controller 10 generates a gate control signal GCS and a data control signal DCS including a gate driver start pulse GSP, a gate driver clock signal GCP, and the like by using the input synchronization signals. The control signal GCS is provided to the gate driver 60, and the data control signal DCS is provided to the data driver 40. In addition, the timing controller 10 rearranges the input image data R, G, and B and provides them to the data driver 40.

As shown in FIG. 2, the gate driver 60 includes one gate driver start pulse GSP and the number of gate lines G1 to Gn during one frame period in the timing controller 10. Gate driver clock signals GCP are provided, and scan signals are generated every one horizontal period H of the gate driver clock signals GCP of the number n of gate lines G1 to Gn. G1 to Gn). Accordingly, the thin film transistors TFTs connected to the gate lines G1 to Gn are sequentially driven.

The data driver 40 performs one horizontal period H of the gate driver clock signals GCP of the number n of the gate lines G1 to Gn in response to the data control signal DCS provided from the timing controller 10. Image data R, G, and B for each line are provided to the data lines D1 to Dm. In particular, the data driver 40 converts the image data R, G, and B input from the timing controller 10 into an analog pixel signal using the gamma voltage from the gamma voltage supply unit 80 to convert the data lines D1. To Dm).

The timing controller 10 of the conventional liquid crystal display device provides the gate driver clock signals GCP of the number n of the gate lines G1 to Gn having the same horizontal period H. However, since a pixel located at a portion far from the data driver 40 has a larger load than a pixel located at a portion close to the data driver 40, a pixel located at a portion far from the data driver 40 is used for image data ( The problem of not effectively securing the charging time of R, G, and B) has been caused. In particular, this problem is even more serious when the liquid crystal display device becomes large.

Accordingly, a technical problem to be solved by the present invention is to allocate the charging time of the image data of a pixel located at a portion far from the data driver to be longer than the charging time of the image data of a pixel located at a portion close to the data driver. It is an object of the present invention to provide a liquid crystal display device capable of effectively securing a charging time of data.

Another object of the present invention is to provide a method of driving the liquid crystal display device.

The technical problem to be achieved by the present invention is not limited to the technical problems mentioned above, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

According to an aspect of the present invention, a liquid crystal panel includes a pixel formed at an intersection of a plurality of gate lines and a plurality of data lines, and the plurality of gates. A gate driver for providing scan signals to the lines, a data driver for converting input image data into an analog pixel signal and providing the plurality of data lines to the plurality of data lines, and a gate number n of the plurality of gate lines to the gate driver A timing controller providing driver clock signals, a timing controller providing a data control signal to the data driver, and a frame memory unit which alternately stores and reads image data in a frame unit and provides the data driver to the data driver, wherein the gate driver clock signals include: On the gate line furthest from the data driver It characterized in that a gate driver clock signal of a horizontal period is the longest and, as the access to the data driver that the horizontal period of the gate driver clock signal to the gate lines of the respective shorter.

In the liquid crystal display according to the exemplary embodiment, as the gate driver clock signals approach the data driver, the horizontal period of the gate driver clock signals for the respective gate lines may be linearly shortened.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention has a horizontal period of a gate driver clock signal for a gate line farthest from the data driver and a horizontal period of a gate driver clock signal for a gate line closest to the data driver. It is preferable that it is 1.2 times-1.8 times.

In the liquid crystal display according to the exemplary embodiment, the frame memory unit may be integrally formed with the timing controller.

According to another aspect of the present invention, there is provided a liquid crystal panel in which pixels are formed at intersections of a plurality of gate lines and a plurality of data lines, and the plurality of gates. A gate driver for providing a scan signal to the lines, a data driver for converting input image data into an analog pixel signal and providing the plurality of data lines to the gate driver; A timing controller that provides gate driver clock signals, a timing controller that provides a data control signal to the data driver, and a line memory unit that alternately stores and reads image data in line units and provides the data driver to the data driver, wherein the gate driver clock signal is provided. For the gate line furthest from the data driver It characterized in that the horizontal period of the gate driver clock signal is the longest and, as the access to the data driver that the horizontal period of the gate driver clock signal to the gate lines of the respective shorter.

According to another exemplary embodiment of the present invention, it is preferable that the horizontal period of the gate driver clock signals for the respective gate lines is linearly shortened as the gate driver clock signals approach the data driver.

Also, the liquid crystal display according to another embodiment of the present invention has a horizontal period of the gate driver clock signal for the gate line furthest from the data driver is equal to the horizontal period of the gate driver clock signal for the gate line closest to the data driver. It is preferable that it is 1.2 times-1.8 times.

In the liquid crystal display according to another exemplary embodiment, the line memory unit may be integrally formed with the timing controller.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, wherein a timing controller provides a gate driver with the gate driver clock signals of the number n of a plurality of gate lines to a gate driver, And providing a data control signal to the data driver by alternately storing and reading image data in a frame unit in a frame memory unit, wherein the gate driver clock signals are provided for the gate line farthest from the data driver. The horizontal period of the gate driver clock signal is the longest, and the horizontal period of the gate driver clock signals for the respective gate lines is shortened as the data driver approaches.

In the method of driving the liquid crystal display according to the exemplary embodiment, the horizontal period of the gate driver clock signals for the respective gate lines is linearly shortened as the gate driver clock signals approach the data driver. desirable.

In addition, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention may include the method of driving the gate driver clock signal for the gate line closest to the data driver with a horizontal period of the gate driver clock signal for the gate line farthest from the data driver. It is preferable that it is 1.2 times-1.8 times of a horizontal period.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, wherein the timing controller provides the gate driver with the gate driver clock signals, the number n of the plurality of gate lines, to the data driver. And providing a data control signal to the data driver by alternately storing and reading image data in a line unit, and providing the data driver signal to the gate line farthest from the data driver. The horizontal period of the gate driver clock signal is the longest, and the horizontal period of the gate driver clock signals for the respective gate lines is shortened as the data driver approaches.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, wherein the horizontal period of the gate driver clock signals for the respective gate lines is linearly shortened as the gate driver clock signals approach the data driver. desirable.

In addition, the driving method of the liquid crystal display device according to another embodiment of the present invention is that the horizontal period of the gate driver clock signal for the gate line furthest from the data driver is the gate driver clock signal for the gate line closest to the data driver. It is preferable that it is 1.2 times-1.8 times of a horizontal period.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

3 and 4, a liquid crystal display according to an exemplary embodiment and a driving method thereof will be described. 3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention. 4 is a waveform diagram illustrating a gate driver clock signal provided for one frame period in the timing controller of FIG. 3.

As shown in FIG. 3, in the liquid crystal display according to the exemplary embodiment, m * n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gate lines. Pixels are formed at intersections of (G1 to Gn), and the pixel signals are provided to the liquid crystal panel 200 having the thin film transistor TFT formed thereon and the data lines D1 to Dm of the liquid crystal panel 200. A data driver 400, a gate driver 600 for providing a scan signal to the gate lines G1 to Gn, a gamma voltage supply unit 800 for providing a gamma voltage to the data driver 400, and a gate driver. Timing controller 100 for controlling the 600 and the data driver 400, and a frame memory unit which alternately stores and reads image data R, G, and B in units of frames, and provides the data to the data driver 400. 110.

The liquid crystal panel 200 includes a plurality of liquid crystal cells Clc disposed in a matrix at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn. Each of the thin film transistors TFT formed in the liquid crystal cell Clc transfers a pixel signal provided from the data lines D1 to Dm to the liquid crystal cell Clc in response to a scan signal provided to the gate lines G1 to Gn. Supply. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line or between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

The gamma voltage supply unit 800 provides a plurality of gamma voltages to the data driver 400 so that an analog pixel signal can be generated.

The timing controller 100 generates a gate control signal GCS and a data control signal DCS including a gate driver start pulse GSP, a gate driver clock signal GCP, and the like by using the input synchronization signals. The control signal GCS is provided to the gate driver 600, and the data control signal DCS is provided to the data driver 400. In addition, the timing controller 100 rearranges the input image data R, G, and B and provides them to the frame memory unit 110.

The frame memory unit 110 stores the image data R, G, and B provided from the timing controller 100 in the first frame memory 111 in units of frames, and then stores the image data R, G, and B in units of frames in the second frame memory 112. While storing the image data R, G, and B, the image data R, G, and B stored in the first frame memory 111 are read out and provided to the data driver 400, and the first frame memory ( While storing image data R, G, and B in frame unit 111, image data R, G, and B stored in the second frame memory 112 are read out and provided to the data driver 400. FIG. Here, the frame memory unit 110 is preferably formed integrally with the timing controller 100.

The data driver 400 performs one horizontal period H of the gate driver clock signals GCP of the number n of the gate lines G1 to Gn in response to the data control signal DCS provided from the timing controller 100. Image data R, G, and B for each line (1) to H (N) are provided to the data lines D1 to Dm. In particular, the data driver 400 converts the image data R, G, and B input from the frame memory unit 110 into an analog pixel signal by using the gamma voltage from the gamma voltage supply unit 800 to convert the data lines ( D1 to Dm).

As shown in FIG. 4, the gate driver 600 includes one gate driver start pulse GSP and the number of gate lines G1 to Gn in one frame period in the timing controller 100. Gate driver clock signals GCP are received, and scan is performed every one horizontal period H (1) to H (N) of the gate driver clock signals GCP of the number n of gate lines G1 to Gn. The signal is generated and sequentially provided to the gate lines G1 to Gn. Accordingly, the thin film transistors TFTs connected to the gate lines G1 to Gn are sequentially driven. Here, the gate driver clock signals GCP are horizontal periods H (1) to H () of the gate driver clock signals GCP for the respective gate lines G1 to Gn as they approach the data driver 400. N)) becomes shorter. That is, the horizontal period H (N) of the gate driver clock signal GCP with respect to the gate line Gn farthest from the data driver 400 is longest, and the gate line G1 closest to the data driver 400 is present. The horizontal period H (1) for is the shortest. Thus, the charging time of the image data (R, G, B) of a pixel located at a portion far from the data driver 400 is set to the image data (R, G, B) of a pixel located at a portion close to the data driver 400. Since it is possible to allocate longer than the charging time, the pixel located far from the data driver 400 can effectively secure the charging time of the image data (R, G, B).

Meanwhile, as the gate driver clock signals GCP approach the data driver 400, the horizontal periods H (1) to H of the gate driver clock signals GCP for the respective gate lines G1 to Gn are approached. It is preferable that (N)) be linearly shortened. Thus, the horizontal periods H (1) to H (N) of the gate driver clock signals GCPs can be effectively allocated during one frame period (1 Frame).

The horizontal period H (N) of the gate driver clock signal GCP for the gate line Gn farthest from the data driver 400 is the gate for the gate line G1 closest to the data driver 400. It is preferable that it is 1.2 times-1.8 times the horizontal period H (1) of the driver clock signal GCP. The gate driver clock for the gate line G1 where the horizontal period H (N) of the gate driver clock signal GCP for the gate line Gn farthest from the data driver 400 is closest to the data driver 400. In the case where the horizontal period H (1) of the signal GCP is less than 1.2 times, the pixel located far from the data driver 400 cannot secure the charging time of the image data R, G, and B effectively. Not. In addition, the horizontal period H (N) of the gate driver clock signal GCP for the gate line Gn furthest from the data driver 400 is the gate for the gate line G1 closest to the data driver 400. In case of exceeding 1.8 times the horizontal period H (1) of the driver clock signal GCP, the horizontal periods H (1) to H (N) of the gate driver clock signals GCP during one frame period (1 Frame). It is not desirable to assign)) effectively.

A liquid crystal display and a driving method thereof according to another exemplary embodiment of the present invention will be described with reference to FIG. 5. 5 is a configuration diagram of a liquid crystal display according to another exemplary embodiment of the present invention. The liquid crystal display and the driving method thereof according to another exemplary embodiment of the present invention will not be described for the same points as the liquid crystal display and the driving method thereof according to the exemplary embodiment of the present invention, and other points will be described.

As shown in FIG. 5, a liquid crystal display according to another exemplary embodiment of the present invention includes a liquid crystal panel 200, a data driver 400, a gate driver 600, a gamma voltage supply unit 800, and a gate driver. The timing controller 100 for controlling the 600 and the data driver 400, and a line memory unit which alternately stores and reads the image data R, G, and B in units of lines and provides the data driver 400 to the data driver 400. 120.

The timing controller 100 generates a gate control signal GCS and a data control signal DCS including a gate driver start pulse GSP, a gate driver clock signal GCP, and the like by using the input synchronization signals. The control signal GCS is provided to the gate driver 600, and the data control signal DCS is provided to the data driver 400. In addition, the timing controller 100 rearranges the input image data R, G, and B and provides them to the line memory unit 120.

The line memory unit 120 stores the image data R, G, and B provided from the timing controller 100 in the first line memory 120_1 in line units, and then stores the image data R, G, and B in line units in the second line memory 120_2. While storing the image data R, G, and B, the image data R, G, and B stored in the first line memory 120_1 are read and provided to the data driver 400, and the third line memory ( While storing the image data R, G, and B in line units 120_3, the image data R, G, and B stored in the second line memory 120_2 are read and provided to the data driver 400. While storing the image data R, G, and B in line units in the fourth line memory 120_4, the image data R, G, and B stored in the third line memory 120_3 are read out to read the data driver ( 400). As described above, the line memory unit 120 alternately stores and reads image data R, G, and B in units of lines and provides the read data to the data driver 400. Here, the line memory unit 120 is preferably formed integrally with the timing controller 100.

As shown in FIG. 4, the gate driver 600 includes one gate driver start pulse GSP and the number of gate lines G1 to Gn in one frame period in the timing controller 100. Gate driver clock signals GCP are received, and scan is performed every one horizontal period H (1) to H (N) of the gate driver clock signals GCP of the number n of gate lines G1 to Gn. The signal is generated and sequentially provided to the gate lines G1 to Gn. Here, the gate driver clock signals GCP are horizontal periods H (1) to H () of the gate driver clock signals GCP for the respective gate lines G1 to Gn as they approach the data driver 400. N)) becomes shorter. Meanwhile, as the gate driver clock signals GCP approach the data driver 400, the horizontal periods H (1) to H (of gate driver clock signals GCP for the respective gate lines G1 to Gn are approached. N)) is preferably shortened linearly. The horizontal period H (N) of the gate driver clock signal GCP for the gate line Gn farthest from the data driver 400 is the gate for the gate line G1 closest to the data driver 400. It is preferable that it is 1.2 times-1.8 times the horizontal period H (1) of the driver clock signal GCP.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that. Therefore, the above-described embodiments will be described in detail so that the disclosure of the present invention may be completed, and those skilled in the art may easily implement the technical idea of the present invention. It is to be understood to be illustrative and not limitative in all respects, as it is provided to fully inform the person skilled in the art the scope of the invention, and the invention is defined only by the scope of the claims. .

As described above, the liquid crystal display and the driving method thereof according to the embodiments of the present invention shorten the horizontal period of the gate driver clock signals for the respective gate lines as the provided gate driver clock signals approach the data driver. Therefore, since the charging time of the image data of a pixel located at a portion far from the data driver can be allocated longer than the charging time of the image data of a pixel located at a portion close to the data driver, the pixels located far from the data driver are assigned to the image data. The charging time of can be secured effectively.

Claims (14)

A liquid crystal panel in which pixels are formed at intersections of a plurality of gate lines and a plurality of data lines; A gate driver providing a scan signal to the plurality of gate lines; A data driver converting the input image data into an analog pixel signal and providing the same to the plurality of data lines; A timing controller providing the gate driver clock signals of the number n of the plurality of gate lines to the gate driver and providing a data control signal to the data driver; And A frame memory unit which alternately stores and reads image data in a frame unit and provides the same to the data driver; The gate driver clock signals have the longest horizontal period of the gate driver clock signal for the gate line farthest from the data driver, and as the data driver approaches the horizontal period of the gate driver clock signals for the respective gate lines. It becomes short, The liquid crystal display device characterized by the above-mentioned. The method of claim 1, And the horizontal period of the gate driver clock signals for the respective gate lines is linearly shortened as the gate driver clock signals approach the data driver. The method of claim 2, And the horizontal period of the gate driver clock signal for the gate line furthest from the data driver is 1.2 times to 1.8 times the horizontal period of the gate driver clock signal for the gate line closest to the data driver. The method of claim 1, And the frame memory unit is integrally formed with the timing controller. A liquid crystal panel in which pixels are formed at intersections of a plurality of gate lines and a plurality of data lines; A gate driver providing a scan signal to the plurality of gate lines; A data driver converting the input image data into an analog pixel signal and providing the same to the plurality of data lines; A timing controller providing the gate driver clock signals of the number n of the plurality of gate lines to the gate driver and providing a data control signal to the data driver; And A line memory unit which alternately stores and reads image data in a line unit and provides the data driver to the data driver, The gate driver clock signals have the longest horizontal period of the gate driver clock signal for the gate line farthest from the data driver, and as the data driver approaches the horizontal period of the gate driver clock signals for the respective gate lines. It becomes short, The liquid crystal display device characterized by the above-mentioned. The method of claim 5, And the horizontal period of the gate driver clock signals for the respective gate lines is linearly shortened as the gate driver clock signals approach the data driver. The method of claim 6, And the horizontal period of the gate driver clock signal for the gate line furthest from the data driver is 1.2 times to 1.8 times the horizontal period of the gate driver clock signal for the gate line closest to the data driver. The method of claim 5, And the line memory unit is integrally formed with the timing controller. Providing, by a timing controller, the gate driver clock signals of the number n of the plurality of gate lines to the gate driver and providing a data control signal to the data driver; And And a frame memory unit alternately storing and reading image data in units of frames and providing the same to the data driver. The gate driver clock signals have the longest horizontal period of the gate driver clock signal for the gate line farthest from the data driver, and as the data driver approaches the horizontal period of the gate driver clock signals for the respective gate lines. The driving method of the liquid crystal display device characterized by shortening. The method of claim 9, And the horizontal period of the gate driver clock signals for the respective gate lines is linearly shortened as the gate driver clock signals approach the data driver. The method of claim 10, The horizontal period of the gate driver clock signal for the gate line furthest from the data driver is 1.2 times to 1.8 times the horizontal period of the gate driver clock signal for the gate line closest to the data driver. Driving method. Providing, by a timing controller, the gate driver clock signals of the number n of the plurality of gate lines to the gate driver and providing a data control signal to the data driver; And And alternately storing and reading image data in a line unit in a line memory unit, and providing the read data to the data driver. The gate driver clock signals have the longest horizontal period of the gate driver clock signal for the gate line farthest from the data driver, and as the data driver approaches the horizontal period of the gate driver clock signals for the respective gate lines. The driving method of the liquid crystal display device characterized by shortening. The method of claim 12, And the horizontal period of the gate driver clock signals for the respective gate lines is linearly shortened as the gate driver clock signals approach the data driver. The method of claim 13, The horizontal period of the gate driver clock signal for the gate line furthest from the data driver is 1.2 times to 1.8 times the horizontal period of the gate driver clock signal for the gate line closest to the data driver. Way.

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