CN114488593A - Display panel's drive circuit, array substrate and display panel - Google Patents
Display panel's drive circuit, array substrate and display panel Download PDFInfo
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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Abstract
The invention discloses a driving circuit of a display panel, an array substrate and the display panel. The driving circuit of the display panel comprises a multi-stage cascade array substrate row driving unit, a time sequence signal transmission line and a time sequence controller. And the time schedule controller is connected with the row driving units of each level of array substrate through a time schedule signal transmission line. The timing controller is configured to: the array substrate row driving unit is divided into a first array substrate row driving group, a second array substrate row driving group and an Nth array substrate row driving group according to the distance from the input end of the time sequence signal transmission line from near to far, and a first type time sequence signal, a second type time sequence signal and an Nth type time sequence signal are output to the first array substrate row driving group, the second array substrate row driving group and the Nth array substrate row driving group so as to drive the pulse width of the grid driving signal output by the first array substrate row driving group, the second array substrate row driving group and the Nth array substrate row driving group to be sequentially reduced, and therefore the problem that due to a parasitic delay circuit on an array substrate, the falling edge of the grid driving signal output by the array substrate row driving unit is delayed, and further the display panel is abnormal is solved.
Description
Technical Field
The invention relates to the technical field of display driving, in particular to a driving circuit of a display panel, an array substrate and the display panel.
Background
The GDL technique can reduce the welding (bonding) process of the external IC, thus improving the productivity and reducing the product cost, and making the liquid crystal display panel more suitable for manufacturing narrow-frame or frameless display products, wherein, the GDL Circuit comprises a plurality of cascaded line driving units, and the multistage cascaded array substrate line driving units are connected with a time sequence signal through a clock transmission line time sequence signal.
It should be noted that the array substrate row driver unit is actually loaded, and has capacitance and resistance characteristics. Therefore, the array substrate row driving unit can be equivalent to an RC delay circuit, and the RC delay circuit can generate a delay effect on the timing signal. In this way, the timing signal received by the array substrate row driving unit (the subsequent array substrate row driving unit) far away from the input end of the timing signal transmission line is delayed by the previous array substrate row driving unit, so that the output gate driving signal is delayed, and the abnormal picture display is caused. Particularly, as the size of the display panel increases and the resolution ratio increases, the number of row driving units of the array substrate on the display panel increases, and the delay problem becomes more serious.
Disclosure of Invention
The present invention is directed to a driving circuit of a display panel, and aims to provide a driving circuit of a display panel, which can solve the delay effect of a row driving unit of an array substrate and make the display panel display well.
In order to achieve the above object, the present invention provides a driving circuit of a display panel, configured to drive a pixel array to operate, including a multi-stage cascaded array substrate row driving unit and a timing signal transmission line, where the timing signal transmission line is configured to receive a timing signal, and an output end of the timing signal transmission line is connected to each stage of the array substrate row driving unit;
the array substrate row driving units are divided into first to Nth array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line to the input end of the time sequence signal transmission line from near to far; the driving circuit of the display panel further includes: a timing controller connected with an input end of the timing signal transmission line, the timing controller configured to: outputting first to Nth type time sequence signals to the first to Nth array substrate row driving groups so as to drive the first to Nth array substrate row driving groups to output gate driving signals; the pulse widths of the gate driving signals corresponding to the first-class to Nth-class time sequence signals are sequentially reduced, and N is less than or equal to the number of the array substrate row driving units.
In one embodiment, the pulse widths of the first-class to nth-class timing signals are sequentially decreased.
In one embodiment, the high-low level voltage difference of the first to nth class timing signals is sequentially increased.
In one embodiment, N is equal to two.
In one embodiment, the ratio of the pulse width of the first type of timing signal to the pulse width of the second type of timing signal is 4: 3.
In one embodiment, the high level voltage values of the first to nth class timing signals are sequentially increased; and/or the low-level voltage values of the first-type to N-type time sequence signals are sequentially decreased.
In an embodiment, the driving circuit of the display panel further includes a source driving circuit and a plurality of data lines, an input end of each data line is connected to the source driving circuit, an output end of each data line is connected to a row of pixel units, and each row of pixel units is divided into first to mth pixel unit groups from near to far according to a distance from the input end of the corresponding data line;
the source driving circuit, the source driving circuit is respectively connected with each data line, and the source driving circuit is configured to: outputting the first to M-th class data signals to the first to M-th pixel cell groups through the data lines;
wherein, the pulse widths of the first class to M class data signals are decreased gradually.
In one embodiment, M is equal to two.
The invention further provides an array substrate, which comprises an effective display area and a non-effective display area, wherein the non-effective display area surrounds the periphery of the effective display area, and the multi-stage cascade array substrate row driving unit in the driving circuit of the display panel is arranged in the non-effective display area of the array substrate.
The present invention also provides a display panel, comprising: the liquid crystal display comprises a color film substrate, liquid crystals and the array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color film substrate.
The time schedule controller is configured to output first to Nth type time schedule signals to first to Nth array substrate row driving groups according to the delayed degree of the time schedule signals received by the first to Nth array substrate row driving groups so as to drive the first to Nth array substrate row driving groups to output grid driving signals; controlling the pulse widths of the grid driving signals corresponding to the first-class to Nth-class time sequence signals to be reduced in sequence; the pulse width of the gate driving signal is reduced, so that the falling edge of the gate driving signal can arrive in advance, and the problem that the timing signal received by the array substrate row driving unit far away from the input end of the timing signal transmission line is delayed by the preceding array substrate row driving unit, so that the output gate driving signal is delayed, and further the abnormal picture display is caused is solved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a circuit diagram of a driving circuit of a display panel according to an embodiment of the invention;
fig. 2 is a schematic diagram of a multi-stage cascade array substrate row driving unit of a driving circuit of a display panel according to an embodiment of the invention;
FIG. 3 is a circuit diagram of a pixel unit according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of a driving circuit of a display panel according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing another waveform of a driving circuit of a display panel according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a second array substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a three-display panel according to an embodiment of the invention.
The reference numbers illustrate:
the objects, features and advantages of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between the embodiments may be combined with each other, but must be based on the realization of the technical solutions by a person skilled in the art, and when the technical solutions are contradictory to each other or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, the present invention provides a driving circuit of a display panel, which is used for driving a pixel array on the display panel to operate, and the driving circuit of the display panel includes a multi-stage cascaded array substrate row driving unit 10 and a timing signal transmission line, where the timing signal transmission line is used for receiving a timing signal, and an output end of the timing signal transmission line is connected to each stage of the array substrate row driving unit 10.
The array substrate row driving units 10 which are cascaded in a multi-stage mode are divided into first to Nth array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line from near to far;
the driving circuit of the display panel further includes:
a timing controller connected with an input end of the timing signal transmission line, the timing controller configured to: outputting first to Nth type time sequence signals to the first to Nth array substrate row driving groups so as to drive the first to Nth array substrate row driving groups to output gate driving signals; the pulse widths of the gate driving signals corresponding to the first-class to Nth-class time sequence signals are sequentially reduced, and N is less than or equal to the number of the array substrate row driving units.
It can be understood that the driving circuit of the display panel of the present application includes multiple cascaded array substrate row driving units, and the specific number is set according to actual driving requirements, for example, 1080. The row driving unit of each level of the array substrate can drive one row of pixel units and can also drive two rows of pixel units.
Dividing the multistage cascaded array substrate row driving units 10 into first to Nth array substrate row driving groups from near to far according to the distance from the input end of the time sequence signal transmission line; the specific number of groups may be set according to the number of array substrate row driving units, the size of the display panel, the resolution and other conditions in practical application, for example, two or three groups, where the number of groups does not exceed the number of array substrate row driving units at most, that is, each group of array substrate row driving groups at least includes one array substrate row driving unit. In addition, the number of the array substrate row driving units in the array substrate row driving groups of different groups may be different and may be the same, and this embodiment may be selected to be the same, so as to reduce the difficulty in dividing the groups. For example, when the number of the array substrate row driving units is 1080 levels, taking N equal to 2 as an example, the first array substrate row driving unit group includes the 1 st to 540 th level array substrate row driving units close to the input end of the timing signal transmission line, and the second array substrate row driving unit group 12 includes the 541 st to 1080 th level array substrate row driving units far from the input end of the timing signal transmission line. Taking N equal to 3 as an example, the first array substrate row driving unit group includes the 1 st to 360 th-level array substrate row driving units close to the input end of the timing signal transmission line, the second array substrate row driving unit group 12 includes the 361 st to 720 th-level array substrate row driving units, and the third array substrate row driving unit includes the 721 st to 1080-level array substrate row driving units far away from the input end of the timing signal transmission line. When the number of the column driving units of the array substrate is other, and/or N takes other values, the analogy is only needed.
The timing driver may be disposed on a timing control board, and the timing control board is connected to a timing signal transmission line through a flexible circuit board or other signal transmission carrier, and the timing signal transmission line is connected to the multi-stage cascade array substrate row driving unit 10.
Referring to fig. 2, the first to N-th clock signals may refer to different timings of the same clock signal, and for example, 8CLK clock signals drive the row driving units 10 of the multi-stage cascaded array substrate, each of the clock signals CLK1 to CLK8 is the first to N-th clock signals in sequence. Taking N equal to 2 as an example, the timing signal CLK1 outputs a first type of timing signal to the first array substrate row driving group 11 and outputs a second type of timing signal to the second array substrate row driving group 12. CLK 2-CLK 8 are similar and will not be described herein. Note that, 8CLK and N equal to 2 are taken as examples for description here. In practical application, the scheme may apply to 4CLK, 10CLK or other number of CLKs, and N may also take 3, take 4 or take other values. Fig. 2 to show a single-sided row driving circuit of an array substrate, which can be extended to dual-sided driving in practical applications.
The sequential reduction of the pulse widths of the gate driving signals corresponding to the first to nth class of timing signals may be realized by adjusting the pulse widths, the high and low level differential pressures, or other parameters of the first to nth class of timing signals. The sequential reduction degree of the pulse widths of the gate driving signals corresponding to the first-class to nth-class timing signals may be determined according to an actual test, for example, be sequentially reduced according to a certain difference.
Referring to fig. 3, when the gate driving signal gate is at a high level, the thin film transistor TFT is turned on, the level of the data signal data is timely expressed in the levels of the storage capacitor and the pixel equivalent capacitor Clc, and the level of the data signal data is consistent with the level of the pixel equivalent capacitor Clc. When the gate driving signal gate is at a low level, the thin film transistor TFT is turned off, and at this time, when the data signal is at a high level, the level of the pixel equivalent capacitor Clc may be maintained at a high level consistent with the level of the data signal data due to the storage capacitor Cst, and when the data signal is at a low level, the level of the pixel equivalent capacitor Clc may be maintained at a low level consistent with the level of the data signal data.
That is, when the data signal is at a high level, the gate driving signal should have a falling edge in time to turn off the thin film transistor, and the level of the pixel equivalent capacitor Clc is kept at a high level consistent with the level of the data signal data by virtue of the storage capacitor Cst.
However, when the timing signal received by the array substrate row driving unit far from the input end of the timing signal transmission line is delayed by the preceding array substrate row driving unit, the output gate driving signal is also delayed, so that the data signal jumps to a low level before the falling edge of the gate driving signal comes, and the levels of the storage capacitor Cst and the pixel equivalent capacitor Clc are pulled down, so that the level of the pixel equivalent capacitor Clc can maintain a high level consistent with the level of the data signal data, and display abnormality is caused.
The timing controller of the present invention is configured to: outputting first to Nth type timing signals to first to Nth array substrate row driving groups according to the delayed degree of the timing signals received by the first to Nth array substrate row driving groups so as to drive the first to Nth array substrate row driving groups to output grid driving signals; controlling the pulse widths of the grid driving signals corresponding to the first-class to Nth-class time sequence signals to be reduced in sequence; the falling edge of the gate driving signal can arrive in advance by reducing the pulse width of the gate driving signal, and then the falling edge of the gate driving signal arrives before the data signal jumps to the low level, so that when the data signal is at the high level, the falling edge of the gate driving signal can appear in time, the thin film transistor is turned off, and the level of the pixel equivalent capacitor Clc can keep the high level consistent with the level of the data signal data by virtue of the function of the storage capacitor Cst, so that the display panel can display well.
Referring to fig. 4, in an embodiment, the pulse widths of the first to nth class timing signals are sequentially decreased.
In this embodiment, the decrement in which the pulse widths of the first-class to nth-class timing signals are sequentially decreased may be set following an actual product.
It is easy to understand that, the input end of the output module in each level of the array substrate row driving unit is connected with the timing signal, and the output end of the output module outputs the gate driving signal, so that the pulse width of the gate driving signal can be changed by adjusting the pulse width of the timing signal.
Fig. 4 shows a waveform diagram of one of the timing signals CLK1, and taking N equal to 2 as an example for explanation, CLKB1 and CLK1 are a pair of timing signals output to the row driving units of the array substrate, and the two timing signals are inverted signals to each other and used for controlling the pull-down nodes of the row driving units of the array substrate. CLKB1 therefore also includes a first type of timing signal and a second type of timing signal as CLK 1. The timing signal CLK1 may be one of the timing signals in a driving structure of 4CLK, 8CLK, 10CLK or other numbers of timing signals.
The pulse signals of the timing signal CLK1 are sequentially output to the multistage cascade array substrate row driving units 10, the first half of the timing signals is the first kind of timing signals, and the first kind of timing signals are output to the first array substrate row driving group 11 (the array substrate row driving group close to the input end), and the pulse width of the first kind of timing signals is half of the period of the timing signals (for example, the pulse width may be 4H if 8H is taken as an example). The second half is a second kind of timing signal, which is outputted to the second array substrate column driving set 12, and the pulse width of the second kind of timing signal is three eighths of the period of the timing signal (for example, 8H, the pulse width may be 3H).
The gate driving signals gata1 and gata2 are gate driving signals output by any two stages of row driving units of the array substrate in the first row driving group 11. The gate driving signals gata3 and gata4 are gate driving signals output by any two stages of row driving units in the second array substrate row driving group 12.
Since the first array substrate row driving group 11 is close to the input end of the timing signal transmission line, the falling edges of the gate driving signals gata1 and gata2 output therefrom may arrive before the data signal data jumps to the low level, so that the levels pixel1 and pixel1 of the pixel equivalent capacitor Clc may maintain the high level consistent with the data signal, so that the picture is displayed well.
And since the second array substrate row driving unit is far away from the input end of the timing signal transmission line, but the pulse width of the second type of timing signal in the timing signal CLK1 is reduced to three eighths of the period of the timing signal, so that the pulse widths of the gate driving signals gata3 and gata4 are lower than those of the gate driving signals gate1 and gate2, so that the falling edges of the delayed gate driving signals gata3 and gata4 still arrive before the data signal data jumps to the low level, and thus the levels pixel3 and pixel4 of the pixel equivalent capacitor Clc can maintain the high level consistent with the data signal, so that the picture can be displayed well.
In this embodiment, the pulse width of each of the paths of timing signals, such as the first to nth paths of timing signals of the timing signal CLK1, is sequentially decreased, so that the pulse widths of the corresponding gate driving signals are sequentially decreased, thereby eliminating the delay effect generated by the line driving unit of the front-stage array substrate, and enabling the falling edge of the gate driving signal to arrive in time, so as to display a good picture. Therefore, the driving circuit of the display panel in the present embodiment can be applied to a large-size or high-resolution display panel.
Referring to fig. 5, in some embodiments, the high-low level voltage differences of the first to nth class timing signals are sequentially increased.
The high-low level voltage differences of the first to nth type of timing signals are sequentially increased in an increasing manner, and may be control high level voltage values of the first to nth type of timing signals to be sequentially increased in an increasing manner, or control low level voltage values of the first to nth type of timing signals to be sequentially decreased in a decreasing manner, or control high level voltage values of the first to nth type of timing signals to be sequentially increased in an increasing manner while control low level voltage values of the first to nth type of timing signals to be sequentially decreased in a decreasing manner. It should be noted that the high level voltage values of the first to nth clock signals are sequentially increased while the low level voltage values of the first to nth clock signals are sequentially decreased. The modulation speed can be improved, and the effect of independently adjusting the high level or the low level can be achieved by smaller voltage change quantity of the high level or the low level of the time sequence signal. It is apparent that the adjustment loss can be reduced by reducing the voltage variation.
In this embodiment, the high-low level differential pressure of the first-class to nth-class timing signals is sequentially increased, and may be set following an actual product, for example, increased according to a preset difference value.
It is easy to understand that, the input end of the output module in the array substrate row driving unit is connected with the timing signal, and the output end of the output module outputs the gate driving signal. And the output module may include at least one thin film transistor. When the time sequence signal is output to the thin film transistor of the output unit of the array substrate row driving unit as the pressure difference of the time sequence signal is larger, the gate-source voltage of the thin film transistor can be improved due to the coupling effect of the gate-source capacitor of the thin film transistor and the improvement of the voltage of the time sequence signal, so that the mobility and the output capacity of the thin film transistor are improved, the ramp time of the time sequence signal which is output as the gate driving signal is quicker, and the purpose of outputting the falling edge of the gate driving signal is achieved. Therefore, by adjusting the high-low level voltage difference of the timing signal, the pulse width of the gate driving signal can be changed.
Fig. 5 shows a waveform diagram of one of the timing signals CLK1, and taking N equal to 2 as an example for explanation, CLKB1 and CLK1 are a pair of timing signals output to the row driving units of the array substrate, and the two timing signals are inverted signals to each other and used for controlling the pull-down nodes of the row driving units of the array substrate. CLKB1 therefore also includes a first type of timing signal and a second type of timing signal as CLK 1. The timing signal CLK1 may be one of the timing signals in a driving structure of 4CLK, 8CLK, 10CLK or other numbers of timing signals.
The pulse signals of the timing signal CLK1 are sequentially output to the multistage cascade array substrate row driving units 10, the first half is a first kind of timing signal, and the first kind of timing signal is output to the first array substrate row driving group 11 (the array substrate row driving group close to the input end), and the difference between the high and low levels is the first high level Vgh1 minus the first low level Vgl 1. The second half is a second kind of timing signal, which is outputted to the second array substrate row driving group 12 (the array substrate row driving group near the input end), and the difference between the high level and the low level is the second high level Vgh2 minus the second low level Vgl 2. In this embodiment, the second high level Vgh2 is greater than the first high level Vgh1, or the second low level Vgl2 is less than the first low level Vgl 1. Or the second high level Vgh2 is greater than the first high level Vgh1 and the second low level Vgl2 is less than the first low level Vgl 1.
The gate driving signals gata1 and gata2 are gate driving signals output by any two stages of row driving units of the array substrate in the first row driving group 11. The gate driving signals gata3 and gata4 are gate driving signals output by any two stages of row driving units in the second array substrate row driving group 12.
Since the first array substrate row driving group 11 is close to the input end of the timing signal transmission line, the falling edges of the gate driving signals gata1 and gata2 output therefrom may arrive before the data signal data jumps to the low level, so that the levels pixel1 and pixel1 of the pixel equivalent capacitor Clc may maintain the high level consistent with the data signal, so that the picture is displayed well.
However, since the second array substrate row driving unit is far away from the input end of the timing signal transmission line, but the voltage difference between the high and low levels of the second type of timing signal in the timing signal CLK1 is larger than that of the first type of timing signal, so that the pulse widths of the gate driving signals gata3 and gata4 are lower than those of the gate driving signals gate1 and gate2, so that the falling edges of the delayed gate driving signals gata3 and gata4 still arrive before the data signal data jumps to the low level, and thus the levels pixel3 and pixel4 of the pixel equivalent capacitor Clc can maintain the high level consistent with the data signal, so that the picture can be displayed well.
In this embodiment, the pulse width of each of the paths of timing signals, such as the first to nth paths of timing signals of the timing signal CLK1, is sequentially decreased, so that the pulse widths of the corresponding gate driving signals are sequentially decreased, thereby eliminating the delay effect generated by the line driving unit of the front-stage array substrate, and enabling the falling edge of the gate driving signal to arrive in time, so as to display a good picture. Therefore, the driving circuit of the display panel in the present embodiment can be applied to a large-sized or high-resolution display panel.
In some embodiments, the pulse widths of the first through nth class timing signals decrease sequentially and the voltage difference increases sequentially.
Referring to fig. 2, 4 and 5, in some embodiments, N is equal to 2.
In this embodiment, N is 2, which can solve the display problem caused by the time delay of the timing signal, and is suitable for a large-size or high-resolution display panel, and can also avoid that one path of timing signal includes too many types of timing signals, which causes the complexity increase of a hardware circuit and a software program and the stability reduction of a system.
Referring to fig. 4, in some embodiments, a ratio of a pulse width of the first type of timing signal to a pulse width of the second type of timing signal is 4: 3. For example, the pulse width of the first type of timing signal is one half of the period of the timing signal, and the pulse width of the second type of timing signal is three eighths of the period of the timing signal. The ratio is 4:3, so that the delay problem of the array substrate row driving unit of most of the current large-size displays and high-resolution displays can be well solved.
In some embodiments, the driving circuit of the display panel further includes a source driving circuit and a plurality of data lines, an input end of each data line is connected to the source driving circuit, an output end of each data line is connected to a row of pixel units, and each row of pixel units is divided into first to mth pixel unit groups according to a distance from the input end of the corresponding data line from near to far;
the source driving circuit, the source driving circuit is respectively connected with each data line, and the source driving circuit is configured to: outputting the first to M-th class data signals to the first to M-th pixel cell groups through the data lines;
the pulse widths of the first-class to M-class data signals are sequentially decreased, and M is less than or equal to the number of the pixel units in a column.
The source driving circuit can be arranged on a time sequence control board, and the time sequence control board is connected with the data line through a flexible circuit board or other signal transmission carriers.
The first to nth data signals may refer to different times of the same data signal. One path of data signal data transmitted on one data line can be sequentially a first-type to an Nth-type data signal.
It can be understood that each pixel unit can also be equivalent to an RC delay circuit, and the data signal is delayed by the delay circuit equivalent to the pixel unit, which may cause the charging problem of the pixel unit such as data mis-charging, and avoid abnormal display.
In this embodiment, the first to M-th type data signals are output to the first to M-th pixel cell groups according to the degree of delay of the data signals received by the first to M-th pixel cell groups. That is, by setting the pulse width of the data signal data to be sequentially decreased (the decrement can be set according to actual needs), when the data signal is output to the pixel unit far away from the input end of the data line, the falling edge can still arrive in time under the influence of the delay effect of the equivalent delay circuit of the pixel unit, so that the display panel can display well to adapt to a high-resolution and large-size display panel. Meanwhile, in the embodiment, only the pulse width of the data signal data is adjusted to eliminate the delay effect of the pixel unit, so that the source electrode driving circuit can follow the video data, control the voltage value of the data signal data, and further control the display panel to display the picture matched with the video data.
In some embodiments, M is equal to 2.
In this embodiment, N is 2, which can well solve the problem of abnormal display caused by delayed data signals, and is suitable for a large-size or high-resolution display panel, and can also avoid that one path of data signals includes too many types of data signals, which results in increased complexity of hardware circuits and software programs and reduced stability of the system.
Example two:
referring to fig. 6, the present invention discloses an array substrate, which includes an effective display area 101 and an ineffective display area, wherein the ineffective display area surrounds the periphery of the effective display area 101, and the multi-stage cascade array substrate row driving unit 10 of the driving circuit of the display panel is manufactured on the ineffective display area 102 by using the original array process of the liquid crystal display panel. The specific structure of the driving circuit of the display panel refers to the above embodiments, and since the array substrate adopts all the technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
Example three:
referring to fig. 7, a display panel is disclosed, which includes an array substrate 100, a color filter substrate 200 and a liquid crystal layer 300, where the liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200; the specific structure of the array substrate 100 refers to the above embodiments, and since the display panel adopts all the technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and no further description is given here.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A drive circuit of a display panel is used for driving a pixel array to work and comprises a multi-stage cascaded array substrate row drive unit and a time sequence signal transmission line, wherein the time sequence signal transmission line is used for receiving a time sequence signal, and the output end of the time sequence signal transmission line is connected with each stage of array substrate row drive unit; the array substrate row driving units are divided into first to Nth array substrate row driving groups according to the distance from the input end of the time sequence signal transmission line from near to far;
the driving circuit of the display panel further includes:
a timing controller connected with an input end of the timing signal transmission line, the timing controller configured to: outputting first to Nth type time sequence signals to the first to Nth array substrate row driving groups so as to drive the first to Nth array substrate row driving groups to output gate driving signals; the pulse widths of the gate driving signals corresponding to the first-class to Nth-class time sequence signals are sequentially reduced, and N is less than or equal to the number of the array substrate row driving units.
2. The driving circuit of a display panel according to claim 1, wherein pulse widths of the first to nth class timing signals are sequentially decreased.
3. The driving circuit of a display panel according to claim 1 or 2, wherein the high-low level voltage differences of the first to nth class timing signals are sequentially increased.
4. The driving circuit of the display panel according to claim 1, wherein N is equal to two.
5. The driving circuit of the display panel according to claim 4, wherein a ratio of a pulse width of the first type of timing signal to a pulse width of the second type of timing signal is 4: 3.
6. The driving circuit of the display panel according to claim 1, wherein high-level voltage values of the first to nth class timing signals sequentially increase; and/or the low-level voltage values of the first-N type time sequence signals are sequentially decreased progressively.
7. The driving circuit of any one of claims 1 to 6, further comprising a source driving circuit and a plurality of data lines, wherein an input terminal of each data line is connected to the source driving circuit, an output terminal of each data line is connected to a column of pixel units, and each column of pixel units is divided into first to Mth pixel unit groups according to a distance from the input terminal of the corresponding data line;
the source driving circuit, the source driving circuit is respectively connected with each data line, and the source driving circuit is configured to: outputting the first to M-th class data signals to the first to M-th pixel cell groups through the data lines;
the pulse widths of the first-class to M-class data signals are sequentially decreased, and M is less than or equal to the number of the pixel units in a column.
8. The drive circuit of a display panel according to claim 7, wherein M is equal to two.
9. An array substrate, comprising an active display area and an inactive display area, wherein the inactive display area surrounds the periphery of the active display area, and the row driving units of the multi-level cascade array substrate in the driving circuit of the display panel according to any of claims 1 to 8 are disposed in the inactive display area of the array substrate.
10. A display panel, comprising: the liquid crystal display comprises a color film substrate, liquid crystal and the array substrate as claimed in claim 9, wherein the liquid crystal layer is arranged between the array substrate and the color film substrate.
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