CN112037728A - Gate driving unit, gate scanning driving circuit and liquid crystal display device - Google Patents
Gate driving unit, gate scanning driving circuit and liquid crystal display device Download PDFInfo
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The embodiment of the invention provides a grid driving unit, a grid scanning driving circuit and a liquid crystal display device, wherein the grid driving unit comprises: the device comprises a pull-up input module, a pull-up module, a pull-down module, a maintenance control module, a maintenance auxiliary module and a zero clearing module; the sustain auxiliary module is connected to the pull-up control node, the third clock signal, the driving signal output end, and the second level input end, and configured to receive the third clock signal and turn on the driving signal output end and the second level input end when the third clock signal is at a first level and the pull-up control node is pulled down to a second level. According to the embodiment of the invention, the maintenance auxiliary module is arranged, so that the noise or the miscellaneous peak of the driving signal output by the grid driving unit is reduced, the stability of the driving signal is improved, and the problem of poor display of the display panel is solved.
Description
Technical Field
The embodiment of the invention relates to the technical field of liquid crystal display, in particular to a gate driving unit, a gate scanning driving circuit and a liquid crystal display device.
Background
With the development of liquid crystal display technology, consumers have an increasing demand for narrow-frame screens, and in order to narrow a frame, an external Gate scanning driving circuit can be manufactured On an Array substrate by adopting a Gate On Array (GOA) technology, so that spaces of a Gate driving chip and a circuit board are saved.
In the conventional GOA technology, as shown in fig. 1, a circuit structure of 13T1C (1 capacitor of 13 thin film transistors) is generally adopted to generate a gate driving signal.
However, in the actual use process, the circuit structure often has a problem that the gate driving signal output by the circuit has a noise peak or noise, which causes poor display of the display panel, because the driving signal is not effectively pulled to the ground or the device is not set to pull down in a certain period when the driving signal outputs a low level.
Disclosure of Invention
Embodiments of the present invention provide a gate driving unit, a gate scanning driving circuit and a liquid crystal display device, so as to reduce the noise or the peak noise of a driving signal output by the gate driving unit, improve the stability of the driving signal, and improve the display defect problem of a display panel.
In a first aspect, an embodiment of the present invention provides a gate driving unit, including: the device comprises a pull-up input module, a pull-up module, a pull-down module, a maintenance control module, a maintenance auxiliary module and a zero clearing module;
the pull-up input module is connected with a drive signal input end and a pull-up control node, and is used for receiving a superior drive signal and setting the pull-up control node to be a first level when the superior drive signal is at the first level;
the pull-up module is connected with the pull-up control node, the first clock signal and the driving signal output end and is used for conducting the first clock signal and the driving signal output end when the pull-up control node is at a first level;
the pull-down module is connected with the driving signal output end, a second clock signal and a second level input end, and is used for receiving the second clock signal and conducting the driving signal output end and the second level input end when the second clock signal is at a first level;
the maintaining control module is connected with a maintaining signal input end of the maintaining module and a fourth clock signal, and is used for receiving the fourth clock signal and setting the maintaining signal input end to be at a first level when the fourth clock signal is at the first level;
the maintaining module is connected to the driving signal input end, the pull-up control node, a third clock signal and the second level input end, and configured to enable the pull-up control node after a higher-level driving signal received by the driving signal input end is at a second level and the pull-up control node is pulled down to the second level, and conduct the pull-up control node and the second level input end when the maintaining signal input end of the maintaining module is at the first level and the third clock signal is at the second level;
the sustain auxiliary module is connected to the pull-up control node, the third clock signal, the driving signal output end and the second level input end, and configured to receive the third clock signal and turn on the driving signal output end and the second level input end when the third clock signal is at a first level and the pull-up control node is pulled down to a second level;
the zero clearing module is connected with a zero clearing signal input end, the pull-up control node, the driving signal output end, the maintaining signal input end and the second level input end, and is used for receiving a zero clearing signal and conducting the pull-up control node, the driving signal output end and the maintaining signal input end with the second level input end when the zero clearing signal is at a first level.
In one possible design, the maintenance assistance module includes: a seventeenth transistor and a thirteenth transistor;
a gate of the seventeenth transistor is connected with the pull-up control node, a source of the seventeenth transistor is connected with the second level input end, and a drain of the seventeenth transistor is connected with a gate of the thirteenth transistor;
and the grid electrode of the thirteenth transistor is connected with the third clock signal, the drain electrode of the thirteenth transistor is connected with the driving signal output end, and the source electrode of the thirteenth transistor is connected with the second level input end.
In one possible design, the maintenance control module includes: a fifth transistor;
and the grid electrode and the drain electrode of the fifth transistor are both connected with the fourth clock signal, and the source electrode of the fifth transistor is connected with the maintaining signal input end of the maintaining module.
In one possible design, the maintenance module includes: a sixteenth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
the gate of the sixteenth transistor is connected with the driving signal input end, the source of the sixteenth transistor is connected with the second level input end, and the drain of the sixteenth transistor is connected with the maintaining module;
the grid electrode of the sixth transistor is connected with the pull-up control node, the source electrode of the sixth transistor is connected with the second level input end, and the drain electrode of the sixth transistor is connected with the maintaining control module;
the gate of the seventh transistor is connected with the input end of the third clock signal, the source of the seventh transistor is connected with the second level input end, and the drain of the seventh transistor is connected with the maintaining control module;
and the drain electrode of the eighth transistor is connected with the pull-up control node, the source electrode of the eighth transistor is connected with the second level input end, and the grid electrode of the eighth transistor is connected with the maintaining control module.
In one possible design, the pull-down module includes: an eleventh transistor;
and the grid electrode of the eleventh transistor is connected with the second clock signal, the drain electrode of the eleventh transistor is connected with the driving signal output end, and the source electrode of the eleventh transistor is connected with the second level input end.
In one possible design, the pull-down module further includes: a ninth transistor;
and the grid electrode of the ninth transistor is connected with the input end of the rear-stage driving signal, the drain electrode of the ninth transistor is connected with the pull-up control node, and the source electrode of the ninth transistor is connected with the second level input end.
In one possible design, the pull-up input module includes: a first transistor;
and the grid electrode and the drain electrode of the first transistor are both connected with the driving signal input end, and the source electrode of the first transistor is connected with the pull-up control node.
In one possible design, the pull-up module includes: a tenth transistor and a first capacitor;
a gate of the tenth transistor is connected to the pull-up control node, a drain of the tenth transistor is connected to the first clock signal, and a source of the tenth transistor is connected to the driving signal output terminal;
one end of the first capacitor is connected with the pull-up control node, and the other end of the first capacitor is connected with the driving signal output end.
In one possible design, the zero module includes: a second transistor, a twelfth transistor, and a third transistor;
the grid electrode of the second transistor is connected with the zero clearing signal input end, the drain electrode of the second transistor is connected with the pull-up control node, and the source electrode of the second transistor is connected with the second level input end;
the grid electrode of the third transistor is connected with the zero clearing signal input end, the drain electrode of the third transistor is connected with the maintaining signal input end, and the source electrode of the third transistor is connected with the second level input end;
and the grid electrode of the twelfth transistor is connected with the zero clearing signal input end, the drain electrode of the twelfth transistor is connected with the driving signal output end, and the source electrode of the twelfth transistor is connected with the second level input end.
In one possible design, the gate driving unit further includes: a starting module;
the starting module is connected with a scanning starting signal input end, the pull-up control node and the second level input end, and is used for receiving a scanning starting signal and conducting the pull-up control node and the second level input end when the scanning starting signal is at a first level.
In one possible design, the start module includes: a fourth transistor;
and the grid electrode of the fourth transistor is connected with the input end of the scanning starting signal, the drain electrode of the fourth transistor is connected with the pull-up control node, and the source electrode of the fourth transistor is connected with the second level input end.
In a second aspect, an embodiment of the present invention provides a gate scan driving circuit, including: a plurality of cascaded gate drive units; the gate driving unit is the gate driving unit according to the first aspect and various possible designs of the first aspect.
In a third aspect, an embodiment of the present invention provides a liquid crystal display device, including: a liquid crystal display substrate, and a data driving circuit and a gate scanning driving circuit as described in the second aspect disposed on the liquid crystal display substrate.
The gate driving unit, the gate scanning driving circuit and the liquid crystal display device provided by the embodiment comprise a pull-up input module, a pull-up module, a pull-down module, a maintenance control module, a maintenance auxiliary module and a zero clearing module; the pull-up input module is connected with a drive signal input end and a pull-up control node, and is used for receiving a superior drive signal and setting the pull-up control node to be a first level when the superior drive signal is at the first level; the pull-up module is connected with the pull-up control node, the first clock signal and the driving signal output end and is used for conducting the first clock signal and the driving signal output end when the pull-up control node is at a first level; the pull-down module is connected with the driving signal output end, a second clock signal and a second level input end, and is used for receiving the second clock signal and conducting the driving signal output end and the second level input end when the second clock signal is at a first level; the maintaining control module is connected with a maintaining signal input end of the maintaining module and a fourth clock signal, and is used for receiving the fourth clock signal and setting the maintaining signal input end to be at a first level when the fourth clock signal is at the first level; the maintaining module is connected with the driving signal input end, the pull-up control node, a third clock signal and the second level input end, and is configured to enable the pull-up control node after a superior driving signal received by the driving signal input end is at a second level and the pull-up control node is pulled down to the second level, and conduct the pull-up control node and the second level input end when the maintaining signal input end of the maintaining module is at the first level and the third clock signal is at the second level; the sustain auxiliary module is connected to the pull-up control node, the third clock signal, the driving signal output end and the second level input end, and configured to receive the third clock signal and turn on the driving signal output end and the second level input end when the third clock signal is at a first level and the pull-up control node is pulled down to a second level; the zero clearing module is connected with a zero clearing signal input end, the pull-up control node, the driving signal output end, the maintaining signal input end and the second level input end, and is used for receiving a zero clearing signal and conducting the pull-up control node, the driving signal output end and the maintaining signal input end with the second level input end when the zero clearing signal is at a first level. The gate driving unit provided by this embodiment can pull down the driving signal output end in any clock period when the driving signal outputs a low level by providing the maintenance auxiliary module, thereby reducing the noise or the miscellaneous peak of the driving signal output by the gate driving unit, improving the stability of the driving signal, and improving the display defect of the display panel.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit diagram of a gate driving unit in the prior art;
FIG. 2 is a timing diagram of the gate driving unit shown in FIG. 1;
fig. 3 is a circuit diagram of a gate driving unit according to an embodiment of the invention;
fig. 4 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 5 is a circuit diagram of a gate driving unit according to another embodiment of the invention;
fig. 6 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the invention.
Reference numerals:
11: a pull-up input module; 12, a pull-up module; 20 a pull-down module; 31 maintaining the control module; 32 maintaining the module; 33 maintaining the auxiliary module; 40, resetting the module; m1: a first transistor; m2: a second transistor; m3: a third transistor; m4: a fourth transistor; m5: a fifth transistor; m6: a sixth transistor; m7: a seventh transistor; m8: an eighth transistor; m9: a ninth transistor; m10: a tenth transistor; m11: an eleventh transistor; m12: a twelfth transistor; m13: a thirteenth transistor; M6A: a sixteenth transistor; M7A: a seventeenth transistor; CKA: a first clock signal; CKB: a second clock signal; CKC: a third clock signal; CKD: a fourth clock signal; gn-b: a drive signal input; gn: a drive signal output terminal; NetA: a pull-up control node; NetB: a sustain signal input; VSS: a second level.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a circuit diagram of a gate driving unit in the prior art. As shown in fig. 1, the gate driving unit has a circuit structure of 13T1C (1 capacitor with 13 tfts). It includes: pull-up units (M1, M10, and C1), pull-down units (M9 and M11), sustain units (M5, M6, M6A, M7, and M8), and clear units (M2, M12, and M3).
In a specific implementation process, when a superior driving signal input by the driving signal input terminal is at a high level, M1 in the pull-up unit is turned on to charge the pull-up control node NetA, and when the NetA node is at a high level, M10 in the pull-up unit is turned on, and the in-plane driving signal output terminal outputs a high level. When a subsequent-stage signal Gn + a (a-th-stage signal later, for example, a is 2, Gn +2 is a driving signal output by a driving signal output terminal of a next stage of Gn +1, Gn +1 is a driving signal output by a driving signal output terminal of a next stage of Gn, and Gn is a driving signal output by a driving signal output terminal of a present stage) is at a high level, M9 in the pull-down unit is turned on, a pull-up control node NetA is turned on with a second level input terminal VSS for discharging, NetA is pulled down to VSS, and M10 is turned off, and at the same time, a second clock signal CKB is at a high level state, and M11 in the pull-down unit is controlled to be turned on, a driving signal output terminal is turned on with the second level input terminal VSS, and an output terminal is pulled down to VSS, and Gn outputs a low level; when the upper-level driving signal input by the driving signal input end is at a high level, the M6 of the maintaining unit is conducted, the maintaining signal input end NetB is pulled down to VSS, when the third clock signal CKC is at a high level state, the NetB is pulled down to VSS, and at the moment, the maintaining unit does not work under the two conditions; when the upper driving signal is at a low level and the fourth clock signal CKD is at a high level, M5 of the sustain unit is turned on, at which time M8 is turned on, discharging the NetA point and pulling NetA low to VSS; before the next frame of picture is turned on after one frame of picture is finished, the clear signal CLR is at high level, M2, M4 and M12 in the clear unit are all turned on, and NetA, NetB and output are respectively discharged to realize the clear function.
Fig. 2 is a timing diagram of the gate driving unit shown in fig. 1. The following describes an example of the operation state of the gate driving unit shown in fig. 1 in each period with reference to fig. 2:
as shown in fig. 2, CKA, CKB, CKC and CKD are clock signals with the same period and different phases, NetA is the level at the pull-up control node in fig. 1, i.e. the gate voltage of M10, NetB is the gate voltage of M8 in fig. 1, and Gn out1 is the present-stage driving signal output by the present-stage driving signal output terminal, i.e. Gn; gn out2 is a driving signal output by the output end of the driving signal of the next stage of Gn out1, namely Gn + 1; gn out3 is the driving signal output by the driving signal output terminal of the next stage of Gn out2, namely Gn + 2.
During the period: because the driving signal Gn-b (in this embodiment, b is 2, that is, the driving signal output by the previous-stage driving signal output terminal of Gn-2, Gn-2 is Gn-1, the driving signal output by the previous-stage driving signal output terminal of Gn-1, Gn-1 is the driving signal output by the previous-stage driving signal output terminal of Gn, Gn is the driving signal output by the current-stage driving signal output terminal) input by the driving signal input terminal is at a high level, M1 is turned on, NetA is changed to a high level, at this time, CKC is at a high level, M7 is turned on, NetB is pulled down to VSS, that is, is in a low level state, M8 is turned off, at this time, CKB is at a high level, M11 is turned on, and the driving signal Gn output by the driving signal output terminal is at a low level;
period two: CKD becomes high level, M5 is conducted, CKC becomes low level, M7 is closed, Gn-2 is high level at the moment, M6 is conducted, then NetB signal is still connected with VSS and is low level, M8 is closed, and NetA signal is maintained;
period three: the CKC and the CKD are maintained, CKB is changed into low level, M11 is closed, CKA is changed into high level, NetA is in high level, M10 is conducted, Gn outputs high level, through the capacitance coupling effect of M10 and a capacitor C1, the NetA signal is further promoted, and a Vgs (namely VGH + Vgs) is added on the basis of the original high level VGH;
period (iv): CKD becomes low level, M5 is closed, CKC becomes high level, M7 is turned on, Gn-2 is low level, M6 is closed, NetB is low level, M8 is continuously closed, and Gn continuously outputs high level;
during the period: CKA becomes low level, M10 outputs low level, CKB becomes high level, M11 is conducted, Gn is pulled down to VSS, CKC and CKD are maintained, and NetB is low level;
the period is: CKC changes to low level, CKD is in high level, at the moment, M7 is turned off, M5 is turned on, NetB signal is in high level, M8 is turned on, NetA is pulled down to VSS, CKA and CKB are maintained, NetA is in low level, M11 is turned on, Gn is connected with VSS, at the moment, Gn + a (in the embodiment, a is 3 for example, namely Gn + a is Gn +3) connected with the grid of M9 is in high level, M9 is turned on, and NetA is connected with VSS; thus the M9 and M8 duty cycles repeat;
period of time (c): CKA becomes high level, CKB becomes low level, at the moment, M11 is closed, CKC and CKD are maintained, NetB is high level, M8 is conducted, NetA is low level;
during the period of time: CKC is changed into high level, CKD is in low level, M7 is conducted, M5 is closed, NetB is in low level, M8 is closed, CKB maintains low level, M11 is closed, CKA maintains high level, at the moment, NetA and Gn are not pulled down and are in a suspended state, therefore, high level input signals transmitted from CKA high level signals are easily generated, Gn generates miscellaneous signals, and the display panel generates badness;
during period ninthly: CKA becomes low level, CKB becomes high level, M11 is conducted, Gn is connected with VSS, CKC and CKD are maintained, M7 is conducted, M5 is closed, NetB is low level, and M8 is closed;
an interval (r): during the equivalent period, CKC is changed into low level, CKD is in high level, at the moment, M7 is closed, M5 is conducted, a NetB signal is in high level, M8 is conducted, NetA is pulled down to VSS, CKA & CKB are maintained, NetA is in low level, M11 is conducted, Gn is connected with VSS, at the moment, Gn +3 is in high level, the M9 period is conducted, and Gn is connected with VSS;
period of time
An equivalence period;
period of time
An equivalence period ((b)); … …
Repeating the steps from the previous step to the last step until the frame period is finished.
In order to solve the problem that abnormal output of the Gn signal is easily generated in the period of the same period of every frame period, and when a plurality of periods are abnormal, abnormal output is generated to cause a mixed peak to appear, the embodiment of the invention provides a gate driving unit to reduce the mixed peak and noise of the output driving signal to avoid bad display of a display panel.
According to the embodiment of the invention, the maintaining auxiliary module is arranged, the CKC signal wire and the plurality of pull-down devices are added, the driving signal output end is communicated with the VSS through the CKC signal wire and the plurality of pull-down devices, and abnormal output of the driving signal output end is effectively avoided.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 3 is a circuit diagram of a gate driving unit according to an embodiment of the invention. As shown in fig. 3, the gate driving unit includes: a pull-up input module 11, a pull-up module 12, a pull-down module 20, a maintenance control module 31, a maintenance module 32, a maintenance assist module 33, and a clear module 40.
And the pull-up input module 11 is connected with the driving signal input end Gn-b and the pull-up control node NetA, and is used for receiving a superior driving signal and setting the pull-up control node NetA to be a first level when the superior driving signal is a first level.
The pull-up module 12 is connected to the pull-up control node NetA, the first clock signal CKA, and the driving signal output terminal Gn, and configured to turn on the first clock signal CKA and the driving signal output terminal Gn when the pull-up control node NetA is at the first level.
The pull-down module 20 is connected to the driving signal output terminal Gn, the second clock signal CKB, and the second level VSS input terminal, and configured to receive the second clock signal CKB and conduct the driving signal output terminal Gn with the second level VSS input terminal when the second clock signal CKB is at the first level.
The sustain control module 31 is connected to the sustain signal input terminal NetB and the fourth clock signal CKD of the sustain module 32, and configured to receive the fourth clock signal CKD and set the sustain signal input terminal NetB to the first level when the fourth clock signal CKD is at the first level.
The maintaining module 32 is connected to the driving signal input terminal Gn-b, the pull-up control node NetA, the third clock signal CKC, and the second level VSS input terminal, and configured to enable the pull-up control node NetA after the upper driving signal received by the driving signal input terminal Gn-b is the second level VSS and the pull-up control node NetA is pulled down to the second level VSS, and to turn on the pull-up control node NetA and the second level VSS input terminal when the maintaining signal input terminal NetB of the maintaining module 32 is the first level and the third clock signal CKC is the second level VSS.
The sustain auxiliary module 33 is connected to the pull-up control node NetA, the third clock signal CKC, the driving signal output terminal Gn, and the second level VSS input terminal, and configured to receive the third clock signal CKC and conduct the driving signal output terminal Gn with the second level VSS input terminal when the third clock signal CKC is at the first level and the pull-up control node NetA is pulled down to the second level VSS.
And the zero clearing module 40 is connected with the zero clearing signal input end, the pull-up control node NetA, the driving signal output end Gn, the maintaining signal input end NetB and the second level VSS input end, and is used for receiving the zero clearing signal and conducting the pull-up control node NetA, the driving signal output end Gn and the maintaining signal input end NetB with the second level VSS input end when the zero clearing signal is at the first level.
In practical applications, the driving signal received by the pull-up input module 11 may be a higher-level scanning signal or a higher-level transmission signal. This embodiment is not limited to this, and the actual circuit needs to be taken as the standard.
The pull-up module 12 is configured to generate a current-stage driving signal, output the current-stage driving signal to a current-stage scanning signal line, and further output the current-stage driving signal to a pixel display area for driving a scanning line.
Optionally, in this embodiment, the second level VSS is a low level, and the first level is a high level.
In this embodiment, by adding the trace of the third clock signal CKC, the CKC is connected to the maintenance auxiliary module 33, so that the device in the maintenance auxiliary module 33 can pull down the driving signal output terminal Gn quickly when the third clock signal CKC is at the first level and the signal of the NetA point is at the low level (the high level here may be the low level pulled down in the previous period and maintained in the current period), thereby ensuring the maintenance of the low level of the NetA and the output of the low level of the driving signal output terminal Gn, and avoiding noise and a peak due to the fact that the NetA or the driving signal output terminal Gn does not have a definite pull-down action.
It is to be understood that the internal circuit of the sustain assist module 33 can be implemented in various ways as long as the pull-down device can be ensured to pull down the driving signal output terminal Gn in each period (for example, the period (r) or each period equivalent to the period (r)) in which the pull-down operation is not explicitly set, and the embodiment is not limited thereto.
The gate driving unit provided in this embodiment can pull down the driving signal output terminal Gn in any clock period when the driving signal outputs a low level by providing the sustain auxiliary module 33, thereby reducing the noise or the noise of the driving signal output by the gate driving unit, improving the stability of the driving signal, and improving the display defect of the display panel.
Fig. 4 is a circuit diagram of a gate driving unit according to another embodiment of the invention. The embodiment describes the maintenance assisting module 33 in detail based on the above embodiment, and as shown in fig. 4, the maintenance assisting module 33 includes: a seventeenth transistor M7A and a thirteenth transistor M13; the gate of the seventeenth transistor M7A is connected to the pull-up control node NetA, the source is connected to the second level VSS input terminal, and the drain is connected to the gate of the thirteenth transistor M13, for enabling the sustain auxiliary module 33 when NetA is maintained at low level or pulled down to low level; the gate of the thirteenth transistor M13 is connected to the third clock signal CKC, the drain is connected to the driving signal output terminal Gn, and the source is connected to the second level VSS input terminal, for pulling the driving signal output terminal Gn low when CKC is high. To ensure that each period (particularly, the period (r) shown in fig. 2 and the periods equivalent to the period (r)) is clearly controlled in level with the driving signal output terminal Gn, thereby preventing the occurrence of a floating state and the occurrence of noise and a noise peak.
Alternatively, as shown in fig. 3, the maintenance control module 31 includes: a fifth transistor M5; the gate and the drain of the fifth transistor M5 are both connected to the fourth clock signal CKD, and the source is connected to the maintenance signal input terminal NetB of the maintenance module 32, for controlling the maintenance module 32 according to the fourth clock signal CKD to maintain the level of NetA, thereby avoiding the interference of abnormal signals.
Alternatively, as shown in fig. 3, the maintaining module 32 includes: a sixteenth transistor M6A, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the sixteenth transistor M6A has a gate connected to the driving signal input terminal Gn-b, a source connected to the second level VSS input terminal, and a drain connected to the sustain module 32, and is configured to enable the sustain module 32 when the driving signal input terminal Gn-b inputs a low level; the sixth transistor M6 has a gate connected to the pull-up control node NetA, a source connected to the second level VSS input terminal, and a drain connected to the sustain control module 31, for enabling the sustain module 32 after the pull-up control node NetA is pulled down by the pull-down module 20; a gate of the seventh transistor M7 is connected to the input terminal of the third clock signal CKC, a source thereof is connected to the input terminal of the second level VSS, and a drain thereof is connected to the sustain control module, for enabling the sustain module 32 when CKC is at a low level; the eighth transistor M8 has a drain connected to the pull-up control node NetA, a source connected to the second level VSS input terminal, and a gate connected to the sustain control module, and is configured to maintain the potential of NetA at a low level when the sustain module 32 is enabled and CKD is at a high level.
Alternatively, as shown in fig. 3, the pull-down module 20 includes: an eleventh transistor M11; the eleventh transistor M11 has a gate connected to the second clock signal CKB, a drain connected to the driving signal output terminal Gn, and a source connected to the second level VSS input terminal, and is configured to pull the driving signal output terminal Gn low when the second clock signal CKB is at a high level.
Alternatively, as shown in fig. 3, the pull-up input module 11 includes: a first transistor M1; the gate and the drain of the first transistor M1 are both connected to the driving signal input terminal Gn-b, and the source is connected to the pull-up control node NetA, for pulling the pull-up control node NetA high when the upper driving signal input from the driving signal input terminal Gn-b is at a high level.
Alternatively, as shown in fig. 3, the drawing-up module 12 includes: a tenth transistor M10 and a first capacitor; the gate of the tenth transistor M10 is connected to the pull-up control node NetA, the drain is connected to the first clock signal CKA, and the source is connected to the driving signal output terminal Gn, for being turned on when NetA is high level, and CKA is output through the driving signal output terminal GnGn; one end of the first capacitor is connected with the pull-up control node NetA, and the other end of the first capacitor is connected with the driving signal output terminal Gn, and is used for raising the potential of the NetA during the output period of the driving signal.
Optionally, as shown in fig. 3, the zeroing module 40 includes: a second transistor M2, a twelfth transistor M12, and a third transistor M3; the grid electrode of the second transistor M2 is connected with the input end of the zero clearing signal, the drain electrode is connected with the pull-up control node NetA, and the source electrode is connected with the input end of the second level VSS and used for clearing the NetA when the zero clearing signal is at a high level; the gate of the third transistor M3 is connected to the clear signal input terminal, the drain is connected to the maintenance signal input terminal NetB, and the source is connected to the second level VSS input terminal, for clearing the maintenance signal input terminal NetB when the clear signal is at a high level; the twelfth transistor M12 has a gate connected to the clear signal input terminal, a drain connected to the drive signal output terminal Gn, and a source connected to the second level VSS input terminal, and is configured to clear the drive signal output terminal Gn when the clear signal is at a high level.
Optionally, as shown in fig. 3, the gate driving unit further includes: a starting module; and the starting module is connected with the scanning starting signal input end, the pull-up control node NetA and the second level VSS input end, and is used for receiving the scanning starting signal and conducting the pull-up control node NetA and the second level VSS input end when the scanning starting signal is at the first level.
In this embodiment, since the gate driving unit of the previous b-stage does not have access to the previous stage transmission signal, the scan start signal is used to access the driving signal input terminal Gn-b of the initial previous b-stage, and the signal correspondingly accessed to the start module is at a low level. Taking b as 2 as an example, the first two sets of level signals are turned on by the scanning start signal STV, and in order to prevent the subsequent GOA gate driving unit from being abnormally turned on, the start module needs to be set to pull down the NetA signal.
Optionally, as shown in fig. 3, the starting module includes: a fourth transistor M4; the fourth transistor M4 has a gate connected to the scan enable signal input terminal, a drain connected to the pull-up control node NetA, and a source connected to the second level VSS input terminal for pulling the NetA signal low when STV is high.
In a specific working process, when an upper-level driving signal input by the driving signal input end Gn-b is in a high level, the M1 in the pull-up unit is conducted to charge the pull-up control node NetA, and when the NetA node is in the high level, the M10 in the pull-up unit is conducted, the in-plane driving signal output end Gn outputs the high level. The second clock signal CKB is in a high level state, controls M11 in the pull-down unit to be conducted, drives the signal output terminal Gn to be conducted with the second level VSS input terminal VSS, and outputs low level when output is pulled down to VSS; when the upper-level driving signal input by the driving signal input end Gn-b is at a high level, the M6 of the maintaining unit is turned on, the maintaining signal input end NetB is pulled down to VSS, when the third clock signal CKC is at a high level, NetB is pulled down to VSS, and at the moment, the maintaining unit does not work under the two conditions; when the third clock signal CKC is at a high level and NetA is at a low level, M17 is turned off, M13 is turned on, and the driving signal output terminal Gn is turned on with VSS, pulling Gn to a low level. When the upper driving signal is at a low level and the fourth clock signal CKD is at a high level, M5 of the sustain unit is turned on, at which time M8 is turned on, discharging the NetA point and pulling NetA low to VSS; before the next frame of picture is turned on after one frame of picture is finished, the clear signal CLR is at high level, M2, M4 and M12 in the clear unit are all turned on, and NetA, NetB and output are respectively discharged to realize the clear function.
For the operating state of each period, as shown in fig. 2, in the prior art, during the period £ l, CKC becomes low, CKD is high, at this time, M7 is off, M5 is on, NetB is high, M8 is on, NetA is pulled down to VSS, CKA and CKB are maintained, NetA is low, M11 is on, Gn is connected to VSS, Gn + a (assuming that a is 3) is high, M9 is on, and NetA is connected to VSS; thus the M9 and M8 duty cycles repeat; therefore, in order to save circuit area, the M9 device can be eliminated in this embodiment compared to the prior art, and meanwhile, the M8 device is used to pull NetA to VSS. In addition, in a period ((r)), CKC is changed into high level, the M13 device is turned on, M7A is turned off, CKD is in low level, M7 is turned on, M5 is turned off, Gn is connected with VSS, and Gn maintains low level state in a non-output period, thereby effectively preventing abnormal output of the driving signal of the gate driving unit; in the periods (c) and (c), when Gn is in a high level state, the NetA signal is in a high level, the M7A is turned on, and then the M13 is turned off, so that the M13 device is prevented from pulling down Gn to be in a VGH output state. Since other duty cycles in the frame period are identical to those shown in fig. 2, they are not described in detail. By performing the above-described cycle, Gn is always pulled down to VSS in the non-Gn output state, and thus abnormal output of Gn can be avoided.
In the above process, compared to the circuit structure of 13T1C in the prior art, since M9 and M8 are both the pull-down devices of NetA, the gate driving unit provided in this embodiment omits M9 in the pull-down unit, and saves area on the premise of ensuring circuit stability. The elimination of the M9 device can reduce the stage transfer effect among Gn, so that cascade connection among gate drive units of different stages is not needed, the mutual effect among the gate drive units is reduced, when a single gate drive unit is abnormal, the abnormality of multiple rows is not caused, and the abnormal position can be quickly positioned.
Fig. 5 is a circuit diagram of a gate driving unit according to another embodiment of the invention. In addition to the above-mentioned embodiment, for example, in addition to the embodiment shown in fig. 4, in order to ensure the pull-down effect, a ninth transistor M9 is added to realize the pull-down of NetA. As shown in fig. 5, in this embodiment, the pull-down module 20 further includes: a ninth transistor M9; the ninth transistor M9 has a gate connected to the post-stage driving signal input terminal Gn-b, a drain connected to the pull-up control node NetA, and a source connected to the second level VSS input terminal.
In a specific working process, when an upper-level driving signal input by the driving signal input end Gn-b is in a high level, the M1 in the pull-up unit is conducted to charge the pull-up control node NetA, and when the NetA node is in the high level, the M10 in the pull-up unit is conducted, the in-plane driving signal output end Gn outputs the high level. When the lower-level signal Gn + a is at a high level, M9 in the pull-down unit is turned on, the pull-up control node NetA is conducted with the second level VSS input terminal VSS for discharging, NetA is pulled down to VSS, M10 is turned off, meanwhile, the second clock signal CKB is in a high level state, M11 in the pull-down unit is controlled to be conducted, the driving signal output terminal Gn is conducted with the second level VSS input terminal VSS, and output is pulled down to VSS, Gn outputs a low level; when the upper-level driving signal input by the driving signal input end Gn-b is at a high level, the M6 of the maintaining unit is turned on, the maintaining signal input end NetB is pulled down to VSS, when the third clock signal CKC is at a high level, NetB is pulled down to VSS, and at the moment, the maintaining unit does not work under the two conditions; when the third clock signal CKC is at a high level and NetA is at a low level, M17 is turned off, M13 is turned on, and the driving signal output terminal Gn is turned on with VSS, pulling Gn to a low level. When the upper driving signal is at a low level and the fourth clock signal CKD is at a high level, M5 of the sustain unit is turned on, at which time M8 is turned on, discharging the NetA point and pulling NetA low to VSS; before the next frame of picture is turned on after one frame of picture is finished, the clear signal CLR is at high level, M2, M4 and M12 in the clear unit are all turned on, and NetA, NetB and output are respectively discharged to realize the clear function.
For the working state of each period, in the period (R), CKC is changed into high level, M13 device is conducted, M7A is closed, CKD is in low level, M7 is conducted, M5 is closed, Gn is connected with VSS, Gn maintains low level state in the non-output period, thereby effectively preventing abnormal output of the driving signal of the gate driving unit; in the periods (c) and (c), when Gn is in a high level state, the NetA signal is in a high level, the M7A is turned on, and then the M13 is turned off, so that the M13 device is prevented from pulling down Gn to be in a VGH output state. Since other duty cycles in the frame period are identical to those shown in fig. 2, they are not described in detail.
In the gate driving unit provided in this embodiment, the maintenance auxiliary module 33 is added on the basis of the original 13T1C circuit, so that the driving signal output terminal Gn can be pulled down in any clock period when the driving signal outputs a low level, thereby reducing the noise or the noise of the driving signal output by the gate driving unit, improving the stability of the driving signal, and improving the display defect problem of the display panel.
An embodiment of the present invention further provides a gate scan driving circuit, including: a plurality of cascaded gate drive units; the gate driving unit is the gate driving unit shown in fig. 3 to 5.
Fig. 6 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the invention. As shown in fig. 6, the liquid crystal display device 60 includes a liquid crystal display substrate 61, a gate scanning driving circuit 62 and a data driving circuit 63 respectively connected to the liquid crystal display substrate 61, and a circuit board 64 connected to the data driving circuit 63, wherein the gate scanning driving circuit 62 is disposed inside the liquid crystal display substrate 61, the circuit board 64 is connected to the data driving circuit 63 and the gate scanning driving circuit 62, the liquid crystal display substrate 61 is provided with a plurality of scanning lines Gx 1011 and a plurality of data lines Sy1012 which are criss-cross, the scanning lines 611 are provided with gate electrodes, the gate scanning driving circuit 62 is connected to the plurality of scanning lines 611 and supplies signals to the scanning lines 611, and the data driving circuit 63 is connected to the plurality of data lines 612 and supplies signals to the data lines 612.
The gate driver is internally provided with the gate scan driving circuit, the circuit board 104 is internally provided with a Level shifter (Level shift), a timing controller chip (T-CON), a GIP circuit, and the like, and the circuit board outputs a low Level VSS, a first clock signal CKA, a second clock signal CKB, a third clock signal CKC, a fourth clock signal CKD, and a start signal STV to the gate scan driving circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. A gate drive unit, comprising: the device comprises a pull-up input module, a pull-up module, a pull-down module, a maintenance control module, a maintenance auxiliary module and a zero clearing module;
the pull-up input module is connected with a drive signal input end and a pull-up control node, and is used for receiving a superior drive signal and setting the pull-up control node to be a first level when the superior drive signal is at the first level;
the pull-up module is connected with the pull-up control node, the first clock signal and the driving signal output end and is used for conducting the first clock signal and the driving signal output end when the pull-up control node is at a first level;
the pull-down module is connected with the driving signal output end, a second clock signal and a second level input end, and is used for receiving the second clock signal and conducting the driving signal output end and the second level input end when the second clock signal is at a first level;
the maintaining control module is connected with a maintaining signal input end of the maintaining module and a fourth clock signal, and is used for receiving the fourth clock signal and setting the maintaining signal input end to be at a first level when the fourth clock signal is at the first level;
the maintaining module is connected to the driving signal input end, the pull-up control node, a third clock signal and the second level input end, and configured to enable the pull-up control node after a higher-level driving signal received by the driving signal input end is at a second level and the pull-up control node is pulled down to the second level, and conduct the pull-up control node and the second level input end when the maintaining signal input end of the maintaining module is at the first level and the third clock signal is at the second level;
the sustain auxiliary module is connected to the pull-up control node, the third clock signal, the driving signal output end and the second level input end, and configured to receive the third clock signal and turn on the driving signal output end and the second level input end when the third clock signal is at a first level and the pull-up control node is pulled down to a second level;
the zero clearing module is connected with a zero clearing signal input end, the pull-up control node, the driving signal output end, the maintaining signal input end and the second level input end, and is used for receiving a zero clearing signal and conducting the pull-up control node, the driving signal output end and the maintaining signal input end with the second level input end when the zero clearing signal is at a first level.
2. A gate drive unit as claimed in claim 1, wherein the sustain assist module comprises: a seventeenth transistor and a thirteenth transistor;
a gate of the seventeenth transistor is connected with the pull-up control node, a source of the seventeenth transistor is connected with the second level input end, and a drain of the seventeenth transistor is connected with a gate of the thirteenth transistor;
and the grid electrode of the thirteenth transistor is connected with the third clock signal, the drain electrode of the thirteenth transistor is connected with the driving signal output end, and the source electrode of the thirteenth transistor is connected with the second level input end.
3. A gate drive unit as claimed in claim 1, wherein the sustain control module comprises: a fifth transistor;
and the grid electrode and the drain electrode of the fifth transistor are both connected with the fourth clock signal, and the source electrode of the fifth transistor is connected with the maintaining signal input end of the maintaining module.
4. A gate drive unit as claimed in claim 1, wherein the sustain module comprises: a sixteenth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
the gate of the sixteenth transistor is connected with the driving signal input end, the source of the sixteenth transistor is connected with the second level input end, and the drain of the sixteenth transistor is connected with the maintaining module;
the grid electrode of the sixth transistor is connected with the pull-up control node, the source electrode of the sixth transistor is connected with the second level input end, and the drain electrode of the sixth transistor is connected with the maintaining control module;
the gate of the seventh transistor is connected with the input end of the third clock signal, the source of the seventh transistor is connected with the second level input end, and the drain of the seventh transistor is connected with the maintaining control module;
and the drain electrode of the eighth transistor is connected with the pull-up control node, the source electrode of the eighth transistor is connected with the second level input end, and the grid electrode of the eighth transistor is connected with the maintaining control module.
5. A gate drive unit as claimed in claim 1, wherein the pull-down module comprises: an eleventh transistor;
and the grid electrode of the eleventh transistor is connected with the second clock signal, the drain electrode of the eleventh transistor is connected with the driving signal output end, and the source electrode of the eleventh transistor is connected with the second level input end.
6. The gate drive unit of claim 5, wherein the pull-down module further comprises: a ninth transistor;
and the grid electrode of the ninth transistor is connected with the input end of the rear-stage driving signal, the drain electrode of the ninth transistor is connected with the pull-up control node, and the source electrode of the ninth transistor is connected with the second level input end.
7. The gate drive unit of any of claims 1-6, wherein the pull-up input module comprises: a first transistor;
and the grid electrode and the drain electrode of the first transistor are both connected with the driving signal input end, and the source electrode of the first transistor is connected with the pull-up control node.
8. A gate drive unit as claimed in any one of claims 1 to 6, wherein the pull-up module comprises: a tenth transistor and a first capacitor;
a gate of the tenth transistor is connected to the pull-up control node, a drain of the tenth transistor is connected to the first clock signal, and a source of the tenth transistor is connected to the driving signal output terminal;
one end of the first capacitor is connected with the pull-up control node, and the other end of the first capacitor is connected with the driving signal output end.
9. The gate drive unit of any of claims 1-6, wherein the zeroing module comprises: a second transistor, a third transistor, and a twelfth transistor;
the grid electrode of the second transistor is connected with the zero clearing signal input end, the drain electrode of the second transistor is connected with the pull-up control node, and the source electrode of the second transistor is connected with the second level input end;
the grid electrode of the third transistor is connected with the zero clearing signal input end, the drain electrode of the third transistor is connected with the maintaining signal input end, and the source electrode of the third transistor is connected with the second level input end;
and the grid electrode of the twelfth transistor is connected with the zero clearing signal input end, the drain electrode of the twelfth transistor is connected with the driving signal output end, and the source electrode of the twelfth transistor is connected with the second level input end.
10. A gate drive unit as claimed in any one of claims 1 to 6, further comprising: a starting module;
the starting module is connected with a scanning starting signal input end, the pull-up control node and the second level input end, and is used for receiving a scanning starting signal and conducting the pull-up control node and the second level input end when the scanning starting signal is at a first level.
11. A gate drive unit as claimed in claim 10, wherein the start-up module comprises: a fourth transistor;
and the grid electrode of the fourth transistor is connected with the input end of the scanning starting signal, the drain electrode of the fourth transistor is connected with the pull-up control node, and the source electrode of the fourth transistor is connected with the second level input end.
12. A gate scan driving circuit, comprising: a plurality of cascaded gate drive units; the gate driving unit is as claimed in any one of claims 1 to 11.
13. A liquid crystal display device, comprising: a liquid crystal display substrate, and a data driving circuit and a gate scan driving circuit as claimed in claim 12 disposed on the liquid crystal display substrate.
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