CN114883181A - Manufacturing method for forming PN junction structure, manufacturing method for masking film and PN junction structure - Google Patents

Manufacturing method for forming PN junction structure, manufacturing method for masking film and PN junction structure Download PDF

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Publication number
CN114883181A
CN114883181A CN202210452775.7A CN202210452775A CN114883181A CN 114883181 A CN114883181 A CN 114883181A CN 202210452775 A CN202210452775 A CN 202210452775A CN 114883181 A CN114883181 A CN 114883181A
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film
junction structure
manufacturing
ion implantation
masking film
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Inventor
何辉飞
陈俊峰
杨培新
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Zibo Lvnengxinchuang Electronic Technology Co ltd
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Zibo Lvnengxinchuang Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention provides a manufacturing method for forming a PN junction structure, a manufacturing method for a masking film and a PN junction structure, which comprises the following steps: step T1, depositing SiO by furnace tube 2 Regulating and controlling the flow of the doping gas in the film process, thereby depositing a film with the doping concentration changing along with the film thickness; step T2, SiO deposited by BOE buffer etching liquid and DHF wet etching furnace tube 2 Film, using SiO of different doping concentrations 2 The films have different etching rates in BOE and DHF, and arc SiO with the edge having film thickness variation is etched 2 A membrane as a masking membrane for ion implantation; and step T3, removing the masking film by a wet method after the segmented ion implantation, and carrying out annealing activation to form a PN junction with small curvature. According to the invention, the blocking rates of the masking films with different thicknesses on ions are different, so that the PN junction structure formed by ion implantation is improved, the curvature is reduced, and the breakdown voltage of the PN junction of the device is improved.

Description

Manufacturing method for forming PN junction structure, manufacturing method for masking film and PN junction structure
Technical Field
The invention relates to the technical field of semiconductor SiC device manufacturing, in particular to a manufacturing method for forming a PN junction structure, a manufacturing method for a masking film and the PN junction structure; in particular to a manufacturing method for changing a PN junction structure formed by SiC ion implantation.
Background
The ideal PN structure is a borderless parallel plane junction, the electric field of the ideal PN structure is one-dimensional, however, the edge of the PN junction manufactured by the actual process has certain curvature, and the edge of the PN junction is actually a cylindrical junction or a spherical junction, when reverse voltage is applied to the device, the larger the curvature of the edge of the PN junction, the more concentrated the electric field of the edge of the PN junction, and the easier the breakdown.
For a traditional semiconductor Si-based device, the thermal diffusion rate of doped ions in an epitaxial layer is much higher than that of doped ions in SiC, in the manufacturing process of the Si-based device, the doped ions are diffused towards the periphery after being activated by a thermal annealing process, the curvature of a PN junction is reduced, the doping concentration at the junction is reduced, and the problem that the edges of a cylindrical surface PN junction and a spherical surface PN junction are easy to break down due to overlarge curvature is solved. Therefore, the problem of large curvature of the PN junction of the SiC device needs to be solved.
Patent document CN111883577A discloses a SiC high-voltage-resistant surge-resistant pn junction unipolar diode, which comprises a substrate made of n-type SiC, wherein a buffer layer, a drift region and a channel expansion region are sequentially extended from one surface of the substrate, a plurality of anode trenches with rectangular cross sections are formed in the channel expansion region, a p + junction region is extended from the side wall and the bottom end of each anode trench, a p-type contact region is extended from the highest surface of the channel expansion region, the p + junction region and the p-type contact region are covered and connected with an ohmic contact anode, and the other surface of the substrate is covered and connected with an ohmic contact cathode.
Patent document CN103280398A discloses a method for preparing a lateral graphene PN junction, belonging to the field of semiconductor devices and thin film crystal growth. The method comprises the steps of firstly preparing n-type doped graphene on a SiC substrate, then carrying out selection treatment on the graphene, including masking or patterning treatment or pre-deposition of a proper amount of p-type doped elements, finally annealing in a hydrogen atmosphere or vacuum, and controlling annealing time and temperature to obtain the transverse graphene PN junction.
Disclosure of Invention
In view of the defects in the prior art, the present invention provides a manufacturing method for forming a PN junction structure, a manufacturing method for a mask film, and a PN junction structure.
The manufacturing method for forming the PN junction structure comprises the following steps:
step T1, depositing SiO by furnace tube 2 Setting flow value parameters at multiple points in the film process to regulate and control the flow of the doping gas, thereby depositing the film with the doping concentration changing along with the film thickness;
step T2, SiO deposited by BOE buffer etching liquid and DHF wet etching furnace tube 2 Film, using SiO of different doping concentrations 2 The films have different etching rates in BOE and DHF, and arc SiO with the edge having film thickness variation is etched 2 A membrane as a masking membrane for ion implantation;
and step T3, removing the masking film by a wet method after the segmented ion implantation, and carrying out annealing activation to form a PN junction with small curvature.
Preferably, in step T2, the ion implantation site of the masking film is provided with a groove;
the groove is in a round table shape, and two sides of the half section of the groove are arc-shaped.
Preferably, a method for manufacturing the masking film for forming the PN junction structure includes the following steps:
step S1, depositing a layer of masking film on the surface of the lightly doped N-epitaxial layer by using a furnace tube;
step S2, coating a photoresist on the masking film, and defining an ion implantation pattern by photoetching;
step S3, etching a masking film with a concave arc edge by using a BOE + DHF wet method;
step S4, removing the photoresist on the surface by a dry method;
step S5, performing high-temperature segmented ion implantation;
step S6, removing the masking film by BOE;
step S7, annealing activation is carried out at 1500-2000 ℃.
Preferably, in step S1, the mask film is 1-2um BSG or PSG thin film;
the boron and phosphorus doping concentration of the deposited BSG or PSG film is uniformly changed along with the film thickness.
Preferably, in step S3, the BOE concentration ratio is 20: 1-6: 1, the concentration ratio of DHF is 10: 1 or 20: 1.
preferably, in step S3, the etching time is set to 120% to 160% of the over-etching amount according to the masking film thickness at the time of etching.
Preferably, in step S2, the photoresist thickness is 1.5-2 um.
Preferably, in step S5, the ion implantation temperature is 400-600 ℃.
Preferably, a PN junction structure manufactured by the manufacturing method for forming a PN junction structure includes: the N-epitaxial layer, the N + substrate and the ion implantation P + type region;
one side of the N-epitaxial layer is connected with the N + substrate, and one side of the N-epitaxial layer, which faces away from the N + substrate, is provided with an ion implantation P + type region.
Preferably, one side of the N-epitaxial layer, which faces away from the N + substrate, is connected with the masking film;
the groove position corresponds to the position of the ion implantation P + type area.
Preferably, the ion implantation is performed with an off-angle of 3-7 °.
The key technology of the process for improving the ion implantation morphology of the SiC device is that a furnace tube is utilized to deposit SiO of BSG or PSG 2 Regulating and controlling the flow of the doping gas in the film process, thereby depositing a BSG or PSG film with the doping concentration changing along with the film thickness; SiO doped with different concentrations of different substances by combining with wet etching agent 2 The masking films with the edges of concave arcs can be formed by different corrosion rates of the films, and cylindrical and spherical PN junctions with small edge curvatures can be formed in the SiC ion implantation process by different blocking rates of the masking films with different thicknesses on ion implantation, so that the phenomenon of low breakdown voltage caused by poor appearance of the PN junctions is improved.
Preferably, the BOE is a silicon dioxide buffered etchant and the DHF is dilute hydrofluoric acid.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the masking films with different doping concentrations are etched by introducing a wet method to form the ion implantation masking film with the edge of a concave arc, and when segmented high-temperature ion implantation is carried out, the masking films with different thicknesses have different ion blocking rates, so that a PN junction structure formed by ion implantation is improved, the curvature is reduced, and the breakdown voltage of a PN junction of a device is improved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of a PN junction structure of the present invention;
FIG. 2 is a schematic diagram after deposition of a masking film;
FIG. 3 is a schematic view after coating a photoresist;
FIG. 4 is a schematic diagram of a masking film after a groove is etched by a wet method;
FIG. 5 is a schematic diagram illustrating the photoresist being removed;
FIG. 6 is a schematic diagram after a segmented ion implantation;
FIG. 7 is a schematic view after removal of the masking film;
shown in the figure:
Figure BDA0003619465660000041
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example 1
As shown in fig. 1, a PN junction structure includes: an N-epitaxial layer 2, an N + substrate 3 and an ion implantation P + type region 4; one side of the N-epitaxial layer 2 is connected with the N + substrate 3, and one side of the N-epitaxial layer 2, which is back to the N + substrate 3, is provided with an ion implantation P + type region 4. One side of the N-epitaxial layer 2, which is back to the N + substrate 3, is connected with the masking film 1; the position of the groove corresponds to the position of the ion-implanted P + type region 4.
A manufacturing method for forming a PN junction structure comprises the following steps: step T1, depositing SiO by furnace tube 2 Regulating and controlling the flow of the doping gas in the film process, thereby depositing a film with the doping concentration changing along with the film thickness; step T2, SiO deposited by BOE buffer etching liquid and DHF wet etching furnace tube 2 Film, using SiO of different doping concentrations 2 The films have different etching rates in BOE and DHF, and arc SiO with the edge having film thickness variation is etched 2 A membrane as a masking membrane 1 for ion implantation; and step T3, removing the masking film 1 by a wet method after segmented ion implantation, and carrying out annealing activation to form a PN junction with small curvature. In the step T2, a groove is provided at the ion implantation position of the masking film 1, the groove is in a circular truncated cone shape, and both sides of the half section of the groove are provided with concave arcs.
As shown in fig. 2 to 7, a method for manufacturing a masking film for forming a PN junction structure includes the steps of: step S1, depositing a layer of masking film 1 on the surface of the N-epitaxial layer 2 by using a furnace tube; step S2, coating a photoresist 5 on the masking film 1, and defining an ion implantation pattern by photoetching; step S3, etching the masking film 1 with the edge of a concave arc by using a BOE + DHF wet method; step S4, removing the surface photoresist 5 by dry photoresist stripping; step S5, performing high-temperature segmented ion implantation; step S6, removing the masking film 1 by BOE; step S7, annealing activation is carried out at 1500-2000 ℃.
In step S1, the mask film 1 employs a BSG or PSG thin film of 1-2 um. In step S2, the photoresist 5 has a thickness of 1.5-2 um. In step S3, the BOE concentration ratio is 20: 1-6: 1, the concentration ratio of DHF is 10: 1 or 20: 1. in step S3, the etching time is set to 120% to 160% of the over-etching amount according to the film thickness of the masking film 1 during etching. In step S5, the ion implantation temperature is 400-600 ℃.
Example 2
Example 2 is a preferred example of example 1.
This example utilizes a furnace tube to deposit SiO 2 The flow of the same doping gas is regulated and controlled in the film process, thereby depositing the doping concentrationA BSG or PSG film whose thickness varies with the thickness of the film; SiO deposited by BOE and DHF wet etching furnace tube 2 Film, and control the over-etching rate, using SiO with different doping concentration 2 The films have different etching rates in BOE and DHF, and arc SiO with the edge having film thickness variation is etched 2 A membrane as a masking membrane 1 for ion implantation; carrying out high-temperature segmented ion implantation, then removing the masking film 1 by a wet method, and carrying out annealing activation at the temperature of 1500-;
as shown in fig. 2 to 7, the present embodiment includes the following methods:
step P1, depositing a layer of masking film 1 on the surface of the lightly doped N-epitaxial layer 2 by using a furnace tube, wherein the masking film 1 is a BSG or PSG film with the thickness of 1-2um, and during deposition, the flow of doping gas is strictly controlled, and the boron and phosphorus doping concentrations of the deposited BSG or PSG film are uniformly changed along with the film thickness; step P2, coating a photoresist 5 on the masking film 1, and defining an ion implantation pattern by photoetching; step P3, using BOE + DHF wet etching to etch out the masking film 1 with the edge of a concave arc, wherein the concentration ratio of BOE is 20: 1-6: 1, the concentration ratio of DHF is 10: 1 or 20: 1, performing 120-160% over-etching according to the thickness of the BSG or PSG thin film deposited in the step P1 to realize that the edge of the masking film 1 of the BSG or PSG is in a concave arc shape; step P4, removing the surface photoresist 5 by dry photoresist removal; step P5, performing segmented ion implantation at 400-600 ℃, and controlling the implantation concentration and depth during the segmented ion implantation; step P6, removing the masking film 1 by BOE; step P7, annealing activation is performed at 1500-2000 ℃.
Example 3
As shown in fig. 2, a layer of BSG or PSG masking film 1 with doping concentration varying with thickness is deposited on the surface of the N-epitaxial layer 2 by controlling the flow of the doping gas using a furnace tube, and the film thickness is 1-2 um.
As shown in fig. 3, a photoresist 5 of 1.5-2um is coated on the masking film 1, and an ion implantation pattern is defined by a photolithography process.
As shown in fig. 4, the masking film 1 is wet-etched using BOE in an amount of 80% to 90% of the film thickness of the masking film 1.
As shown in fig. 5, using a single wafer type etching machine, the remaining masking film 1 is wet-etched by DHF, so that the final masking film 1 forms a concave arc groove with a concave edge, the etching time is controlled to be 120% -160% of the over-etching amount, and the photoresist 5 is removed.
As shown in fig. 6, the device is subjected to segmented ion implantation under the conditions of temperature of 400-600 ℃ and deflection angle of 3-7 °.
As shown in fig. 7, the masking film 1 is removed by BOE, and then thermal annealing at 2000 ℃ is performed to activate the implanted ions, so as to form a PN junction of SiC with small curvature.
It is well within the knowledge of a person skilled in the art to implement the system and its various devices, modules, units provided by the present invention in a purely computer readable program code means that the same functionality can be implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description has described specific embodiments of the present invention. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1. A manufacturing method for forming a PN junction structure is characterized by comprising the following steps:
step T1, depositing SiO by furnace tube 2 Setting flow value parameters at multiple points in the film process to regulate and control the flow of the doping gas, thereby depositing the film with the doping concentration changing along with the film thickness;
step T2, SiO deposited by BOE buffer etching liquid and DHF wet etching furnace tube 2 Film, using SiO of different doping concentrations 2 The films have different etching rates in BOE and DHF, and arc-shaped SiO2 films with the edges being changed in film thickness are etched to be used as masking films (1) for ion implantation;
and step T3, removing the masking film (1) by a wet method after segmented ion implantation, and carrying out annealing activation to form a PN junction with small curvature.
2. The manufacturing method of forming a PN junction structure of claim 1, wherein: in step T2, the ion implantation position of the masking film (1) is provided with a groove;
the groove is in a round table shape, and two sides of the half section of the groove are provided with concave arcs.
3. A method for manufacturing a masking film for forming a PN junction structure according to claim 1, comprising the steps of:
step S1, depositing a masking film (1) on the surface of the N-epitaxial layer (2) by using a furnace tube;
step S2, coating a photoresist (5) on the masking film (1), and defining an ion implantation pattern by photoetching;
step S3, etching a masking film (1) with a concave arc edge by using a BOE + DHF wet method;
step S4, removing the photoresist on the surface by dry method (5);
step S5, performing high-temperature segmented ion implantation;
step S6, removing the masking film (1) by BOE;
step S7, annealing activation is carried out at 1500-2000 ℃.
4. The method of manufacturing a masking film for forming a PN junction structure according to claim 3, wherein: in step S1, the mask film (1) is a BSG or PSG film of 1-2 um.
5. The method of manufacturing a masking film for forming a PN junction structure according to claim 3, wherein: in step S3, the BOE concentration ratio is 20: 1-6: 1, the concentration ratio of DHF is 10: 1 or 20: 1.
6. the method of manufacturing a masking film for forming a PN junction structure according to claim 3, wherein: in step S3, the etching time is set to 120% to 160% of the over-etching amount according to the film thickness of the masking film (1) at the time of etching.
7. The method of manufacturing a masking film for forming a PN junction structure according to claim 3, wherein: in step S2, the photoresist (5) has a thickness of 1.5-2 um.
8. The method of manufacturing a masking film for forming a PN junction structure according to claim 3, wherein: in step S5, the ion implantation temperature is 400-600 ℃.
9. A PN junction structure manufactured by the manufacturing method for forming a PN junction structure according to claim 2, comprising: the N-epitaxial layer (2), the N + substrate (3) and the ion implantation P + type region (4);
one side of the N-epitaxial layer (2) is connected with the N + substrate (3), and one side of the N-epitaxial layer (2) back to the N + substrate (3) is provided with an ion implantation P + type region (4).
10. The PN junction structure of claim 9, wherein: one side of the N-epitaxial layer (2), which is back to the N + substrate (3), is connected with the masking film (1);
the position of the groove corresponds to the position of the ion-implanted P + type region (4).
CN202210452775.7A 2022-04-27 2022-04-27 Manufacturing method for forming PN junction structure, manufacturing method for masking film and PN junction structure Pending CN114883181A (en)

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