CN1148804C - Highly integrated chip-on-chip packaging - Google Patents

Highly integrated chip-on-chip packaging Download PDF

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Publication number
CN1148804C
CN1148804C CNB991070917A CN99107091A CN1148804C CN 1148804 C CN1148804 C CN 1148804C CN B991070917 A CNB991070917 A CN B991070917A CN 99107091 A CN99107091 A CN 99107091A CN 1148804 C CN1148804 C CN 1148804C
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CN
China
Prior art keywords
chip
set
connecting
chips
connected
Prior art date
Application number
CNB991070917A
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Chinese (zh)
Other versions
CN1241032A (en
Inventor
克罗德・露易斯・伯汀
克罗德·露易斯·伯汀
・乔治・弗伦斯
托马斯·乔治·弗伦斯
约翰・霍威尔
韦恩·约翰·霍威尔
・朱里斯・斯泊吉斯
埃德蒙·朱里斯·斯泊吉斯
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国际商业机器公司
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Priority to US09/105,419 priority Critical patent/US5977640A/en
Application filed by 国际商业机器公司 filed Critical 国际商业机器公司
Publication of CN1241032A publication Critical patent/CN1241032A/en
Application granted granted Critical
Publication of CN1148804C publication Critical patent/CN1148804C/en

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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

一种高集成度芯片上芯片封装,它包含:至少两个叠置的芯片上芯片组件,其中每一个芯片上芯片组件至少具有二个有源区电连接在一起的独立芯片,其中所述二个芯片的所述有源区彼此面对;以及用来将所述芯片电连接到外部电路的互连衬底,该互连衬底包含:连接于芯片的有源区的第一组连接元件;用来连接到所述外部电路的第二组连接元件;以及具有导电线条的衬底,所述导电线条将所述第一组连接元件连接到所述第二组连接元件。 Chip on a highly integrated chip package, comprising: at least two chips stacked chip assembly, wherein each of the chip-chip assembly having at least two separate chips connected together electrically active regions, wherein the two the active area of ​​the chips face each other; and means for electrically connecting the chip to an external circuit interconnection substrate, the interconnect substrate comprising: an active area of ​​the chip is connected to a first set of connection elements ; to a second set of connections for connecting the external circuit element; and a substrate having a conductive line, said first set of conductive lines to said connecting element is connected to the second group of elements. 其中所述第二组连接元件包含:与所述至少两个芯片上芯片组件中一个的外侧面齐平的第一组连接件;以及与所述至少两个芯片上芯片组件中另一个的外侧面齐平的第二组连接件。 Wherein said second set of connecting elements comprises: a first set of connecting member to the outer surface of the at least two components in a chip-on-chip flush; and at least the other of the two chips in the chip assembly outer flush with the side of a second set of connections.

Description

高集成度芯片上芯片封装 Highly integrated chip on chip packages

本申请涉及到二个共同未决的申请:Bertin等人的题为“半导体封装件中的微弯曲工艺”的美国申请No.09/105382和Ference等人的题为“改变特性的芯片上芯片互连”的美国申请No.09/105477。 The present application is related to two co-pending applications: Bertin et al., Entitled "semiconductor package microbending process," U.S. Application No.09 / 105382 and Ference et al, entitled "Chip-on-chip changed characteristic interconnection "US application No.09 / 105477. 相关的申请被转让于记载的受让人,因而同时提出申请,此处并列为参考。 Related applications are assigned to the assignee described thus apply simultaneously, in parallel herein by reference.

技术领域 FIELD

本发明一般涉及到半导体器件,更具体地说是涉及到半导体器件中的芯片上芯片封装。 The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device on a chip in a chip package.

背景技术 Background technique

在电子开发和封装中,最近50年已发生了巨大的进步。 In the electronic development and packaging in the last 50 years great progress has occurred. 集成电路密度已经并继续高速提高。 High-speed integrated circuit density has been and continues to improve. 但80年代之前,制作在芯片中的电路外部的互连电路密度的相应提高跟不上集成电路密度的提高。 However, before the 1980s, a corresponding increase in circuit density interconnect circuits external to keep up with the production increase in the integrated circuit chip density. 出现了许多新的封装工艺。 Many new packaging technology. 一个特定的工艺称为“芯片上芯片组件”工艺。 A particular process referred to as "chip-on-chip components" process. 本发明涉及到芯片上芯片组件的具体技术领域。 The present invention particularly relates to the technical field on the chip of the chip assembly.

许多情况下,比之设计新的衬底集成电路,可以更快速而便宜地制造芯片上芯片组件。 In many cases, than the design of new integrated circuit substrate can be more quickly and cheaply manufacturing the chip-on-chip components. 芯片上芯片组件工艺由于密度的提高而显现出优点。 Chip assembly process due to increased chip density and show advantages. 由于密度的提高,在信号传播速度和与其它装置不协调的器件总重量方面得到了同样的改进。 Due to increased density to obtain the same improvement in signal propagation speed and uncoordinated with other terms means the total weight of the device. 目前的芯片上芯片组件结构通常由直接粘合到一系列集成电路元件的印刷电路板衬底组成。 The current chip by the chip assembly structure is typically bonded directly to a printed circuit board substrate composed of a series of integrated circuit components.

还有许多不同的技术领域,与如何将粘合有芯片上芯片组件的衬底从外部电连接到衬底上的电路有关。 There are many different technical fields, and how the adhesive with a substrate chip of the chip assembly from the external electrical connection to the circuit on the substrate related. 这些技术领域包括引线键合、载带自动键合(TAB)、倒装TAB和倒装芯片。 These areas include wire bonding techniques, tape automated bonding (TAB) is contained, the flip-TAB and flip chip. 在下列美国专利中可找到一些例子:1994年6月授予Fogal等人的美国专利No.5323060“具有叠层芯片分布的多芯片组件”、1997年2月授予B0ne等人的美国专利No.5600541“具有由介质载带制作的分立芯片载体的垂直IC芯片叠层”、1996年2月授予Korneld等人的美国专利No.5495394“多芯片组件中的三维管芯封装”、以及1995年3月授予Rostoker等人的美国专利No.5399898“采用倒装芯片管芯的多芯片半导体分布”。 Some examples can be found in the following US Patents: June 1994 awarded Fogal et al., US Patent No.5323060 "has distributed multi-chip module chip stack," in February 1997 awarded B0ne et al., US Patent No.5600541 "discrete chip carrier having a dielectric carrier tape made of a vertical stack of IC chip", granted February 1996 Korneld et al U.S. Patent No.5495394 "in a three-dimensional multi-chip module package die", and March 1995 U.S. Patent No. Rostoker et al No.5399898 "flip-chip die, multi-chip semiconductor distributed."

不幸的是,这些技术很昂贵,而且在大多数情况下无法返工(亦即清除和代换)封装件的组元,从而降低了成品率并增加了成本。 Unfortunately, these techniques are expensive and in most cases can not be reworked (i.e., removal and substitution) component package, which reduces the yield and increases the cost. 芯片尺寸的个性化设计也受到严重限制。 Personalized design the chip size is also severely limited. 目前,芯片能够在晶片级或封装级进行个性化设计。 Currently, the chip can be personalized at the wafer level or package level. 由于在封装之前,在晶片后制造工艺中不能够个性化设计芯片,而无法得到产品应用的明显灵活性和制造成本的优点。 Since before packaging, after the wafer manufacturing process can not be personalized chip design, and can not obtain significant advantages and flexibility of the manufacturing cost of the product application.

发明内容 SUMMARY

因此,本发明的优点是提供消除上述和其它限制的芯片上芯片元件、互连、及其制造方法。 Thus, the advantages of the present invention is to provide the chip to eliminate the above and other limitations of chip components, interconnects, and a manufacturing method.

本发明提供一种高集成度芯片上芯片封装,它包含:至少两个叠置的芯片上芯片组件,其中每一个芯片上芯片组件至少具有二个有源区电连接在一起的独立芯片,其中所述二个芯片的所述有源区彼此面对;以及用来将所述芯片电连接到外部电路的互连衬底,该互连衬底包含:连接于芯片的有源区的第一组连接元件;用来连接到所述外部电路的第二组连接元件;以及具有导电线条的衬底,所述导电线条将所述第一组连接元件连接到所述第二组连接元件,其中所述第二组连接元件包含:与所述至少两个芯片上芯片组件中一个的外侧面齐平的第一组连接件;以及与所述至少两个芯片上芯片组件中另一个的外侧面齐平的第二组连接件。 The present invention provides a highly integrated chip-on-chip package, comprising: at least two chips stacked chip assembly, wherein each of the chip-chip assembly having at least two separate chips connected together electrically active region, wherein the active area of ​​the two chips face each other; and means for electrically connecting the chip to an external circuit interconnection substrate, the interconnect substrate comprising: an active area of ​​the chip is connected to a first set of connection elements; for connection to the second set connected to an external circuit element; and a substrate having a conductive line, the conductive line connecting said first set of connector elements to said second set of connecting elements, wherein the second set of connecting elements comprises: a first connecting part on the at least two chips in the chip assembly a flush outer surface; at least two other chips in the chip assembly and the outer surface flush a second set of connections.

在上述芯片上芯片封装的一个实施例中,该至少二个芯片的工艺不同。 In one embodiment, the die chip package, the chip of at least two different processes.

在上述芯片上芯片封装的一个实施例中,所述外部电路是可插接的连接。 Said chip on a chip package embodiment, the external circuit is connected to the plug.

在上述芯片上芯片封装的一个实施例中,所述互连衬底与所述芯片上芯片组件的所述至少二个芯片中的一个的高度相同。 A chip on the chip package of the embodiment, the interconnection of the chip on the substrate and chip assembly to at least the height of one of two identical chips.

在上述芯片上芯片封装的一个实施例中,多个芯片上芯片组件相互堆叠放置。 In one embodiment, the die chip package, a plurality of chips are stacked chip assembly is placed.

在上述芯片上芯片封装的一个实施例中,第一组连接件包括焊料球。 In one embodiment, the die chip package, the connection member comprises a first set of solder balls.

在上述芯片上芯片封装的一个实施例中,第二组连接件包括金属焊点。 In one embodiment, the die chip package, the second set of pads comprises a metal connecting member.

借助于具有至少二个功能完全独立的芯片且电连接在一起的芯片上芯片组件以及用来将芯片电连接到外部电路的芯片上芯片元件连接/互连,实现了本发明的优点。 By means of a completely independent function having at least two chip-on-chip and the electrical chip components connected together on a chip and a chip element for electrically connecting the chip to an external circuit connections / interconnections, to achieve the advantages of the present invention.

从如附图所示的本发明最佳实施例的更确切的描述中,本发明的上述和其它的优点和特定将更为明显。 From a more precise description of preferred embodiments of the present invention as shown in the accompanying drawings, the above and other advantages of the present invention and particular will become apparent.

附图说明 BRIEF DESCRIPTION

以下结合附图来描述本发明的最佳示范实施例,在这些附图中,相似的参考号表示相似的元件。 Preferred exemplary embodiment of the present invention will be described accompanying drawings, in the drawings, like reference numerals refer to like elements in conjunction with the following.

图1是根据本发明最佳实施例的具有第一示范芯片上芯片元件连接的芯片上芯片元件的剖面图;图2、3和4是根据本发明最佳实施例的具有第二、第三和第四示范芯片上芯片元件连接的芯片上芯片元件的剖面图;图5是采用图4的示范芯片上芯片元件连接的芯片上芯片封装件的剖面图;图6是具有第五示范芯片上芯片元件连接的图1的芯片上芯片元件的剖面图;图7是采用图6的示范芯片上芯片元件连接的芯片上芯片封装件的剖面图;图8、9、10、11、12和13剖面图示出了根据本发明第二实施例的芯片上芯片元件的制造顺序;图14是根据本发明第三实施例的芯片上芯片元件的剖面图;图15是采用图14的芯片上芯片元件的芯片上芯片封装件的剖面图;图16是根据本发明第四实施例的芯片上芯片元件的剖面图;图17是根据本发明第五实施例的芯片上芯片元件的剖面图;图1 FIG. 1 is a sectional view of a first exemplary on-chip chip component on a chip connected to the chip element of the preferred embodiment of the present invention; FIGS. 2, 3 and 4 is a second preferred embodiment according to the third embodiment of the present invention. and a cross-sectional view of a chip-on-chip components fourth exemplary on-chip connected to the chip element; FIG. 5 is a sectional view of the chip using the chip package of FIG. 4 an exemplary chip-on-chip element of the connection; Figure 6 is a fifth exemplary chip sectional view of a chip on the chip component connected to chip elements of FIG. 1; FIG. 7 is a cross-sectional view of a chip using the chip package of FIG exemplary chip-chip connecting element 6; 8,9,10,11,12 and 13 in FIG. sectional view illustrating a chip according to the manufacturing sequence of the present invention, the second embodiment of the chip element; FIG. 14 is a cross-sectional view of a chip-on-chip device of the third embodiment of the present invention; FIG. 15 is the use of chip-on-chip 14 of FIG. sectional view of the chip package on the chip element; FIG. 16 is a sectional view on a chip of the fourth embodiment of the present invention is embodiment a chip element; FIG. 17 is a sectional view of a fifth embodiment of the chip of the present invention, the chip element; FIG. 1 8是采用图17的芯片上芯片元件的芯片上芯片封装件的剖面图。 8 is a sectional view of the chip using a chip-on-chip package element chip 17 of FIG.

具体实施方式 Detailed ways

参照图1,示出了根据本发明最佳实施例的第一示范芯片上芯片元件10。 Referring to FIG. 1, there is shown a first preferred exemplary embodiment of a chip of the present invention, a chip component 10. 芯片上芯片元件10包含第一芯片30、第二芯片40和芯片上芯片元件连接20。 Element chip 10 on the chip 30 comprising a first chip, the second chip 40 and the chip-on-chip element 20 is connected. 第一芯片30的有源区35通过诸如C4(控制熔塌芯片连接)焊料球连接50之类的芯片间连接或光子互连,被电连接到第二芯片40的有源区45。 The active region 35 of the first chip 30, such as by C4 (controlled collapse chip connection) solder balls or photonic interconnect connection between the chip 50 and the like, are electrically connected to the active region 45 of the second chip 40. 焊料球连接50提供了芯片间联系的高性能电通路。 Providing the solder balls 50 connected to a high-performance electrical path between the chip contact. 这一互连与芯片电学布线的固有高性能一起,大大地降低了第一芯片30和第二芯片40二者的芯片外驱动器(未示出)的尺寸和功率。 The inherent high performance electrical interconnect wiring with the chip, greatly reducing both the first chip 30 and second chip 40 chip size and power of the drive (not shown). 虽然此例和以后的例子具体示出了焊料球和焊料柱,但应该理解,也可以采用诸如聚合物金属复合物互连、电镀铜柱、微锁连接等等之类的不同组分构成的其它互连。 Although this embodiment and subsequent examples specifically illustrate solder balls and the solder column, it should be appreciated that different polymers may be used such as a metal composite component interconnect plating copper pillar, micro-lock connector of the like configuration other interconnection.

在此特定例子中,芯片上芯片元件连接20是连接于第一芯片30的焊料柱22。 In this particular example, the chip-chip connecting element 20 is connected to the first chip 30 of solder pillars 22. 焊料柱22使得能够将芯片上芯片元件10一般通过衬底连接到外部电路。 It makes it possible to solder pillars 22 on the chip element chip 10 is typically connected to an external circuit through the substrate.

图2示出了第二示范芯片上芯片元件,其中芯片上芯片元件连接20包含焊料球。 FIG 2 shows a second exemplary chip on the chip element, wherein the connecting element 20 comprises a chip-chip solder balls. 在图1和2中,在IBM Dkt,No.BU9-98-011的相关应用中,可找到制造焊料柱和焊料球的示范性方法。 In FIGS. 1 and 2, in the related applications IBM Dkt, No.BU9-98-011, the exemplary method can be found for producing a solder ball and the solder column. 也可以通过下列步骤来制造焊料柱和焊料球:1)制造具有可焊金属焊点的第一芯片。 You may be produced and the solder ball of solder columns by the following steps: 1) producing a first chip having a solderable metal solder joint. 可以用作焊料柱焊点的外围区焊点的直径可以是例如125微米,间距为250微米。 Solder pads may be used as a column of pads in the peripheral region may be for example 125 microns in diameter, a pitch of 250 microns. 中心区焊点的直径可以是50微米,间距为100微米。 The diameter of the central region may be pads 50 microns and a pitch of 100 microns.

2)制造具有C4焊料球阵列的第二芯片。 2) manufacturing the second chip having an array of C4 solder balls. C4的组分可以是Pb∶Sn=97∶3,且C4应该与第一芯片中心区焊点的间距一致。 C4 components may be Pb:Sn = 97:3, and C4 to be consistent with the first chip pad spacing of the central region.

3)将第一芯片固定到第二芯片。 3) fixing the first chip to the second chip. 通过标准的芯片拾放技术(CPP),或通过诸如不用清除的助熔剂、PADS、松香助熔剂与炉回流结合的工艺,可以做到这一点。 By standard pick and place technology chip (the CPP), or by a process such as a flux without clearance, the PADS, rosin flux and reflux furnace binding, can do this.

4)将焊料柱或焊料球固定到第二芯片。 4) The solder ball or solder column is fixed to the second chip. 通过焊料注入铸模,可以做到这一点。 Solder into a mold, you can do this.

5)将芯片上芯片元件连接到衬底。 5) The chip components on a chip connected to the substrate. 借助于通过标准的放置与连结工艺将易熔焊料连结在衬底TSM焊点上,可以做到这一点。 By means of a standard coupling process and placing the eutectic solder connecting TSM pads on the substrate, this can be done.

图3和4示出了芯片上芯片元件的第三和第四例子,其中的芯片上芯片元件连结20包含焊料球26和布线25(图3)或丝焊28(图4)。 3 and 4 illustrate a third and fourth example of a chip component on a chip, wherein the chip-chip connecting element 20 comprises solder balls 26 and the wiring 25 (FIG. 3) or wire bonds 28 (FIG. 4). 在图3中,在衬底57中制作空腔55,使第二芯片40的顶部与衬底57的顶部的高度相同。 In Figure 3, the cavity 55 made in the substrate 57, the second top die 40 and the same height as the top of the substrate 57. 焊料球26则可以与连接的焊料球50尺寸相同,从而将芯片上芯片元件连接到衬底57。 Solder balls 26 may be identical to the size of solder balls 50 connected to connect the chip components on the chip 57 to the substrate.

图5示出了采用图4的芯片上芯片元件10A的芯片上芯片封装件。 FIG. 5 shows a chip package using chip-on-chip elements 10A chip 4 of FIG. 丝焊28连接于衬底72的顶侧。 Bonding wire 28 is connected to the top side 72 of the substrate. 衬底72的底侧包含用来将芯片上芯片封装件连接于不同封装级的焊料球76。 The bottom side of the substrate 72 to the upper chip comprises a chip package connected to a different package level solder balls 76. 粘合剂71将芯片上芯片元件10A机械连接于衬底72。 The adhesive 71 on the chip is mechanically connected to chip elements 10A of the substrate 72. 树脂挡条66和包封剂64保护着芯片30和40,并为丝焊和芯片结构60提供强度。 Crosspiece 66 and the resin encapsulant 64 protects the chip 30 and 40, and to provide strength to the structure of the chip 60 and wire bonding. 金属盖62提供了紧凑、耐用而热增强的芯片上芯片封装件。 The metal cap 62 provides a compact, durable and thermally enhanced chip chip package.

如图6和7可见,芯片上芯片元件10B的芯片上芯片元件连结20包含焊料球插件32。 6 and 7 can be seen, the chip component 10B chip on the chip-chip connecting element 20 comprises a plug 32 solder balls. 焊料球插件32提供了到衬底的电互连以及第二芯片40的尺寸所需的高度。 Solder balls to provide electrical plug 32 and the interconnection substrate 40 of the second chip size desired height. 焊料球插件32由连接于一个芯片40的有源区的第一组焊料球、连接于外部电路的第二组焊料球、以及第一组和第二组焊料球之间的导电通道组成。 The solder balls connected to the insert 32 by a first set of one chip solder balls 40 of the active region, a second set of solder balls connected to an external circuit, and a conductive path between the first and second solder balls group consisting. 此通道被不导电的材料包围。 This channel is surrounded by non-conductive material. 图7示出了采用图6的芯片上芯片元件10B的芯片上芯片封装件。 FIG. 7 shows a chip using on-chip elements 6 on the chip package of FIG chip 10B. 焊料球插件被连接于衬底72的顶侧。 Solder ball plug is connected to the top side of the substrate 72. 衬底72的底侧包含用来将芯片上芯片封装件连接于不同级封装件的焊料球76。 The bottom side of the substrate 72 to the upper chip comprises a chip package connected to the solder balls of the package 76 different levels. 散热器74通过粘合剂78被连接到第一芯片30。 A first radiator 74 is connected to the chip 30 via an adhesive 78. 散热器使芯片上芯片元件10B得以散热。 10B so that the heat sink element on a chip to chip cooling.

图1-7和后面例子的芯片上芯片元件的一些优点包括:可以用不同的半导体工艺来制造芯片30和40,并将它们连接起来而不受这些工艺用于单一芯片时所固有的限制。 Some advantages of the examples of FIGS. 1-7 and the following chip element chip comprising: a chip 30, and can be produced with different semiconductor processes 40, and connecting them when the process is used without the limitations inherent in a single chip. 例如,芯片30可以是逻辑芯片,而芯片40可以是DRAM芯片,在芯片上芯片元件级上产生逻辑/DRAM组合。 For example, chip 30 may be a logic chip, and the chip 40 may be a DRAM chip, generates a logic / DRAM chip on the chip combination element level. 第二,比之在每个芯片上提供所有功能和电路的单个芯片来说,芯片30和40单独地说是较小而较不复杂的。 Second, the ratio of all circuits and functions on a single chip each chip, the chips 30 and 40 are said to be individually less complex and smaller. 第三,大量存储器可以位于处理器的紧邻。 Third, the large amount of memory may be located in close proximity to the processor. 第四,由于芯片上芯片元件的极为平坦的金属特性,而具有较大的互连密度。 Fourth, since the characteristic of extremely flat metal chip components on a chip, having a greater density interconnection. 最后,本发明的芯片上芯片元件提供了比提供同样功能的简单高集成芯片更低的成本、更低的功率和更高的性能。 Finally, the chip-on-chip device of the present invention provide a lower functionality than simply providing the same high-integrated chip cost, lower power and higher performance.

图8-13剖面图示出了根据本发明第二实施例的芯片上芯片元件的制造顺序。 Figure 8-13 illustrates a cross-sectional view on the chip fabrication sequence of a second embodiment according to the present invention, the chip element. 在图8中,示出了具有有源电路和互连层145的芯片晶片140。 In FIG 8, it shows a wafer 140 having an active circuit chip and the interconnect layer 145. 晶片140可以是例如硅晶片、GaAs晶片、SiGe晶片等。 The wafer 140 may be, for example, a silicon wafer, GaAs wafer, SiGe wafer. 有源电路和互连层145包含外部互连所需的结构和图形。 The active layer 145 and the interconnect circuitry comprises a desired pattern structure and external interconnection. 在图9中,二类元件被固定到晶片140:集成电路(IC)芯片130和焊料球插件(也称为隔件)32。 In Figure 9, two types of member 140 is fixed to the wafer: an integrated circuit (IC) chip 130 and the solder ball plug (also referred to as spacer) 32. IC芯片130被电连接于晶片140中的有源电路,并提供较高水平的集成电路功能。 The IC chip 130 is electrically connected to the active circuitry in the wafer 140, an integrated circuit and to provide a higher level of functionality. 可以使用诸如带包封的焊料球和丝焊之类的电连接。 Can be electrically connected using solder balls, such as a wire bonding and a encapsulating with like. 焊料球插件32提供了晶片140上有源电路层145和IC芯片130有源电路层侧形成的平面之间的电通路。 Solder ball plug 32 is provided on the electrical path between the plane 140 active circuitry layer wafer 145 and the IC chip 130 formed on the active layer side circuit. 虽然在本例子中具体示出了焊料球插件32,但也可以使用诸如具有通道孔的硅晶片、多层陶瓷和有机PCB间隔之类的其它间隔。 Although in the present example specifically shows a plug solder balls 32, but other spacing may be used such as a silicon wafer-based channel bore, and the organic multilayer ceramic PCB interval. 同时,虽然在本例子中用焊料球来将IC芯片130和焊料球插件32连接到晶片140,但也可以采用诸如导电环氧树脂、PMC胶、各向异性导电粘合剂和瞬变液相键合之类的其它互连方法。 Meanwhile, although in the present example by solder balls to the IC chip 130 and the solder ball plug 32 is connected to the wafer 140, may also be employed, such as a conductive epoxy, glue the PMC, the anisotropic conductive adhesive and transient liquid phase other bonding interconnection method or the like. 可以用焊料球包封体(未示出)来包围焊料球。 It may be encapsulated solder balls (not shown) surrounding the solder balls.

如图10所见,在整个表面上淀积共形涂层34(例如对二甲苯)。 As seen in Figure 10, a conformal coating 34 is deposited (e.g., para-xylene) over the entire surface. 然后如图11所示,用机械和/或化学方法整平此涂层。 Then, as shown in FIG. 11, with mechanical and / or chemical methods for this leveling coating. 整平的一个例子可以是用标准的晶片抛光方法对表面进行机械抛光。 Examples of a flattened surface may be polished using standard mechanical wafer polishing method. 这一整平使结构中焊料球插件32中的互连通道孔出现在表面上。 This leveling passage interconnecting pore structure in the solder ball plug 32 appears on the surface. 这些通道孔构成到外部电路的连接。 These passage holes constituting the connection to an external circuit. 图12示出了在焊料球插件32上制造用于对外部电路互连的焊料球36。 FIG 12 shows a solder ball 32 on the solder ball plug manufacturing an external circuit interconnects 36. 在预定点38处切割芯片上芯片元件,形成能够用焊料球36连接到外部电路的“超芯片”。 38 at a predetermined point on the dicing die chip element, formed by solder balls 36 can be connected to an external circuit "super chip." 图13示出了连接于载体/衬底72的超芯片。 Figure 13 shows a super-chip connection to the carrier / substrate 72. 制造图13所示的超芯片有一些优点。 Ultra chip shown in FIG 13 has some manufacturing advantages. 这些优点包括:用多层不同半导体工艺的非常高的集成度;元件速度、带宽要求和芯片外速度方面的优越性能;组元芯片物理上很小且不需要复杂的电路或制造工艺,导致成品率高和成本低;以及借助于以各种形式连接几个组元元件,能够达到专用化。 These advantages include: a very high degree of integration with multiple layers of different semiconductor process; element speed, bandwidth requirements and speed chip superior performance; on-chip component physically small and does not require complex circuitry or manufacturing process, resulting in the finished high and low cost; and with the aid of several component elements are connected in various forms, customization can be achieved.

图14和15是根据本发明第三实施例的芯片上芯片元件80的剖面图。 14 and 15 are sectional views of the chip 80 on the chip element according to the third embodiment of the present invention. 芯片上芯片元件80包含由二个芯片构成一组的二个组,每个组有电连接于第二芯片的第一芯片30和40以及30A和40A(例如图1中的芯片上芯片元件10)。 Chip 80 on the chip element comprises two groups, each composed of a set of two chips are electrically connected to the first chip 30 and 40A and 40 and 30A of the second chip (for example, a chip element chip 10 in FIG. 1 ). 在此例子中,芯片30和30A的背侧彼此相对。 In this example, the backside of the chip 30 and 30A face each other. 二组芯片通过芯片上芯片元件连接20A(此例子中是互连衬底88)电连接到一起。 20A is connected via two groups of chips on a chip-chip element (in this example are interconnection substrate 88) electrically connected together. 互连衬底88还通过诸如丝焊84、C4连接86和金属焊点连接82之类的电连接,将芯片上芯片元件80连接到外部器件。 Through the interconnection substrate 88, such as a welding wire 84, C4 86 and connector 82 is electrically connected to the metal pads or the like connected to an external device 80 is connected to a chip-on-chip element. 虽然为了说明的目的,在图14和15的芯片上芯片元件80上示出了不同类型的连接,但通常对于一种应用只使用一种类型的连接(亦即,连接82、84和86可以都是例如C4连接)。 Although for purposes of illustration, in FIG chip 15 and the chip component 14 80 show different types of connection, but usually for one application to use only one type of connection (i.e., 82, 84 and 86 can be connected are, for example, C4 is connected). 图15示出了采用图14的芯片上芯片元件80的芯片上芯片封装件。 FIG 15 shows a chip component on a chip on the chip 80 using a chip package 14 of FIG. 二个散热器92通过粘合剂94被连接于芯片30和30A。 Two heat sink 92 is connected to the chip 30 via an adhesive 94 and 30A. 散热器使芯片上芯片元件80得以散热。 The chip on the chip heat sink 80 to heat sink element. 在衬底57中制作空腔55,使第二芯片40的顶部与衬底57的顶部的高度相同。 Production of a cavity 55 in the substrate 57, the second top die 40 and the same height as the top of the substrate 57. 焊料球26则可以与连接的焊料球50尺寸相同,从而将芯片上芯片元件连接到衬底57。 Solder balls 26 may be identical to the size of solder balls 50 connected to connect the chip components on the chip 57 to the substrate. 这样,如根据本发明这一实施例所述,可以将几个各具有分立和特定功能且可能用不同的半导体工艺制造的芯片结合在一起。 Thus, according to this embodiment as described in the present invention, each having several discrete and specific functions, and may combine different semiconductor chip manufacturing process.

图16是根据本发明第四实施例的包含芯片上芯片元件80A的可插接的芯片上芯片封装件的剖面图。 FIG 16 is a cross-sectional view of the plug chip chip package comprising a chip-on-chip device 80A according to the fourth embodiment of the present invention. 芯片上芯片元件80A包含芯片30、30A、40、40A、互连衬底88A、和耦合衬底88B。 80A comprises a chip on the chip element chip 30,30A, 40,40A, interconnection substrate 88A, and coupling the substrate 88B. 在此例子中,芯片上芯片元件80A被包封剂96包封,从而提供一个坚实的元件。 In this example, the chip component 80A is on-chip encapsulant 96 encapsulating, thereby providing a solid element. 互连衬底88A使得能够通过可插接界面电连接到外部电路。 Interconnection substrate 88A can be connected to an external circuit such that the through pluggable electrical interface.

图17是根据本发明第五实施例的芯片上芯片元件80B的剖面图。 FIG 17 is a cross-sectional view of FIG. 80B chip element chip according to a fifth embodiment of the present invention. 除了芯片上芯片元件连接20A包含延伸于芯片上芯片元件80B上下表面的可堆叠的互连衬底88C之外,芯片上芯片元件80B与芯片上芯片元件80(图14)是相似的。 In addition to on-chip-chip connecting member 20A comprises an interconnection substrate 88C 80B extending upper and lower surfaces of the chip components on the chip can be stacked on the chip and the chip element 80B chip-on-chip element 80 (FIG. 14) are similar. 芯片上芯片元件连接20A的上表面包含可熔性金属焊点82,而芯片上芯片元件连接20A的下表面包含焊料球86。 The upper surface 20A of the chip-chip connecting element comprises a fusible metal pad 82, and on-chip-chip connecting member comprises a lower surface 20A of the solder balls 86. 芯片上芯片元件结构80B是三维可堆叠组件的示范单元结构。 Chip element on the chip 80B is an exemplary structure of a three-dimensional structure may be cell stack assembly. 另一种示范单元结构可以包含取消芯片40和40A,并使芯片上芯片元件连接20A延伸跨过芯片30和30A。 Another exemplary cell structure may comprise chip 40 and the cancel 40A, and the chip-chip connecting member 20A extends across the chip 30 and 30A. 图18示出了含有二个图17的芯片上芯片元件单元结构80B的堆叠的组件。 Figure 18 shows a stacked assembly comprising two on-chip 17 chip components of the cell structure 80B.

堆叠的组件和单元结构的一些优点是:首先,可以容易地适应不同尺寸和厚度的芯片。 Some of the advantages of the stack structure of components and units are: First, the chip can be easily adapted to different sizes and thicknesses. 第二,结构是可返工的。 Second, the structure is rework. 第三,各种尺寸的结构都是可能的而没有明显的先决条件。 Third, the structure of various sizes are possible without significant prerequisites. 第四,有可能安排单元结构之间的热问题。 Fourth, it is possible to arrange the thermal problems between cell structures.

于是,根据本发明的芯片上芯片元件和连接,使得能够得到高集成度工艺和可靠而紧凑的半导体封装件。 Thus, according to the chip on a chip and the connecting member of the present invention, it makes it possible to obtain a high integration process and robust, compact semiconductor package. 芯片上芯片封装件还提供了增强的电学性能、机械性能与热性能。 Chip chip package provides enhanced electrical, mechanical and thermal properties.

虽然参照最佳实施例已经具体地描述了本发明,但本技术领域熟练人员能够理解,可以作出上述的和其它的形式和细节的改变而不超越本发明的构思与范围。 While there has been described with particular reference to preferred embodiments of the present invention, but those skilled in the art will appreciate that changes may be made to the above-described and other forms and details without exceeding the spirit and scope of the present invention.

Claims (7)

1.一种高集成度芯片上芯片封装,它包含:至少两个叠置的芯片上芯片组件,其中每一个芯片上芯片组件至少具有二个有源区电连接在一起的独立芯片,其中所述二个芯片的所述有源区彼此面对;以及用来将所述芯片电连接到外部电路的互连衬底,该互连衬底包含:连接于芯片的有源区的第一组连接元件;用来连接到所述外部电路的第二组连接元件;以及具有导电线条的衬底,所述导电线条将所述第一组连接元件连接到所述第二组连接元件,其中所述第二组连接元件包含:与所述至少两个芯片上芯片组件中一个的外侧面齐平的第一组连接件;以及与所述至少两个芯片上芯片组件中另一个的外侧面齐平的第二组连接件。 A highly integrated chip-on-chip package, comprising: at least two chips stacked chip assembly, wherein each of the chip-chip assembly having at least two separate chips connected together electrically active region, wherein the active area of ​​said two chips face each other; and means for electrically connecting the chip to an external circuit interconnection substrate, the interconnect substrate comprising: an active area of ​​the chip is connected to a first set of the connecting element; a second set of connection elements for connecting to the external circuit; and a substrate having a conductive line, said conductive line of said first set of connecting elements connected to the second set of connecting elements, wherein said second set of connecting elements comprises: a first connecting part on the at least two chips in the chip assembly a flush outer surface; and at least two chip-on-chip assembly other of the outer surface flush a second set of connections flat.
2.权利要求1的芯片上芯片封装,其中该至少二个芯片的工艺不同。 Chip on chip package of claim 1, wherein the process at least two different chips.
3.权利要求1的芯片上芯片封装,其中所述外部电路是可插接的连接。 Chip 3. The chip package of claim 1, wherein the external circuit is connected to the plug.
4.权利要求1的芯片上芯片封装,其中所述互连衬底与所述芯片上芯片组件的所述至少二个芯片中的一个的高度相同。 Chip on chip package of claim 1, wherein said same height a of the interconnect substrate and the chip-on-chip assembly of at least two chips.
5.权利要求1的芯片上芯片封装,其中多个芯片上芯片组件相互堆叠放置。 Chip on chip package of claim 1, wherein the plurality of chips are stacked chip assembly is placed.
6.权利要求1的芯片上芯片封装,其中第一组连接件包括焊料球。 Chip on chip package of claim 1, wherein the connecting member comprises a first set of solder balls.
7.权利要求1的芯片上芯片封装,其中第二组连接件包括金属焊点。 Chip on chip package of claim 1, wherein the connecting member comprises a second set of metal pads.
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