WO2003085732A1 - Micro-electro-mechanical systems packaging - Google Patents

Micro-electro-mechanical systems packaging Download PDF

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Publication number
WO2003085732A1
WO2003085732A1 PCT/US2002/006352 US0206352W WO03085732A1 WO 2003085732 A1 WO2003085732 A1 WO 2003085732A1 US 0206352 W US0206352 W US 0206352W WO 03085732 A1 WO03085732 A1 WO 03085732A1
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WO
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plurality
mems die
top
bottom
substrate
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PCT/US2002/006352
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French (fr)
Inventor
Glenn S. West
Aijay Babulal Alai
Venkata Pavanpratap Chemata
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Nano Storage Pte Ltd
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/007Interconnections between the MEMS and external electrical signals
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A micro-electro-mechanical-system 'MEMS' die having a bottom part (24) and a top part (22), the bottom part having a bottom length and a bottom width, the top part having a top length and a top width; at least one of the bottom length and the bottom width being of a greater dimension than the corresponding top length and top width to thereby form an upper surface on the bottom part on which upper surface interconnect pads are provided. A multi-technology module (10) using such a MEMS as well as at least one other die of a different technology, and a substrate (18) for the module, are also disclosed.

Description

Micro-Electro-Mechanical Systems Packaging

Field of Invention

This invention relates to micro-electro-mechanical-systems ("MEMS") and refers particularly, though not exclusively to the use of MEMS in modules having at least one further die of a different process technology.

Definition

Throughout this specification "different process technology" and its grammatical equivalent means a die of a different manufacturing process technology and/ or a different functional technology.

Background to the Invention

Micro-Electro-Mechanical Systems ("MEMS") is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through the utilization of microfabrication technology. While the electronics are fabricated using integrated circuit ("IC") process sequences, the micromechanical components are fabricated using compatible "micromachining" processes that selectively etch away parts of the silicon wafer, or add new structural layers, to form the mechanical and electromechanical devices.

However, MEMS are different from ICs. In addition to electrical interconnections, MEMS have to interact with the environment in many different ways. This adds complexity and functionality to the MEMS packaging, which is not represented in existing IC standards. MEMS devices of different shapes, sizes, functionality, and environmental robustness have been produced. All of these factors need to be represented in standards tailored to MEMS packaging to ensure the continued growth of MEMS technology.

Since MEMS is a relatively young technology, there are no MEMS packaging or MEMS interconnect standards available.

MEMS dies are usually fabricated using 0.6 to 1.0 micron ("u") technology. Current digital and mixed signal chips are fabricated using less 0.18 micron technology. A MEMS system requires integration with digital and mixed signal chips.

MEMS packaging has been identified as a critical element in the practical integration and subsequent commercialization of MEMS devices.

Traditionally, the components are normally mounted un- encapsulated on a substrate where the bare dies are connected to the surface by wire bonding, tape bonding, or flip-chip techniques. The module is then personated by a plastic moulding. The module is then mounted on the PCB in the same way as any other QFP (quad flat pack) or BGA (ball grid array) component.

Increasing I/O count is a predictable trend in the industry due the increased levels of individual device functionality, and the increase in bus width to support higher levels of performance. Supporting I/O counts with the same or reduced package size means a package must support higher I/O densities. One of the most important functions of a package is as the interposer between the IC and the second level interconnect, the PCB. If the substrate and assembly technology cannot support the minimum die size, the die size has to grow to accommodate the package, leading to more expensive solutions. With new silicon generations coming out approximately every 18 months, and with a corresponding gate shrink of approximately 42% each generation, an increasing number of IC designs are becoming pad limited.

A MEMS die can not use the total die area for I/O because most of the area is used for the MEMS structure. MEMS dies need a high number of I/O signal counts to interact with the MEMS structure. So the issue of MEMS connectivity with external devices becomes more critical due less space availability.

In normal, existing IC manufacturing, connections required for the IC are routed to the periphery of the die using an inline pattern, or a staggered pattern. These connections are then routed to the pads that are used for soldering/ connecting to the PCB. The staggered and inline pattern techniques limit the number of pads on the periphery of the die. For example, to make 1000 connections using the traditional staggered pad arrangement will require a die size of approximately 25mm X 25mm.

MEMS dies usually need a large number of signals to control the MEMS structure, and there is no place available for external connections on MEMS structure.

US patent 6297072 is directed at a method of fabrication of a microstructure having an internal cavity. The specification addresses the issue of connecting two MEMS dies together and to provide electrical connectivity between them.

US patent 6309912 is for a method of interconnecting an embedded integrated circuit. The specification discloses how to connect electrical terminations of an integrated circuit die to corresponding circuit traces of a circuit carrying substrate.

US patent 5488256 is titled "Semiconductor Device with Interconnect Substrate". The specification discloses the use of a metal base to hold the substrate and devices. Interconnect is provided using more than one substrate in one plane. Interconnects are provided using wire bonds only.

It is therefore the principal object of the present invention to provide a new standard in MEMS packaging.

Another object of the present invention is to provide integration of at least one MEMS die with at least one other digital and/or analog die.

A further object is to provide a high density interconnect for MEMS dies.

The invention has as other objects one or more of:

(a) a single component containing several modules connected for a combined function;

(b) a smaller overall package when compared to packaged components performing the same function;

(c) reducing the I/O to the system board;

(d) allowing integration of mixed semiconductor technology; and

(e) simplification of board complexity by combining a plurality of devices onto one package, thereby by reducing total opportunities for error at the board assembly level, as well as allowing for a cheaper PCB. Summary of Invention

With the above and other objects in mind, the present invention provides a micro-electro-mechanical- system ("MEMS") die having a bottom part and a top part, the bottom part having a bottom length and a bottom width, the top part having a top length and a top width; at least one of the bottom length and the bottom width being of a greater dimension than the corresponding top length and top width to thereby form an upper surface on the bottom part on which upper surface interconnect pads are provided.

Preferably, the bottom length is greater than the top length and/ or the bottom width is greater than the top width.

The interconnect pads may be arranged in an array of at least one row and at least one column where there is a first plurality of rows and a second plurality of columns, the first plurality being different to the second plurality. The number of rows and the number of columns may vary along the upper surface, the upper surface extending completely around an outer periphery of the top part. Advantageously, the upper surface is of substantially constant width.

The array may be arranged as a series of sub-arrays, each sub- array having the required number of interconnect pads to enable a chip to be connected thereto, a plurality of chips being mounted on the sub-arrays on the upper surface, at least one of the plurality of chips being of a different process technology to the MEMS die, thereby forming a multi- technology module ("MTM").

At least one, but preferable both, of the top part and the bottom part may have a cavity. If both have cavities, the cavities are: vertically aligned, of the same shape, of the same size and have their openings facing each other. A micromachine is mounted in one or both of the cavities. With the present invention there may not be required a peripheral conductor around the periphery of one or both of the cavities. There is preferably provided a conductor connected directly to the micromechanical machine and directly to at least one of the interconnect pads.

In another form, the present invention provides a multi- technology module ("MTM") including at least one substrate, the at least one substrate having at least one hole therein, each of the at least one holes being sized and shaped to accommodate a top part of MEMS die, the MTM including a plurality of further chips at least one of which is of a different process technology to the MEMS die.

If the top part of the MEMS die is of a height less than the thickness of the substrate the hole may be a blind hole. Alternatively, it may be a cavity.

If the top part of the MEMS die is of a height substantially equal to or greater than the thickness of the substrate, the hole will be a through hole.

There may be at least two substrates with one being located above and substantially parallel to the other; or are arranged longitudinally of each other.

In a further form the present invention provides a substrate for a MTM, the substrate having at least one hole therein for receiving therein a top part of a MEMS die, the hole being of substantially the same size and shape as the top part. If the top part of the MEMS die is of a height less than the thickness of the substrate the hole may be a blind hole. Alternatively, it may be a cavity.

If the top part of the MEMS die is of a height substantially equal to or greater than the thickness of the substrate, the hole will be a through hole.

In yet another form, the present invention provides a MEMS die having a bottom part and a top part, at least one of the top part and the bottom part having a cavity, a micromachine being mounted in the cavity, there being at least one conductor extending directly from at least one interconnect pad located around the periphery of at least one of the cavities to the micromachine.

There may be a cavity in each of the top part and the bottom part, the cavities being: vertically aligned, of the same shape, of the same size, and having their openings facing each other.

With this form, there may be no need for a peripheral conductor extending around the periphery of at least one of the cavities.

The bottom part may have a bottom length and a bottom width, the top part have a top length and a top width; at least one of the bottom length and the bottom width being of a greater dimension than the corresponding top length and top width to thereby form an upper surface on the bottom part on which upper surface the interconnect pads are provided.

In another form of the present invention there is provided a MEMS die having a plurality of interconnect pads arranged as a first plurality of rows and a second plurality of columns, the first plurality being different to the second plurality.

In a final form of the present invention there is provided a substrate for a multi technology module, the substrate having a first plurality of arrays each of a plurality of interconnect pads and a second plurality of arrays of a plurality of vias, all arrays being formed in rows and columns.

Each array of pads may be arranged in an array of a first plurality of rows and a second plurality of columns, the first plurality being different to the second plurality; and each array of vias may be arranged in an array of a first number of rows and a second number of columns, the first number being different to the second number.

MTM therefore provides various packaging and interconnect methodologies in addition to standard methods in semiconductor industry.

Description of the Drawings

In order that the present invention may be readily understood and put into practical effect, there shall now be described by way of non-limitative example only preferred embodiments of the present invention, the description being with reference to the accompanying illustrative drawings in which:

Figure 1 is a perspective view of a multi-technology module according to the present invention;

Figure 2 is a front view of the embodiment of Figure 1 ;

Figure 3 is a top view of the embodiment of Figure 1 ;

Figure 4 is a cross-sectional view along the lines and in the direction of arrows 4-4 on Figure 3;

Figure 5 is a bottom view of the embodiment of Figure 1 ; Figure 6 is a top view of a bottom part of a MEMS die according to the present invention;

Figure 7 is a "transparent" top view of the die of Figure 6 with the top part in place;

Figure 8 is a "transparent" front view of the embodiment of Figure 7;

Figure 9 is an illustration of a new arrangement of pads for a MEMS die bottom part according to the present invention;

Figure 10 is an enlarged view of the array of pads of on a part of Figure 9;

Figure 11 is a perspective view of a substrate for the embodiment of Figure 1 ;

Figure 12 is a front view of the substrate of Figure 11;

Figure 13 is an illustration of the foot print layout on the substrate;

Figure 14 is an enlarged view of part of Figure 13;

Figure 15 is a "transparent" view of a lower part of a MEMS die for a multi- technology module.

Figure 16 is a "transparent" front view of the die of Figure

15;

Figure 17 is a perspective view of the module of Figure

15;

Figure 18 is a front view of the module of Figure 15;

Figure 19 is a front view of data storage module according to the present invention;

Figure 20 is an underneath view of the module of Figure 19;

Figure 21 is a top view of the lower substrate of the module of Figure 19; and

Figure 22 is a top view of the upper substrate of the module of Figure 19. Description of the Preferred Embodiment

To first refer to Figures 1 to 5, there is shown a multi- technology module ("MTM") 10 mounted to a printed circuit board ("PCB") 12 using a ball grid array ("BGA") 14.

The MTM 10 is an integration of multiple integrated circuits built in, or with, a number of different process technologies. In this example, there is a first chip 16 mounted to the underneath of a substrate 18. A second chip 20 is provided and which is in the dual construction from having a top part 22, and a bottom part 24 - the parts 22,24 are connected physically and electrically along their sides 26. An overlap 28 region is provided to give an interconnect region between second chip 20 and substrate 18. Top part 22 is located in a hole 23 in substrate 18 with the size and shape of hole 23 being substantially the same as those of top part 22.

A third chip 34 is mounted beneath substrate 18, and a fourth chip 36 is also mounted beneath the substrate 18. The fourth chip 36 is of dual construction having a top part 38 and bottom part 40. The parts 38, 40 are connected physically and electrically along their sides 42. Top part 38 is located in a cavity 39 in substrate 18, the cavity 39 being of a size, shape and height substantially the same as those of the top part 38. A fifth chip 44 is mounted to the top of substrate 18 directly above fourth chip 36.

Any or all of the chips 16, 20, 34, 36 and 44 may be MEMS dies; but in particular chips 20, 36 may be MEMS dies. Of those that are not MEMS dies, at least one is of a different process technology. Dies may be classified by their process technology due to manufacturing or functional differences. For manufacturing differences, dies may have process technologies of l.Ou, 0.8u, 0.6u, 0.5u, 0.35u, 0.25u, 0.18u, 0.13u, O. lOu, and so forth, in traditional to latest order. MEMS, digital and analog dies may be manufactured in any of these different technologies. For functional differences, MEMS dies have a moving machine as part of the die whereas analog and digital dies have no moving parts. An analog die is used with analog signals, a digital die with digital signals, and a mixed die with both analog and digital signals.

The MEMS dies are preferably as illustrated in Figures 6 to 8. Hence, there is a MEMS die 46 having a top part 48, a bottom part 50 electrically and physically connected to the top part 48, and a micromachine 52 mounted relative to top part 48 and bottom part 50. An interconnect surface 54 is formed on the upper surface 56 of bottom part 50 and extends completely around the periphery 58 of top part 48 from the periphery 58 of top part 48 to the periphery 60 of bottom part 50.

The top part 48 is shown as being co-axially mounted on bottom part 50. The mounting of top part 48 may be at any location within the periphery of bottom part 50. If not co-axial, the width of the interconnect surface 54 will vary around the periphery of top part 48. For example, it is possible for the width of interconnect surface 54 to be different along each of the sides of top part 48. It is possible for two sides of the top part 48 to vertically align with the sides of bottom part 50. In that case the periphery of top 48 extends for the remaining two sides only.

At least one, but preferably both, of the top part 48 and bottom part 50 has a generally rectangular, cavity 62, 64 respectively, in which the micromachine 52 is located. The cavities 62, 64 are vertically aligned and may extend for all or part of the full heights of top part 48 and bottom part 50. There are a top cover 66 and bottom cover 68 to close the cavities 62, 64. The covers 62, 64 may be integral with and formed with the top part 48 and bottom part 50 respectively. The cavities 62, 64 are of the same shape, which is preferably the same shape as top part 48 and bottom part 50 respectively. Although shown as rectangular, any suitable size and shape may be used for either or both of the cavities 62, 64. The sizes and shapes used will be significantly influenced by the nature and structure of the micromachine 52.

From an interconnect pad 70 a conductor 72 connects pad 70 directly to the micromachine 52. Therefore, a peripheral conductor around the inner periphery of interconnect surface 54 may not be required.

As shown on Figures 7, 9 and 10, on the interconnect surface 54 an array 74 of interconnect pads 76 is provided. The pads 76 of array 74 are arranged in rows 78 and columns 80 rather than the usual staggered array. There may be any required number of rows 78, and columns 80. As illustrated in Figure 9, there are four columns on the sides and three on the ends; on Figure 7 there are three on the sides and the ends; and on Figure 6 there are four on the sides and the ends. The number of rows is as required. The pad-to-pad pitch may be as low as 200 microns, and the pad diameter may be as low as 60 microns. The array 74 may have the rows 78 and columns 80 as close as 100 microns to the inner and outer edges of interconnect surface 54.

The conductors of the MEMS die are routed directly to the pads 76 of array 74 from the inner part of die 46. As the cavities 62, 64 contain the micromachine 52, the inner part of the 46 cannot be used for connections. By increasing the numbers of rows 78 and/or columns 80, the number of pads can be increased. Therefore, the MEMS die 46 can be made smaller. Ultimately, for a given micromachine 54, the limits in size reduction will not be pad limits as exists at present. As is stated earlier, using existing technology, a MEMS die with 1000 connections would normally require a die size of approximately 25mm X 25mm. Using the present invention, the die size with the same numbers connected may be as low as 10mm X 10mm.

Furthermore, the use of the present invention allows connections for a MEMS die to be any known technique including, for example: flip chip with solder balls; flip chip without solder balls; or any advanced technology for chip-to- chip interconnects, and chip-to-PCB interconnects.

Figures 11 to 14 provide details of the substrate 18. The substrate 18 may be used as a common base to hold MEMS and other dies, and well as providing interconnects between them. Holes 82 (including holes 23 and 39), which may be through holes as illustrated or may be cavities (blind holes), are provided for the top parts 22, 38 of MEMS dies 46 (being chips 20, 36). If the top parts 22, 38 are of a height less than the overall thickness of the substrate 18, the holes 82 may be blind holes (cavities) or through holes. If, however, the top part 48 is of a height substantially the same as or greater than the thickness of the substrate 18, the holes 82 will be through holes. By having holes 82 accommodating the top parts 48, the overall height of the assembly is reduced. The substrate 18 may be of any suitable material for a PCB, including silicon and /or an organic material. For example, FR4, BT normally used for printed circuit boards, and/ or silicon wafer normally used for integrated circuit manufacture, may be used. The substrate 18 may be a single layer, or multi-layer. The substrate 18 may have a footprint to connect all components the complete MTM assembly, and to connect the MTM to the PCB or the like using substrate interconnect pads 84. These may have a lesser connection count.

Figure 11 also shows the pad 76 and via 86 arrangement which is shown in more detail in Figure 13, which shows a part of substrate 18 around a cavity 82 with the pad 76 and via 86 arrangement. Figure 14 shows a part of that pad 76 and via 86 arrangement on an enlarged scale. As can be seen, the pads 76 and vias 86 are again arranged in rows and columns on the same basis as those on the MEMS die described earlier with reference to Figures 7 to 10. The pad 76 and via 86 arrangement in rows and columns is to facilitate the maximum number of connections in a small space, and with ease of routing. The pads 76 may be connected to pads of other dies through the vias 86, and the inner layer of the substrate 18 as is normal for a multi-layer PCB. The vias 86 may be filled, or may be plated through the hole ("PTH"). The via 86 diameter may be as low as of the order of approximately 160 microns, and the via hole 88 diameter may be of the order of approximately 80 microns. The conductors may be in any layer of substrate 18.

As such, the substrate 18 may be of any suitable form or construction to allow the respective chips to perform their respective functions to achieve the desired result. As stated earlier, the nature and function of the chips may vary the routing as may be required for effective communication between the chips. By using the substrate for the interconnects, production costs may be reduced. Figures 15 to 18 show a MEMS die for a Multi-Technology Module, created using the present invention. The bottom part 50 has the array 74 arranged as a series of arrays 90, 92, 94, 96, 98, 100, 102, 104 and 106. Pads 76 are arranged in differing combinations of rows and columns to enable different chips (108 to 124) to be placed thereon and connected thereto (Figures 17 and 18). There is a plurality of conductors 72 each connected to a different pad 76, and in this example the pads 76 are in two arrays 92 and 100 for chips 110 and 118. As a result of the connections being directly from the MEMS die to the chips 110 and 118, the signal quality should be high.

MEMS devices such as this are useful when there are considerable dimensional restraints (but not necessarily costs restraints). The chips 108 to 124 may be of any functionality and /or type. The assembly may be encapsulated to protect it and its components from the external environment.

Figures 19 to 22 show a Multi-Technology Module according to the present invention. This is different to that of Figures 1 to 5 in that the substrate 18 is mounted above second substrate 30, with interconnect pads 126 at the periphery of the underneath of the two substrates and/ or on both top and bottom of second substrate 30. Substrates 18, 30 may be as shown in Figures 9 to 12, although substrate 18 may not have any cavities, and substrate 30 may have one hole 82, which may not be a cavity.

Underneath substrate 30 is mounted (and electrically connected thereto) an ADC/DAC chip 128, and controller 130. A MEMS die 132 is also mounted beneath substrate 30 and has its top part 134 extending into hole 82. A flash chip 136 and SDRAM chip 137 are mounted on and connected to the top of substrate 30. The power dies 138, 140, 142 are mounted on and electrically connected to substrate 18.

The MTM shown may have a MEMS die 132 that may use 0.8u technology and may have a function of data storage. The ADC/DAC die 128 may be a mixed signal die manufactured using 0.13u technology to perform analog signal processing, analog-to-digital conversion, and digital-to-analog conversions. The controller die 130 may be a digital die to perform digital signal processing. The power dies 138, 140, 142 may be analog dies manufactured using 0.35 micron technology to perform power supply and regulation to all dies on substrate 30. As a result there is an MEMS die 132, and there are a number of other dies of different process technology. The resultant MTM may be as small as 2.4mm X 16mm X 9mm and have a data storage capacity of 500 MB. Its three-layer structure includes all components necessary for a MEMS-based data storage system.

Whilst there has been described in the foregoing description preferred embodiments of the present invention, it will be understood by those skilled in the technology concerned that many variations or modifications in details of design or construction may be made without departing from the present invention.

The present invention extends to all features disclosed, either individually or in all possible permutations or combinations thereof.

Claims

The Claims:
1. A micro-electro-mechanical-system ("MEMS") die having a bottom part and a top part, the bottom part having a bottom length and a bottom width, the top part having a top length and a top width; at least one of the bottom length and the bottom width being of a greater dimension than the corresponding top length and top width to thereby form an upper surface on the bottom part on which upper surface interconnect pads are provided.
2. A MEMS die as claimed in claim 1, wherein the bottom length is greater than the top length.
3. A MEMS die as claimed in claim 1, wherein the bottom width is greater than the top width.
4. A MEMS die as claimed in claim 1, wherein the bottom length is greater than the top length, and the bottom width is greater than the top width.
5. A MEMS die as claimed in claim 1, wherein the interconnect pads are arranged in an array of at least one row and at least one column.
6. A MEMS die as claimed in claim 5, wherein there is a first plurality of rows.
7. A MEMS die as claimed in claim 5, wherein there is a second plurality of columns.
8. A MEMS die as claimed in claim 7, wherein the first plurality is different to the second plurality.
. A MEMS device as claimed in claim 8, wherein the number of rows and the number of columns varies along the upper surface.
10. A MEMS die as claimed in claim 1, wherein the upper surface extends completely around an outer periphery of the top part.
11. A MEMS die as claimed in claim 10, wherein the upper surface is of substantially constant width.
12. A MEMS die as claimed in claim 5, wherein the array is arranged as a series of sub-arrays, each sub-array having the required number of interconnect pads to enable a chip to be connected thereto.
13. A MEMS die as claimed in claim 12, wherein a plurality of chips are mounted on the sub-arrays on the upper surface, at least one of the plurality of chips being of a different process technology to the MEMS die, thereby forming a multi- technology module.
14. A MEMS die as claimed in claim 1, wherein at least one of the top part and the bottom part have a cavity, a micromachine being mounted in the cavity.
15. A MEMS die as claimed in claim 14, wherein both the top part and bottom part have cavities, the cavities being: vertically aligned, of the same shape, of the same size and having their openings facing each other.
16. A MEMS die as claimed in claim 14, wherein there is no peripheral conductor around the periphery of at least one of the cavities.
17. A MEMS die as claimed in claim 14, wherein the micromechanical machine is connected directly to at least one of the interconnect pads by at least one connector.
18. A MEMS die as claimed in claim 17, wherein there are a plurality of conductors each connecting the micromechanical machine directly to a different one of the interconnect pad.
19. A multi- technology module ("MTM") including at least one substrate, the at least one substrate having at least one hole therein, each of the at least one holes being sized and shaped to accommodate a top part of MEMS die, the MTM including a plurality of further chips at least one of which is of a different process technology to the MEMS die.
20. A MTM as claimed in claim 19, wherein there are at least two substrates with one being located above and substantially parallel to the other.
21. A MTM as claimed in claim 19, wherein the top part is of a height substantially equal to or greater than a thickness of the substrate, the holes being through holes.
22. A MTM module as claimed in claim 19, wherein the top part is of a height less than a thickness of the substrate, the holes being blind holes.
23. A substrate for a MTM, the substrate having at least one cavity therein for receiving therein a top part of a MEMS die according to claim 1, the cavity being of substantially the same size and shape as the top part.
24. A substrate as claimed in claim 23, wherein the top part is of a height substantially equal to or greater than a thickness of the substrate, the cavity being a through hole.
25. A substrate as claimed in claim 23, wherein the top part is of a height less than a thickness of the substrate, the cavity being a blind holes.
26. A MEMS die having a bottom part and a top part, at least one of the top part and the bottom part having a cavity, a micromachine being mounted in the cavity, there being at least one conductor connected directly to the micromechanical machine and to at least one interconnect pad.
27. A MEMS die as claimed in claim 26, wherein both the top part and the bottom part have a cavity, the cavities being: vertically aligned, of the same shape, of the same size, and having their opening facing each other.
28. A MEMS die as claimed in claim 26, wherein there are a plurality of conductors each connecting a different one of a plurality of interconnect pads to the micromachanical machine.
29. A MEMS die as claimed in claim 26 or claim 27, wherein the bottom part has a bottom length and a bottom width, the top part has a top length and a top width; at least one of the bottom length and the bottom width being of a greater dimension than the corresponding top length and top width to thereby form an upper surface on the bottom part on which upper surface a plurality of interconnect pads are provided.
30. A MEMS die as claimed in claim 29 wherein the bottom length is greater than the top length.
31. A MEMS die as claimed in claim 29, wherein the bottom width is greater than the top width.
32. A MEMS die as claimed in claim 29, wherein the bottom length is greater than the top length, and the bottom width is greater than the top width.
33. A MEMS die as claimed in claim 29, wherein the interconnect pads are arranged in an array of at least one row and at least one column.
34. A MEMS die as claimed in claim 33, wherein there is a first plurality of rows and a second plurality of columns the first plurality being different to the second plurality.
35. A MEMS device as claimed in claim 34, wherein the number of rows and the number of columns varies along the upper surface.
36. A MEMS die as claimed in claim 29, wherein the upper surface extends completely around an outer periphery of the top part.
37. A MEMS die as claimed in claim 36, wherein the upper surface is of substantially constant width.
38. A MEMS die as claimed in claim 33, wherein the array is arranged as a series of sub-arrays, each sub-array having the required number of interconnect pads to enable a chip to be connected thereto.
39. A MEMS die as claimed in claim 38, wherein a plurality of chips are mounted on the sub-arrays on the upper surface, at least one of the plurality of chips being of a different process technology to the MEMS die, thereby forming a multi- techno logy module.
40. A MEMS die having a plurality of interconnect pads arranged as a first plurality of rows and a second plurality of columns, the first plurality being different to the second plurality.
41. A substrate for a multi technology module, the substrate having a first plurality of arrays each of a plurality of interconnect pads and a second plurality of arrays of a plurality of vias, all arrays being formed in rows and columns.
42. A substrate as claimed in claim 41, wherein each array of pads is arranged in an array of a first plurality of rows and a second plurality of columns, the first plurality being different to the second plurality.
43. A substrate as claimed in claim 41, wherein each array of vias is arranged in an array of a first number of rows and a second number of columns, the first number being different to the second number.
PCT/US2002/006352 2002-02-28 2002-02-28 Micro-electro-mechanical systems packaging WO2003085732A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Publication number Priority date Publication date Assignee Title
US8011082B2 (en) 2005-11-09 2011-09-06 Koninklijke Philips Electronics N.V. Method of manufacturing a package carrier
US8351222B2 (en) 2005-11-09 2013-01-08 Koninklijke Philips Electronics N.V. Package carrier for enclosing at least one microelectronic device
US9173315B2 (en) 2005-11-09 2015-10-27 Koninklijke Philips N.V. Package carrier for a microelectronic element

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