CN114866186A

CN114866186A - LDPC decoding delay optimization method based on 5G

Info

Publication number: CN114866186A
Application number: CN202210358110.XA
Authority: CN
Inventors: 刘多强; 卜智勇; 薛顺瑞; 韩晓萌
Original assignee: Chengdu Zhongke Micro Information Technology Research Institute Co Ltd
Current assignee: Chengdu Zhongke Micro Information Technology Research Institute Co Ltd
Priority date: 2022-04-07
Filing date: 2022-04-07
Publication date: 2022-08-05
Anticipated expiration: 2042-04-07
Also published as: CN114866186B

Abstract

The invention provides a LDPC decoding delay optimization method based on 5G, which comprises the following steps: s1, ARM completes calculation of parameters needed by the PUSCH link processing module of each slot in advance through MAC scheduling information, and issues the parameters to the uplink baseband processing unit; s2, the uplink baseband processing unit receives the IQ frequency domain data, processes the IQ frequency domain data and outputs a plurality of CB code blocks; s3, determining whether to perform LDPC decoding delay optimization on the CB code block; s4, cutting and punching the code word check bits of the CB code block; s5, 2Z for CB code block start _c The soft LLR values are padded with "0 x 00"; s6, parallel LDPC decoding is carried out on the CB code block; s7, reading CB code blocks after parallel LDPC decoding and combining; s8, CRC is carried out on the CB code block after combination, andafter the CRC check is passed, a TB transmission block is synthesized and then sent to a 5G NR protocol MAC layer. The invention can improve the LDPC decoding performance, reduce the LDPC decoding time delay and improve the peak data rate of the system.

Description

LDPC decoding delay optimization method based on 5G

Technical Field

The invention relates to the technical field of wireless communication, in particular to an LDPC decoding delay optimization method based on 5G.

Background

With the rapid development of mobile communication technology, explosive mobile data traffic increases, massive device links, and new business requirements and application scenarios are emerging continuously, and 5G systems are coming to a vigorous development period.

The design of the 5G NR physical layer is the most core part of the whole 5G system design, and compared with LTE, ITU and 3GPP, the 5G is required to have higher and more comprehensive key performance indexes. The most challenging key technical indexes such as peak rate, user experience rate, and delay need to be achieved through the design of the physical layer.

The OFDM + MIMO technology is used as the basis of physical layer design, a flexible frame structure and a duplex mechanism are adopted, and meanwhile, compared with LTE, in the field of channel coding and coding, the 5G NR adopts a new combined technology of data channel LDPC coding and control channel Polar coding. The LDPC code has lower coding complexity and lower decoding time delay compared with the Turbo code, so that the signal transmission with large data volume can be better supported.

In order to support application scenarios such as eMBB, the 5G NR physical layer key technology adopts a novel channel coding technology, and provides powerful support for realizing key technical indexes of a 5G system by using a larger carrier bandwidth and a richer modulation mode.

In the 5G NR system, a data channel adopts a Quasi-Cyclic LDPC (QC-LDPC) code to carry out channel coding and decoding. For the base station, the LDPC decoding performance of the uplink PUSCH link directly determines the throughput rate and the error rate of the system.

In 5G NR, an LDPC codec needs to support a flexible code rate and a flexible code length, and flexible variation of the size of an information block is supported through a basic matrix and a shift factor. Because the 5G NR needs to support multiple code rates and has higher requirements on flexibility of code length, the LDPC code may be superior to other coding schemes in implementation complexity.

Although LDPC codes have the advantage of being highly parallelizable for decoding relative to Turbo codes, they also suffer from hardware resource overhead and low latency processing problems. Meanwhile, as NR supports different application scenarios, its flexibility increases the implementation complexity of LDPC codes.

The 5G physical layer baseband processing unit is used as a core component, and the performance of the 5G physical layer baseband processing unit is directly related to the performance of the whole 5G system. The base station design scheme mainly using X86, ARM, FPGA and ASIC as architectures has advantages and disadvantages in research and development cost, industrial ecology and performance. The base station product with the multi-core stacking technical architecture mainly based on the CPU or the ARM can be quickly put into the market, and the research and development cost is low. The base station product constructed by the FPGA/ASIC chip technology has long research and development period, higher cost, good performance and long life cycle.

In order to adapt to a novel LDPC channel coding and decoding technology, flexible uplink and downlink time slot ratio of a base station is supported, LDPC decoding processing needs to be further optimized, LDPC decoding performance is improved, physical layer processing time delay is reduced, and system peak data rate is improved.

When a 5G base station physical layer receiver based on the OFDM technology is implemented, the complexity of design and implementation of the receiver is increased sharply due to multi-antenna MIMO and multi-user access. Meanwhile, in order to support flexible uplink and downlink time slot matching, channel coding and decoding are core components of a baseband in the situation that the requirement on the traffic peak rate of the uplink is high, a large amount of hardware resources are consumed, and the realization of a programmable logic circuit is challenged. The hardware implementation represented by FPGA/ASIC is a necessary choice for designing 5G base stations in the industry. In order to support a multi-user multi-cell service scenario, the high throughput rate and the low delay of the LDPC decoding of the PUSCH link become the bottleneck of the technical scheme.

Especially for the LDPC decoding process of the baseband receiver channel, the performance and the time delay determine the performance of the whole baseband unit. The LDPC decoding time delay is reduced, the uplink data rate of the system is improved to several Gbit/s, and meanwhile, the low bit error rate BER is achieved, and great challenges are brought to the design realization of an LDPC decoder and the whole receiver link.

Therefore, while meeting the performance index of the 5G system, the application requirements are met with as low design complexity as possible, and the layout and optimization are required to be performed from a baseband processing architecture and a signal processing algorithm.

Disclosure of Invention

The invention aims to provide a LDPC decoding delay optimization method based on 5G, so as to improve the LDPC decoding performance, reduce the LDPC decoding delay and improve the peak data rate of a system.

The invention provides a LDPC decoding delay optimization method based on 5G, which comprises the following steps:

s1, ARM completes calculation of parameters needed by the PUSCH link processing module of each slot through MAC scheduling information in advance, and issues the obtained parameters needed by the PUSCH link processing module to the uplink baseband processing unit;

s2, the uplink baseband processing unit receives the IQ frequency domain data, performs the symbol level and bit level signal processing of the PUSCH link on the IQ frequency domain data by using the parameters required by the PUSCH link processing module, and then outputs a plurality of CB code blocks with the same code word length;

s3, determining whether to carry out LDPC decoding delay optimization on the CB code block, if so, entering the step S4; otherwise, go to step S5;

s4, cutting and punching the code word check bits of the CB code block;

s5, 2Z for CB code block start _c Soft LLR values fill "0 x 00";

s6, parallel LDPC decoding is carried out on the CB code block processed in the step S5;

s7, reading the CB code blocks after parallel LDPC decoding, and combining the information bits;

and S8, performing CRC check on the combined CB code block, combining a TB transmission block after the CRC check is passed, and sending the TB transmission block to a 5G NR protocol MAC layer.

Further, in step S2, the symbol-level and bit-level signal processing of the PUSCH link includes sequentially performing OFDM demodulation, channel estimation, MIMO equalization, demapping, soft demodulation at a symbol level, and descrambling and rate matching at a bit level.

Further, when performing bit-level rate de-matching, dividing the TB transmission block obtained after descrambling into a plurality of CB code blocks with the same code word length according to the parameters required by the PUSCH link processing module and the processing mode of rate de-matching, wherein the code word length of each CB code block is N; and when performing bit-level de-Rate matching, the MAC layer schedules to confirm whether to perform HARQ retransmission according to indexes such as Block Error Rate (Block Error Rate):

when the MAC layer schedules not to start HARQ retransmission, the rate de-matching module of the physical layer baseband processes according to the redundancy version RV being 0, and a CB code block cannot be reprocessed due to decoding error;

when the MAC layer starts HARQ retransmission, the de-rate matching module performs data combination by retransmitting a certain CB code block or increasing check bits according to the specific value of the redundancy version RV, so that the signal-to-noise ratio gain is improved, and the success rate of LDPC decoding is favorably improved.

Further, in step S3, it is determined whether to perform LDPC decoding delay optimization on the CB code block according to the modulation coding scheduling MCS, the code rate R, the redundancy version RV, the signal-to-noise ratio SNR, and the data traffic requirement.

Further, step S4 includes the following sub-steps:

s41, calculating the total code word length N of each CB code block before LDPC decoding _cb ：

N _cb ＝N+2Z _c (1)

Wherein, N is the code word length before phase shift of the CB code block;

s42, calculating the length of code word check bit of CB code block _paritybits ：

length _paritybits ＝N+2Z _c -K (2)

Wherein Z is _c K is the code word information bit length of the CB code block as a shifting factor;

s43, calculating the column number mb of the parity check matrix check bits:

s44, obtaining the relational expression of mb and N according to the formulas (1) to (3):

N＝K+Z _c (mb-2) (4)

s45, calculating the actual coding rate R:

s46, obtaining mb, R, K and Z from the formulas (3) and (5) _c The relationship of (1):

wherein, rounding is needed when mb is calculated, and is ensured to be not less than 4;

s47, under the MCS, for a redundancy version RV of 0, performing puncturing on the parity bits of the CB code block output by the de-rate matching process, removing the LLR soft values padded at the tail with "0 x 00", calculating mb according to formula (6), and substituting the calculated mb into formula (4), where the obtained codeword length N is the codeword length N' after the puncturing is completed and before the phase shift of the CB code block.

Further, in step S5, 2Z starting from the CB code block _c After the soft LLR value is filled with '0 x 00', the information is the sum check bit; therefore, the total length of the codeword sent to LDPC decoding is:

(1) if the code word check bits of the CB code block are not cut and punched in the step S4, the total length of the code words sent to the LDPC decoding is N _cb ＝N+2Z _c ；

(2) If the code word check bits of the CB code block are not cut and punched in the step S4, the total length of the code words sent to the LDPC decoding is N _cb ＝N′+2Z _c 。

Further, in step S5, the 2Z for starting the CB code block is implemented by designing a state machine FSM _c The soft LLR values fill in the "0 x 00" operation.

Further, the state machine FSM comprises four states:

ilde state: waiting for a CB code block input by a former-stage module and skipping the state when a latter-stage module can receive data;

the read state: reading the CB code block with the code word length of N or N', and starting 2Z of the CB code block _c Soft LLR values fill "0 x 00";

wait state: waiting for one CB code block to finish the filling operation, and then entering a gap state;

gap state: and (4) between the padding operations of two adjacent CB code blocks, performing time-delay processing time-limit isolation protection.

Further, 2Z starting for CB code block _c After each LLR soft value is filled with '0 x 00', data splicing is needed:

firstly, according to the length of code word of CB code block is N or N' and the shift factor Z _c Calculating the relative position of data splicing: for LLR soft values of floating point numbers, fixed point processing is needed during hardware processing; need to calculate 2Z _c Integer and remainder of/32, and (N) _cb -2Z _c ) A remainder of/32; then according to (N) _cb -2Z _c ) A remainder of/32, namely determining the end position of the last beat of valid data in 32 bytes in the transmission process of the data stream of each CB code block; then according to (N) _cb -2Z _c ) The remainder of/32, the specific positions of 2 effective clock cycles before and after data splicing are determined;

then, data splicing is carried out according to the relative position of the data splicing: when 2Z is _c When the/32 can not be divided evenly, the rest number of 0 LLR values are placed at the lower bits of 256 bits, and the data of the CB code block of the current clock is placed at the upper bits of 256 bits; and subsequent data splicing, namely placing the data of the CB code block of the current clock at the high order of 256 bits, and placing the data of the CB code block of the previous clock at the low order of 256 bits.

Further, step S6 includes the following sub-steps:

s61, initializing: according to the selected channel model, the soft LLR values after symbol soft demodulation after channel equalization are solved, and the soft LLR values L after soft demodulation are initialized for all variable nodes i _i (ii) a Then, the parity check equation h is satisfied for all _i,j Set M for 1 i, j _j,i ＝L _i Number of iterations iter _num 0; definition B _j Bit set, A, in the jth parity-check equation representing the parity-check matrix H _i A parity check equation representing the ith LLR value;

s62, check node CN updates: the message E is calculated for each check node CN using the formula _j,i The CN output of (2):

M _j,i ＝α _j,i β _j,i

α _j,i ＝sign(M _j,i )

β _j,i ＝|M _j,i |

s63, for i equal to 0,1, …, N-1, calculating the sum of LLRs using the following equation

S64, judging the ending criterion: for i ═ 0,1, …, N-1, let:

obtaining a decision based on the above equation

If it is not

Or the decoding iteration number reaches the set maximum iteration number iter _max Stopping decoding calculation; otherwise, go to S65;

s65, variable node VN update: for each variable node VN applying the following formula,computing a message M _j,i VN output of:

iter _num ＝iter _num +1

returning to S62, the iterative decoding calculation is continued.

In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:

1. the invention adopts an ARM + FPGA implementation framework, fully utilizes the flexibility of ARM soft solution design, and realizes the functions of command control, parameter calculation and the like; and the real-time processing of the streaming data signals is realized by utilizing the architectural advantages of FPGA parallel and stream processing. Compared with BBU architectures of X86 and ARM, the invention has great advantages in processing delay, peak rate, energy consumption and the like.

2. By adopting the 5G NR receiver multi-path parallel LDPC decoding acceleration implementation method which is convenient for hardware implementation, the low bit error rate performance requirement of LDPC decoding is met on one hand, and the requirement of an uplink two-stream or four-stream multi-cell multi-user application scene on the data rate reaching 1G bit/s is met on the other hand. Under the conditions of high-order modulation and high signal-to-noise ratio, the LDPC decoding can be realized by fewer iterations. And the plurality of LDPC decoders are processed in parallel, so that the decoding data throughput rate can be improved by several times.

3. Based on the normalized minimum sum LDPC decoding algorithm adopting the hierarchical scheduling, under the condition of high code rate and RV being 0, the code word check bit cutting and punching method of the CB code block is adopted, compared with the method for directly decoding the original code word length, the decoding time of a single LDPC decoder for the CB code block is greatly shortened, and the data rate can be improved by 3-4 times. The LDPC decoding processing can be completed in a slot (slot) scheduling period by selecting a proper normalization factor and the LDPC decoding iteration times, and the requirement of the 5G NR on the time delay less than 1ms is met.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and it is obvious for those skilled in the art that other related drawings can be obtained according to these drawings without inventive efforts.

FIG. 1 is a flowchart of an LDPC decoding delay optimization method based on 5G according to an embodiment of the present invention.

Fig. 2 is a flowchart of the uplink PUSCH processing of the NR base station in the embodiment of the present invention.

FIG. 3 is a block diagram of a base graph BG1 in an embodiment of the invention.

FIG. 4 is a block diagram of a base graph BG2 in an embodiment of the invention.

Fig. 5 is a schematic diagram of state transition of a state machine FSM according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a padding operation and data splicing in the embodiment of the present invention.

FIG. 7 is a block diagram of a multi-way parallel LDPC decoder in an embodiment of the present invention.

FIG. 8 is a block diagram of a parameter manager in an embodiment of the invention.

FIG. 9 is a schematic diagram of iterative decoding using a normalized min-sum LDPC decoding algorithm with hierarchical scheduling (first layer calculation) according to an embodiment of the present invention

Fig. 10 is a schematic diagram (second layer calculation) of iterative decoding using a hierarchical scheduling normalized min-sum LDPC decoding algorithm in the embodiment of the present invention.

Fig. 11 is a structural diagram of a parity check matrix H in the embodiment of the present invention.

FIG. 12 is a block diagram of LDPC decoding in an embodiment of the present invention

FIG. 13 is a block diagram of an output control unit of LDPC decoding according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

Examples

As shown in fig. 1, this embodiment proposes a delay optimization method for LDPC decoding based on 5G, which includes the following steps:

s1, the ARM completes calculation of parameters required by a PUSCH (Physical Uplink Shared Channel) link processing module of each slot in advance through MAC scheduling information, and issues the obtained parameters required by the PUSCH link processing module to a BBU (Baseband Unit);

parameters required by the PUSCH link processing module comprise DMRS symbol position, a modulation mode qm, a transmission block size TB size, a rate matching code word length E, a code rate R, a redundancy version RV, an LDPC code word length N and a shift factor Zc; these parameters will be used for specific digital signal processing by the functional units of the PUSCH link.

S2, the uplink baseband processing unit (through a forward CPRI (common public Radio interface)) receives the IQ frequency domain data, and uses the parameters required by the PUSCH link processing module to perform the symbol level and bit level signal processing of the PUSCH link on the IQ frequency domain data, and then outputs a plurality of CB code blocks with the same code word length;

as shown in fig. 2, the symbol-level and bit-level signal processing of the PUSCH link includes OFDM demodulation, channel estimation, MIMO equalization, demapping, and soft demodulation at the symbol level, and descrambling and rate matching at the bit level, which are sequentially performed.

Wherein, when performing bit-level de-rate matching, the method determines the transmission block size TB size according to parameters (such as Modulation Coding Scheme (MCS), transmission block size TB size) required by the PUSCH link processing moduleCode block number C, shift factor Z _c And Redundancy Version (RV), etc.), dividing the TB transmission block obtained after descrambling into a plurality of CB code blocks with the same code word length, wherein the code word length of each CB code block is N. And when performing bit-level de-Rate matching, the MAC layer schedules to confirm whether to perform HARQ retransmission according to indexes such as Block Error Rate (Block Error Rate):

when the MAC layer schedules not to start HARQ retransmission, the rate de-matching module of the physical layer baseband processes according to the redundancy version RV being 0, and a CB code block cannot be reprocessed due to decoding error; when the MAC layer starts HARQ retransmission, the de-rate matching module performs data combination by retransmitting a certain CB code block or increasing check bits according to the specific value of the redundancy version RV, so that the signal-to-noise ratio gain is improved, and the success rate of LDPC decoding is favorably improved.

It should be noted that, while the performance of HARQ retransmission is improved, the delay of baseband digital signal processing is also increased, which may cause service traffic to decrease, and therefore, whether to start HARQ retransmission may be selected according to needs.

and determining whether to perform LDPC decoding delay optimization on the CB code block according to the modulation coding scheduling MCS, the code rate R, the redundancy version RV, the signal-to-noise ratio SNR, the data flow requirement and the like.

For example, when LDPC decoding is performed based on a CB code block, if conditions such as redundancy version RV of 0, 256QAM (e.g., MCS >16) in the modulation scheme, SNR of 20dB or more, and a requirement for uplink traffic to reach data traffic of Gbit/S are satisfied, and LDPC decoding delay optimization can be performed on the CB code block, step S4 is performed, so as to greatly shorten LDPC decoding processing time, and maintain good decoding performance and system high throughput.

S4, cutting and punching the code word check bits of the CB code block; specifically, the method comprises the following steps:

s41, calculating each CB code block and performing LDPC decodingTotal length N of preceding codeword _cb ：

N _cb ＝N+2Z _c (1)

Wherein, N is the code word length before phase shift of the CB code block;

length _paritybits ＝N+2Z _c -K (2)

s43, calculating the column number mb of the parity check matrix check bits:

N＝K+Z _c (mb-2) (4)

s45, calculating the actual coding rate R:

wherein, rounding is needed when calculating mb, and is guaranteed to be not less than 4. In the current 5G NR specification, for the base graph BG1, K-22Z _c The maximum value of mb is 46; for the base graph BG2, K is 10Z _c The maximum value of mb is 42. For the structures of base map BG1 and base map BG2, as shown in fig. 3 and 4, kb represents the number of columns of system bits, and for base map BG1, kb takes the value of 22; for the base graph BG2, kb may take the values 6, 8, 9, 10. mb denotes the column number of check bits, for base graph BG1,mb ranges from 4 to 46; for the base graph BG2, mb ranges from 4 to 44. nb is the total number of columns of the parity check matrix H. The core matrix has the characteristic of high row weight and can ensure the LDPC decoding performance. The line orthogonality is beneficial to designing a hardware implementation structure of line parallel or block parallel, so that the decoding speed can be improved. For the base graph BG2, the non-row orthogonal design has better performance for the matrix with medium and low code rate, and the application scenario with high reliability can be supported by matrix expansion.

S47, under the MCS, for a redundancy version RV of 0, performing puncturing on the parity bits of the CB code block output by the de-rate matching process, removing the LLR soft values padded at the tail with "0 x 00", calculating mb according to formula (6), and substituting the calculated mb into formula (4), where the obtained codeword length N is the codeword length N' after the puncturing is completed and before the phase shift of the CB code block. For example: the transmission block TB in a slot is represented by a base pattern BG1, K-8448, Z _c 384, R0.8148, mb 5 can be calculated from equation (6). At this time, according to the formula (4), the codeword length N' after the phase shift of the CN code block and the completion of the puncturing is calculated to be 8448+384 × (5-2) ═ 9600. Therefore, the LLR soft value of the punched check bits is cut, namely the length of the code word check bits of the CB code block is reduced, effective code word information bits and necessary code word check bits are reserved, the LDPC decoding performance is hardly influenced, but the length of the code words is greatly shortened, so that the code rate is indirectly improved, the H size of a parity check matrix is reduced, the operation amount of iterative decoding is reduced, and the LDPC decoding time can be greatly shortened.

S5, 2Z for CB code block start _c The soft LLR values are padded with "0 x 00";

2Z at the beginning of a code block to CB _c After the soft LLR value is filled with '0 x 00', the information is the sum check bit; therefore, the total length of the codeword sent to LDPC decoding is:

(2) If the code word check bit of the CB code block is not cut and punched in the step S4, the code word check bit is sent to the LDPC decodingThe total code length of the code is N _cb ＝N′+2Z _c 。

In the embodiment, 2Z for starting CB code blocks is realized by designing a state machine FSM _c The soft LLR values fill in the "0 x 00" operation. As shown in fig. 5, the state machine FSM comprises four states:

the read state: reading the CB code block with the code word length of N or N', and starting 2Z of the CB code block _c The soft LLR values are padded with "0 x 00";

wait state: waiting for one CB code block to finish the padding operation, and then entering a gap state;

gap state: and between the filling operations of two adjacent CB code blocks, a delay processing time limit is used for isolation protection to prevent the logic time sequence from being tensed.

firstly, according to the length of code word of CB code block is N or N' and the shift factor Z _c Calculating the relative position of data splicing: for the soft LLR values of floating-point numbers, fixed-point processing is required during hardware processing. For example, the bit width of the LLR soft values for each CB code block may be defined as 8 bits, fixed-point format 8Q2, expressed as a total bit width of 8 bits, with the least significant bits being the fractional bits of 2 bits and the most significant bits being the sign bits. In order to improve the LDPC decoding throughput rate, the bit width of the LDPC decoder interface data is designed according to 256 bits. To facilitate data splicing, 2Z needs to be calculated _c Integer and remainder of/32, and (N) _cb -2Z _c ) A remainder of/32; then according to (N) _cb -2Z _c ) The remainder of/32, namely determining the end position of the last beat of valid data in 32 bytes in the transmission process of the data stream of each CB code block; then according to (N) _cb -2Z _c ) The remainder of/32 determines the specific location of the 2 valid clock cycles before and after the data splice.

Then, data splicing is carried out according to the relative position of the data splicing: as shown in FIG. 6, when 2Z _c /32, when the clock cannot be divided evenly, the rest number of 0 LLR values are placed at the low order of 256 bits, and the data of the CB code block of the current clock is placed at the high order of 256 bits; and subsequent data splicing, namely placing the data of the CB code block of the current clock into the upper bits of 256 bits, and placing the data of the CB code block of the previous clock into the lower bits of 256 bits.

as shown in fig. 7, in this embodiment, the LDPC decoder performs iterative decoding by using a normalized minimum sum LDPC decoding algorithm of hierarchical scheduling, transmits the CB code blocks processed in step S5 to the plurality of parallel LDPC decoders in a time-sharing manner for LDPC decoding, and allows the decoding process to end in advance when the decoding parity check passes. The parameter manager in the figure converts TB-level parameters into CB-level parameters, and distributes the CB-level parameters to the filling 2Z _c A processing unit and a multiplexer. Filling 2Z _c Processing unit completes each CB code block start 2Z _c The soft LLR values are padded with "0 x 00" and concatenated with the valid LLR codeword information. And the multiplexer module sequentially polls the CB code blocks according to the currently processed CB code blocks and sends the CB code blocks into 4 LDPC decoders for LDPC decoding processing. The LDPC decoder performs LDPC decoding according to the CB code blocks and outputs an LDPC decoding result of each CB code block. And the output control unit performs polling output on the LDPC decoding results of the 4 LDPC decoders according to the CB code block sequence and transmits the results to a subsequent CRC check module.

Wherein, to facilitate the hardware logic processing, the check bit control factor mb and the shift factor Z issued to the higher layer (such as protocol stack in 5G communication, L2/L3) _c Parameters such as the base graph type BG1 or BG2 are buffered and managed by a parameter manager (FIFO memory), which performs LDPC decoding parameter configuration based on CB code blocks, as shown in fig. 8.

For convenience of multi-user access and management, a TB transport block scheduled in each slot and a CB code block in the TB transport block are specified, and corresponding ID numbers (such as an ID number slot _ ID of the slot, an ID number TB _ ID of the TB transport block, and an ID number CB _ ID of the CB code block) are assigned, so that the hardware circuit performs LDPC decoding processing according to the CB code block.

The schematic diagram of the normalized minimum sum LDPC decoding algorithm adopting the hierarchical scheduling is shown in fig. 9 and 10, in the iterative decoding process, check nodes are divided into a plurality of groups, a group of check node information in the check matrix is updated in each iteration, all variable nodes adjacent to the group of check nodes are updated, the next group of check node information and the variable node information adjacent to the group of check nodes are updated, and so on until the last group of update is completed. And after the iteration of the current round is finished, judging whether to carry out the next iteration according to the test equation and the iteration time setting. Meanwhile, the variable node information updated in the iteration of the current round can be used for updating the check node information of the next iteration, so that the convergence speed is increased, the iteration times can be saved, and the throughput can be improved. When the check passes or the maximum iteration times are reached, the LDPC decoding process can be ended. The consumption of hardware resources is determined by the number of parity check equation units at the same time, all check nodes participate in operation at the same time to improve the throughput of the fully parallel LDPC decoding, although the throughput can be improved, the consumption of the hardware resources is huge, and the hardware resources are wasted under the condition that the code length and the code rate are variable. Therefore, the normalized minimum sum LDPC decoding algorithm adopting the hierarchical scheduling can enable the decoding throughput rate and the hardware resource consumption to be relatively balanced, and the method is practicable in practice.

The main calculation formula of the normalized min-sum LDPC decoding algorithm is as follows:

the metric of the binary variable is represented by the following log-likelihood ratio (LLR):

where l (x) provides a hard decision for x, and modulo l (x) determines the reliability of the hard decision.

Converting the log-likelihood ratio LLR to probability:

the extrinsic information from check node j to variable node i is represented as log-likelihood ratio LLR:

defining a parity check matrix H for LDPC decoding, using B _j The symbol represents the set of bits (the set of positions of 1 in each row) in the parity check equation of the parity check matrix H, denoted by a _i The parity check equation for the ith bit (the set of positions of 1 in each column) is represented. The structure of the parity check matrix H is as shown in fig. 11, and the LDPC parity check matrix H is composed of A, B, C, D, E five sub-matrices. The sub-matrix A corresponds to information bits to be coded of a system; the submatrix B is a square matrix having a dual diagonal structure, and corresponds to parity bits. The weight of the first or last column of the sub-matrix B is equal to 1, the last row of the sub-matrix B has a non-zero value and a weight equal to 1, and if there is a column with a weight of 1, the remaining columns comprise a square matrix such that the weight of the first column is 3. The columns following the weight 3 column have a diagonal structure (i.e., major diagonal and off-diagonal elements). If there is no column with weight 1, the sub-matrix B consists of only one square matrix, so that the weight of the first column is 3. The sub-matrix C is an all-zero matrix, the sub-matrix D corresponds to a single parity check row, and the sub-matrix E is an identity matrix of a Base Graph (BG) corresponding to check bits with a low spreading code rate.

Therefore, the following equations (8) to (10) can be obtained:

wherein,

consider M _j,i Sign bit and size of (c):

M _j,i ＝α _j,i β _j,i (12-a)

α _j,i ＝sign(M _j,i ) (12-b)

β _j,i ＝|M _j,i | (12-c)

from equations (11) and (12), we obtain:

wherein,

is defined as:

for external information E _j,i From

Formally, considering equation (13), the maximum in the summation corresponds to the minimum β _j,i . Thus, the following relation can be obtained:

since the approximate value of equation (15) is large and affects the LDPC decoding convergence rate, the equation is corrected:

wherein, the lambda is a normalized scaling factor, and the value range of the lambda is more than 0 and less than or equal to 1. In this embodiment, the normalized scaling factor λ is dynamically configured based on CB code blocks, that is, one normalized scaling factor λ is configured when LDPC decoding is performed on each CB code block. In particular, where LDPC coding duration allows, a suitable single normalized scaling factor λ may be selected to approximately scale LLR values for all CB codeblocks. In a hardware implementation, it is not practical to update the normalized scaling factor λ in real-time, especially for the channel decoding process of the 5G base station uplink PUSCH. The value range of the configured normalized scaling factor λ is 0 < λ ≦ 1, and in order to improve the LDPC decoding performance, the value of the normalized scaling factor λ is preferably limited to 0.6 to 0.9, and generally, the default value is set to λ ≦ 0.75. In practical engineering implementation, the most appropriate normalization scaling factor λ needs to be selected according to the system simulation situation.

Thus, equation (13) can be written as:

since each variable node can be connected to the LLR of the input channel and the LLR of each check node. The total LLR of the ith bit is the sum of the two LLRs

Wherein L is _i Representing soft-demodulated LLR soft values.

For White Gaussian Noise (AWGN) model in communication system, i-th sample y is received _i ＝x _i h _i +n _i Wherein n is _i Conforming to an independent normal distribution N (0, sigma) ² )，

N ₀ Is the noise density.

Therefore, the channel transition probability is easily obtained:

where x ∈ {0,1}, then:

final hard decision of LDPC decoding

Given the symbols, the decision is based on checking whether the parity check equation is satisfied

And whether the set maximum decoding iteration number is reached. If not, then M is updated _j,i ：

Therefore, the process of performing parallel LDPC decoding on the CB code blocks processed in step S5 in step S6 includes the following steps:

M _j,i ＝α _j,i β _j,i

α _j,i ＝sign(M _j,i )

β _j,i ＝|M _j,i |

s63, for i 0,1, …, N-1, the following equation is applied to calculate the sum of LLRs

S64, judging the ending criterion: for i ═ 0,1, …, N-1, let:

obtaining a decision based on the above equation

If it is not

Or the decoding iteration number reaches the set maximum iteration number iter _max Stopping decoding calculation; otherwise, the process proceeds to S65.

S65, variable node VN update: for each variable node VN, the message M is calculated using the formula _j,i VN output of:

iter _num ＝iter _num +1

returning to S62, the iterative decoding calculation is continued.

In the LDPC decoding process, check nodes are divided into a plurality of groups, a group of check nodes CN in a parity check matrix H is updated firstly in each iteration decoding, and then all variable nodes VN adjacent to the group of check nodes are updated. And then updating the CN information of the next group and the VN information adjacent to the group until the CN information and the VN information of the last group are updated. The updated VN information is applied to the updating process of the CN information after the current iteration, so that the iteration convergence speed is accelerated, the iteration times can be saved, the decoding delay is reduced, and the decoding throughput rate is improved.

The throughput rate calculation formula of the LDPC decoder is as follows:

wherein N is _cb The total code word length of each CB code block before LDPC decoding is carried out; cycle is a single decoding iteration time period; num _iter The actual iteration number is; delta _t Controlling the processing time for the parameter; f. of _clk Clock frequency for the LDPC decoder; r is the code rate.

When decoding LDPC, the main parameters are: code word total length N of each CB code block before LDPC decoding _cb Base graph BG1 or BG2 for indexing a shifting factor Z _c Parameters a and j of, the number of columns of parity check matrix check bits mb, the maximum number of iterations iter _max And the like.

Wherein Z is _c ＝a×2 ^j ，a＝{2,3,5,7,9,11,13,15}，j＝{0,1,2,3,4,5,6,7}。

The structure of each parallel LDPC decoder is shown in fig. 12, and the LDPC decoder includes an input control unit, a check node unit, LLR memory segments, a routing network module, a shift network module, and an output control unit. The input control unit realizes the configuration of LDPC decoding parameters and the flow control of data, and transmits a data frame by taking the code word length of one CB code block as a processing unit. The LLR memory slices are used for storing input channel LLR values and LLR values after iterative updating, and the number of the memory slices is equal to the column number of the core matrix of the parity check matrix H plus 1. The number of input pins of the check node unit is equal to the maximum row weight of the parity check matrix. Routing network moduleThe block inputs LLR data subjected to cyclic shift in the LLR memory fragments to pin ports of check node units, the check node units realize the function of hierarchical scheduling decoding by reading data on different groups of pin ports, and the final decoding output is realized by iterative computation. To facilitate LDPC decoding iterative check, the shift network module may provide the PCM list and the shift factor Z via the 5G NR specification _c A value index table, which pre-calculates all parity check matrixes H containing only 0 and 1, according to the base graph BG1 or BG2 and the shift factor Z _c The parity check matrix H is indexed, thereby completing the parity check. The shift network module adopts a Banyan network structure so as to support different shift factors Z _c And hardware parallel processing. The check node memory is used for caching the check node value after each iteration and updating the variable node information in the next iteration. The output control unit completes data bit width matching and clock domain crossing processing, and sends out related decoding states, so that internal execution conditions of the decoder can be monitored conveniently.

And S7, reading the CB code blocks after parallel LDPC decoding, combining information bits, and realizing by an output control unit, wherein the structure of the output control unit is shown in FIG. 13, and the module mainly completes the design ideas of 4 LDPC decoders for polling output data streams according to the CB code block requirements, and cascading and outputting the information bits output by the CB code block decoding, and is also a parallel-serial conversion and time division multiplexing design idea essentially. When the output control unit outputs, a FIFO memory is used for buffering for functional module isolation. In fig. 13, the input control unit inputs the original frame header information, then updates the frame information such as the output packet length, and performs buffering, waits for the output of the LDPC decoding result of the CB code block, and finally performs the output of the cascade combination. The reading controller is used for controlling the data and state output reading process of the 4 LDPC decoders, realizing the data alignment of the TB block output, and preventing the data among different TB transmission blocks from being crossed and disordered so as to influence the transmission of data packets. The CB code block data counter and the state counter are modulo 4 counters, and polling reading operation of 4 LDPC decoders is convenient to realize. The output selector is used for realizing information bit combination of the LDPC decoding results of the CB code blocks through framing, namely outputting a frame header firstly and then outputting an information bit set of the LDPC decoding results of all the CB code blocks of one TB transmission block. And finally, the data frame is put into a buffer unit, and a CRC (cyclic redundancy check) module at the later stage reads the combined information bit set to perform CRC. In order to prevent the overflow of the buffer unit, the full state of the buffer unit is fed back to the read controller, so that the flow control is carried out. In addition, in order to facilitate system debugging and diagnosis, a monitor is designed for monitoring the state of the output control unit in real time and capturing key information for online analysis and diagnosis.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A LDPC decoding delay optimization method based on 5G is characterized by comprising the following steps:

s4, cutting and punching the code word check bits of the CB code block;

s5, 2Z for CB code block start _c LLR soft value filling'0x00”；

2. The delay optimization method for LDPC decoding based on 5G according to claim 1, wherein in step S2, the symbol-level and bit-level signal processing of the PUSCH link comprises sequentially performing OFDM demodulation, channel estimation, MIMO equalization, demapping and soft demodulation at symbol level, and descrambling and rate matching at bit level.

3. The 5G-based LDPC decoding delay optimization method according to claim 2, wherein when performing bit-level de-rate matching, according to parameters required by the PUSCH link processing module, the TB transmission block obtained after descrambling is divided into a plurality of CB code blocks with equal code word length according to a processing mode of de-rate matching, and the code word length of each CB code block is N; and when performing bit-level de-Rate matching, the MAC layer schedules to confirm whether to perform HARQ retransmission according to indexes such as Block Error Rate (Block Error Rate):

4. The 5G-based LDPC decoding delay optimization method of claim 1, wherein in step S3, whether to perform LDPC decoding delay optimization on the CB code block is determined according to a modulation coding scheduling MCS, a code rate R, a redundancy version RV, a signal-to-noise ratio SNR and a data traffic requirement.

5. The delay optimization method of LDPC decoding based on 5G of claim 1, wherein the step S4 comprises the following sub-steps:

N _cb ＝N+2Z _c (1)

Wherein, N is the code word length before phase shift of the CB code block;

length _paritybits ＝N+2Z _c -K (2)

s43, calculating the column number mb of the parity check matrix check bits:

N＝K+Z _c (mb-2) (4)

s45, calculating the actual coding rate R:

6. The delay optimization method for LDPC decoding based on 5G according to claim 5, wherein in step S5, the decoding is started at 2Z for CB code blocks _c After the soft LLR value is filled with '0 x 00', the information is the sum check bit; therefore, the total length of the codeword sent to LDPC decoding is:

7. The delay optimization method for LDPC decoding based on 5G according to claim 6, wherein the step S5 is implemented by designing a state machine FSM to implement 2Z for starting CB code blocks _c The soft LLR values fill in the "0 x 00" operation.

8. The 5G-based LDPC decoding delay optimization method of claim 7, wherein the state machine FSM comprises four states:

9. The 5G-based LDPC decoding delay optimization method of claim 8, wherein 2Z for CB code block start _c After each LLR soft value is filled with '0 x 00', data splicing is needed:

firstly, according to the length of code word of CB code block is N or N' and the shift factor Z _c Calculating the relative position of data splicing: for LLR soft values of floating point numbers, fixed point processing is needed during hardware processing; need to calculate 2Z _c Integer and remainder of/32, and (N) _cb -2Z _c ) A remainder of/32; then according to (N) _cb -2Z _c ) The remainder of/32, namely determining the end position of the last beat of valid data in 32 bytes in the transmission process of the data stream of each CB code block; then according to (N) _cb -2Z _c ) The remainder of/32, the specific positions of 2 effective clock cycles before and after data splicing are determined;

10. The delay optimization method for LDPC decoding based on 5G according to claim 1, wherein the step S6 comprises the following sub-steps:

s61, initializing: according to the selected channel model, the soft LLR values after symbol soft demodulation after channel equalization are solved, and the soft LLR values L after soft demodulation are initialized for all variable nodes i _i (ii) a Then, the parity check equation h is satisfied for all _i,j Set M for 1 i, j _j,i ＝L _i Number of iterations iter _num 0; definition B _j J-th odd representing parity check matrix HSet of bits in even parity-check equation, A _i A parity check equation representing the ith LLR value;

M _j,i ＝α _j,i β _j,i

α _j,i ＝sign(M _j,i )

β _j,i ＝|M _j,i |

S64, judging the ending criterion: for i ═ 0,1, …, N-1, let:

obtaining a decision based on the above equation

If it is not

iter _num ＝iter _num +1

returning to S62, the iterative decoding calculation is continued.