JP2021044826A - Methods and systems for encoding and decoding for ldpc codes - Google Patents

Abstract

To provide methods and devices for encoding source words and decoding codewords with LDPC matrices.SOLUTION: The methods and devices use an LDPC matrix Hn of a lifting factor Z. The LDPC matrix Hn comprises a plurality of submatrices, each submatrix having a size of Z×Z, and at least one submatrix has m1 diagonal elements of "1", where m1 is an integer greater than or equal to 2.SELECTED DRAWING: Figure 8

Description

The application relates to mobile air interface technology, and in particular to methods and systems for encoding and decoding binary low density parity check (LDPC) codes.

The LDPC encoder in the transmitter is used to encode the source word to generate the codeword. The LDPC decoder in the receiver is used to decode the received codeword. The IEEE 802.11ad standard employs various rates of LDPC codes.

IEEE 802.11REVmc proposes several rates of 7/8 LDPC codes. However, the proposed LDPC code is not optimized for error rate performance or has a different codeword length than the LDPC code in the IEEE 802.11ad standard. Differences in codeword length can affect the implementation of blocking and deblocking processes at transmitters and receivers, respectively.

を受け取るステップと、1×Nの符号語ベクトル

を生成するステップとを含み、GはK×Nの生成器行列であり、Gはパリティ検査行列H_nから導出され、H_nはリフティング係数Zを有し、H_nは複数のサブ行列を含み、各サブ行列のサイズはZ×Zであり、少なくとも1つのサブ行列はm₁の「1」の対角要素を有し、m₁は2以上の整数である。 According to one embodiment of the present disclosure, a method for encoding a source word is provided. The method is a 1 × K source word line vector

And the 1 × N codeword vector

G is a K × N generator matrix, G is derived from the _{parity check matrix H n , H n} has a lifting coefficient Z, and H _n contains multiple sub-matrixes. , the size of each sub-matrix is Z × Z, at least one sub-matrix having diagonal elements of "1" of the m _1, m ₁ is an integer of 2 or more.

であり、

はバイナリ行列であり、

は位数n−kの識別行列であり、「T」は行列転置を表し、パリティ検査行列は

である。 According to one embodiment of the present disclosure.

And

Is a binary matrix,

Is an order n−k identification matrix, “T” represents matrix transpose, and the parity check matrix is

Is.

According to one embodiment of the present disclosure, H _n is to divide the parity check matrix H of the first MxN into square sub-matrix using the lifting coefficient Z, where M = I × Z and N. = J × Z, I and J are integers, I is greater than 2, J is greater than 0, and the split parity check matrix H is a submatrix of (M / Z) rows × (N / Z) columns. _{And that m 1} row is selected from the M / Z row sub-matrix _{of the split parity check matrix H, and m 1} row of the sub-matrix of the first split parity check matrix H is of the matrix H _n . Produced by adding as a row in a submatrix, where m ₁ is an integer greater than or equal to 2. In one embodiment, M− (m ₁ × Z) + Z = N−K. In one embodiment, Z = 42 and N = 672. In another embodiment, K = 588 and the new matrix H _n comprises 84 rows × 672 columns.

According to one embodiment of the present disclosure, the remaining m ₂ rows of the submatrix of the divided parity check matrix H are added as the second new row of the submatrix of the _{new matrix H n , where m 2} is an integer greater than or equal to 1. Is. In one embodiment, m ₂ = <((M / Z) −m ₁ ).

According to one embodiment of the present disclosure, the method takes _{m 2 rows from the remaining (M / Z−m 1} ) rows of the submatrix of the first split parity check matrix H to the second of the new matrix H _n . _{The step of adding as a submatrix row and m 3 rows from the remaining (M / Z−m 1} −m ₂ ) rows of the submatrix of the first split parity check matrix H are added to the third sub of the new matrix H _{n. The step of adding as a matrix row and m 4 rows from the remaining (M / Z − m 1 − m 2} −m ₃ ) rows of the submatrix of the first split parity check matrix H are added to the fourth of the new matrix H _n . Including the step to add as a submatrix row of, N = 1344, Z = 42, m ₁ , m ₂ , m ₃ , and m ₄ are integers, m ₁ + m ₂ + m ₃ + m ₄ = <M / Z, m ₁ > 1, m ₂ > = 1, m ₃ > = 1, and m ₄ > = 1.

According to one embodiment of the present disclosure, the first parity check matrix H is an LDPC matrix with a coding rate of 13/16 specified in 802.11ad, and the first matrix H has 126 rows × 672 columns. Yes, Z = 42, and the second matrix H _n is generated with the parameters m ₁ = 2 and Z = 42.

According to one embodiment of the present disclosure, the first parity check matrix H is a low density parity check (LDPC) matrix with a coding rate of 13/16, and the first matrix H is 252 rows × 1344 columns. , Z = 84, and the second matrix H _n is generated with the parameters m ₁ = 2 and Z = 84.

According to one embodiment of the present disclosure, the second matrix H _n is:

According to one embodiment of the present disclosure, the second matrix H _n is:

According to one embodiment of the present disclosure, the first parity check matrix H is an LDPC matrix having a coding rate of 3/4 specified in 802.11ad, and the first matrix H has 168 rows × 672 columns. Yes, Z = 42, and the second matrix H _n is generated with the parameters m ₁ = 2, m ₂ = 2, Z = 42.

According to one embodiment of the present disclosure, the first parity check matrix H is an LDPC matrix with a coding rate of 3/4, the first matrix H is 336 rows × 1344 columns, and Z = 84. , The second matrix H _n is generated with the parameters m ₁ = 2, m ₂ = 2, Z = 84.

According to one embodiment of the present disclosure, the second matrix H _n is:

According to one embodiment of the present disclosure, the second matrix Hn is:

According to one embodiment of the present disclosure, H _n = [H ₁ H ₂ ], H ₁ is a (n−k) × (k) matrix having a lifting coefficient Z, and H 1 has a plurality of sub-matrixes. Including, the size of each submatrix is Z × Z, and H ₂ is a full-rank (n−k) × (n−k) matrix whose columns have a weight of 2 except for the last column.

According to one embodiment of the present disclosure, H1 is:

である。 H2 is

Is.

を復元するために1×Nのベクトル

を生成するステップとを含み、

であり、H_nは複数のサブ行列を含み、H_nはリフティング係数Zを有し、各サブ行列のサイズはZ×Zであり、少なくとも1つのサブ行列はm₁の対角要素を有し、m₁は2以上の整数である。 According to one embodiment of the present disclosure, a method for decoding a demodulated signal is provided. The method consists of a step of receiving a demodulated signal having a row vector S, a step of decoding a 1 × N row vector S using the _{parity check matrix H n used in the coding process, and a 1 × K source word.} Row vector

Vector of 1 × N to restore

Including steps to generate

H _n contains multiple sub-matrix, H _n has a lifting coefficient Z, the size of each sub-matrix is Z × Z, and at least one sub-matrix has diagonal elements of _{m 1.} , M ₁ is an integer greater than or equal to 2.

According to one embodiment of the present disclosure, a system for performing the above method is provided.

According to one embodiment of the present disclosure, a system for carrying out the above method is provided. In one embodiment, the system is a station. In one embodiment, the system is an access point. In one embodiment, the system is a wireless transmitter / receiver unit.

Here, by way of example, reference is made to the accompanying drawings showing exemplary embodiments of the present application.

It is a block diagram which shows the exemplary communication system by one Embodiment of this disclosure. It is a block diagram which shows the exemplary processing system by one Embodiment of this disclosure. It is a block diagram which shows the exemplary implementation of the transmitter of this disclosure. It is a block diagram which shows an exemplary step in the method of processing the information bit stream of this disclosure. FIG. 3 is a block diagram illustrating an exemplary implementation of the LDCP encoder of the present disclosure. It is a figure which shows the exemplary single carrier frame format of 802.11ad. It is a figure which shows the exemplary structure of the data block of the 802.11ad single carrier frame format. It is an LDPC parity check matrix specified by IEEE802.11ad with a codeword length of 672. It is an LDPC parity check matrix specified by IEEE802.11ad with a codeword length of 672. It is an LDPC parity check matrix specified by IEEE802.11ad with a codeword length of 672. It is an LDPC parity check matrix specified by IEEE802.11ad with a codeword length of 672. The cyclic permutation submatrix obtained from the 4 × 4 identity matrix is shown. It is an LPDC parity check matrix proposed by IEEE802.11ay with a codeword length of 1344. It is an LPDC parity check matrix proposed by IEEE802.11ay with a codeword length of 1344. It is an LPDC parity check matrix proposed by IEEE802.11ay with a codeword length of 1344. It is an LPDC parity check matrix proposed by IEEE802.11ay with a codeword length of 1344. It is a figure which shows the single carrier blocking using the different modulation techniques in 802.11ad and 802.11REVmc. It is a figure which shows the single carrier blocking using the different modulation techniques in 802.11ad and 802.11REVmc. It is a figure which shows the single carrier blocking using the different modulation techniques in 802.11ad and 802.11REVmc. FIG. 6 is a block diagram illustrating exemplary steps in the process of generating a _{parity check matrix H n} for LDPC coding according to an embodiment of the present disclosure. It is a figure which shows _{the LDPC parity check matrix H n} of an exemplary coding rate 7/8 based on LDPC of rate 13/16 in 802.11 by this disclosure. It is a figure which shows _{the LDPC parity check matrix H n} of an exemplary coding rate 7/8 based on LDPC of rate 13/16 in 802.11 by this disclosure. It is a figure which shows _{the LDPC parity check matrix H n} of an exemplary coding rate 7/8 based on LDPC of rate 3/4 in 802.11 by this disclosure. It is a figure which shows _{the LDPC parity check matrix H n} of an exemplary coding rate 7/8 based on LDPC of rate 3/4 in 802.11 by this disclosure. It is a figure which shows the exemplary sub-matrix of the LDPC parity check matrix H _{n by this disclosure.} It is a figure which shows the exemplary LDPC parity check matrix H _{n generated by one Embodiment of this disclosure.} It is a figure which shows the performance of various LDPC codes using different modulation methods. It is a figure which shows the performance of various LDPC codes using different modulation methods. It is a figure which shows the performance of various LDPC codes using different modulation methods. It is a figure which shows the performance of various LDPC codes using different modulation methods. It is a figure which shows the performance of various LDPC codes using different modulation methods. It is a figure which shows the performance of various LDPC codes using different modulation methods. It is a block diagram which shows the exemplary implementation of the receiver of this disclosure. FIG. 6 is a block diagram illustrating exemplary steps in the process of decoding a received signal according to an embodiment of the present disclosure. FIG. 6 is a block diagram illustrating an exemplary implementation of the LDCP decoder of the present disclosure. It is a figure which shows an exemplary LDPC decoding process.

The same reference numbers are used throughout the drawing to indicate similar elements and features. Although embodiments of the present invention will be described in conjunction with the illustrated embodiments, it will be appreciated that the invention is not intended to be limited to such embodiments.

The present disclosure teaches methods, devices, and systems for encoding and decoding codewords in wireless networks. Although described primarily with respect to 802.11ad networks, the present disclosure may also apply to other blocking coding-based systems.

FIG. 1A shows a communication network 100 with a plurality of stations (STA) 102 and access points (AP) 104. Each of the STA102 and AP104 can include a transmitter, a receiver, a encoder, and / or a decoder, as described herein. Network 100 is an IEEE802.11 network, 5th generation (5G) or 4th generation (4G) telecommunications network, new generation communication standard (LTE), 3rd generation partnership project (3GPP), universal mobile communication system (UMTS). ) And other wireless or mobile communications networks, but may be operated by one or more communications or data standards or technologies. The STA102 can generally be any device that can provide wireless communication or can use the 802.11 protocol. The STA102 is a laptop, desktop PC, PDA, access point or Wi-Fi phone, wireless transmitter / receiver (WTRU), mobile station (MS), mobile device, smartphone, mobile phone, or other wireless-enabled computing or mobile device. Can be. In some embodiments, the STA 102 comprises a machine capable of transmitting, receiving, or transmitting and receiving data within the communication network 100, but performing key functions other than communication. In one embodiment, the machine includes a device or device having means for transmitting and / or receiving data over the communication network 100, such device or device is usually for the primary purpose of communication. Not operated by the user. The AP104 may include a base station (BS), an advanced node B (eNB), a wireless router, or other network interface that acts as a wireless transmit and / or receive point for the STA102 within network 100. The AP104 is connected to a backhaul network 110 that allows data to be exchanged between the AP104 and other remote networks, nodes, APs, and devices (not shown). The AP104 can support communication with each STA102 by establishing uplink and downlink communication channels with each STA102, as represented by the arrows in FIG. 1A. Communication within network 100 may be unscheduled, may be scheduled by AP104, or by a scheduling or management entity (not shown) within network 100, or is not scheduled with scheduled communication. It may be mixed with communication.

FIG. 1B shows an exemplary processing system 150 that can be used to implement the methods and systems described herein, such as STA102 or AP104. The processing system 150 can be, for example, a base station, a wireless router, a mobile device, or any suitable processing system. Other processing systems suitable for carrying out this disclosure may be used, which may include components different from those discussed below. Although FIG. 1B shows a single instance of each component, there may be multiple instances of each component within the processing system 150.

The processing system 150 can include one or more processing devices 152 such as processors, microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), dedicated logic circuits, or combinations thereof. The processing system 150 shall also include one or more input / output (I / O) interfaces 154 that may allow interface with one or more suitable input and / or output devices (not shown). Can be done. One or more input and / or output devices may be included as components of the processing system 150 or may be external to the processing system 150. The processing system 150 is, but is not limited to, an intranet, internet, P2P network, WAN, LAN, WLAN and / or cellular, or a network such as a mobile communication network such as 5G, 4G, LTE or other networks as described above. It can include one or more network interfaces 158 for wired or wireless communication with. Network interface 208 can include wired links (eg, Ethernet® cables) and / or wireless links (eg, one or more radio frequency links) for intra-network and / or inter-network communication. The network interface 158 can provide wireless communication, for example, via one or more transmitters or transmit antennas, one or more receivers or receive antennas, and various signal processing hardware and software. In this example, a single antenna 160 that can act as both a transmit and receive antennas is shown. However, in other examples, there may be separate antennas for transmission and reception. Network interface 158 may be configured to send and receive data to and from backhaul network 110 or other user devices, access points, receiving points, transmitting points, network nodes, gateways or relays (not shown) within network 100. it can.

The processing system 150 can also include one or more storage 170s that can include mass storage devices such as solid state drives, hard disk drives, magnetic disk drives and / or optical disk drives. The processing system 150 can include one or more memories 172 that can include volatile or non-volatile memory (eg, flash memory, random access memory (RAM), and / or read-only memory (ROM)). .. The non-temporary memory 172 can store instructions for execution by the processing device 152, such as executing the present disclosure. Memory 172 can contain other software instructions, such as implementing an operating system and other applications / features. In some examples, one or more datasets and / or modules may be provided by external memory (eg, an external drive that is in wired or wireless communication with the processing system 150), or may be temporary or non-temporary. It may be provided by a computer-readable medium. Examples of non-temporary computer readable media include RAM, ROM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, CD-ROM, or other portable memory storage.

The processing system 150 can include a encoder 162 for encoding the source word into a codeword and / or a modulator 164 for modulating the codeword into a symbol. The encoder 162 can perform encoding on the source word to generate a bit-by-bit codeword. Modulator 164 can then perform modulation on the codeword (eg, by modulation techniques such as BPSK, QPSK, 16QAM, or 64QAM). In some examples, the instructions coded in memory 172 are the encoder 162 and / or the modulator 164 because the encoder 162 and / or the modulator 164 may not be a separate module of the processing system 150. The processing device 152 can be configured to perform the functions of. In some examples, the encoder 162 and the modulator 164 can be embodied within the transmitter module within the processing system 150. In some examples, the transmit antenna 160, the encoder 162, and the modulator 164 can be embodied as external transmitter components of the processing system 150 and can simply convey the source language from the processing system 150. it can.

The processing system 150 can include a demodulator 180 and a decoder 190 for processing the received signal. The demodulator 180 can perform demodulation on the received modulated signal (eg, BPSK, QPSK, 16QAM, or 64QAM signal). The decoder 190 can then perform appropriate decoding on the demodulated signal in order to restore the original signal contained in the received signal. In some examples, the instructions coded in memory 172 are the demodulator 180 and / or the decoder 190, because the demodulator 180 and / or the decoder 190 may not be a separate module of the processing system 150. The processing device 152 can be configured to perform the functions of. In some examples, the demodulator 180 and the decoder 190 can be embodied in a receiver module within the processing system 150. In some examples, the receiving antenna 160, the demodulator 180, and the decoder 190 can be embodied as external receiver components of the processing system 150, and the signal decoded from the received signal is sent to the processing system 150. You can simply tell.

Provides communication between components of processing system 150 including processing device 152, I / O interface 154, network interface 158, encoder 162, modulator 164, storage 170, memory 172, demodulator 180, and decoder 190. There may be bus 192. Bus 192 may be any suitable bus architecture, including, for example, a memory bus, a peripheral bus, or a video bus.

Communication between STA102 and AP104 in network 100 is by encoding the transmitted source words using Low Density Parity Check (LDPC) coding technology and / or the received codewords in the LDPC code. It can be carried out by decoding using a decoding technique. After the source word is encoded using the LDPC coding technique, when the codeword is transmitted as a signal from AP104 to STA102 or from STA102 to AP104, the LDPC coding information of the transmitted signal is It can be included in the transmission frame. After the transmitted signal is received by the STA102 or AP104 along with the LDPC coding information of the received signal, the STA102 or AP104 can select an appropriate LDPC decoding technique for decoding the received signal.

Transmitter and Coder Figure 2A shows an example implementation of a STA102 or AP104 transmitter. The transmitter can include a source word splitting module 202, an LDPC encoder 204, a bit-to-symbol mapping modulator 206, and a blocking module 208.

FIG. 2B shows an exemplary step of processing an input information bitstream by a transmitter.

The source word splitting module 202 can be used to split the input information bitstream into source words of appropriate size (step 222). For example, using the source word splitting module 202, the input information bit stream is 336 bits (for a 1/2 coding rate of 802.11ad), 420 bits (for a 5/8 coding rate of 802.11ad), 504. Bits (for 802.11ad 3/4 encoding rate), 546 bits (for 802.11ad 13/16 encoding rate), and 588 bits (for codeword size 672 bits, 7/8 encoding rate) Can be divided into source words of the size (in the case of). The K-bit source word can be thought of as a 1 × K row vector or a one-dimensional binary 1 × K matrix. For example, a 588-bit source word can be considered as a 1x588 row vector or a one-dimensional binary 1x588 matrix.

The source word can then be encoded into a codeword using the LDPC encoder 204 (step 224). FIG. 3 shows an exemplary implementation of the LDPC encoder 204. In one embodiment, the LDPC encoder 204 can include an LDPC matrix generator 302, a generator matrix module 304, a source word input interface 306, and a codeword generator 308.

The LDPC parity check matrix generator 302 can generate, for example, the LDPC parity check matrix H which is a binary (NK) × N matrix with N = 672 and K = 588. The LDPC code is functionally defined by a sparse parity check matrix. The (n, k) LDPC code is a linear binary block code C with a k-dimensional subspace of ^{{0, 1} n.} Gaussian elimination and column reordering give the equivalent parity check matrix H = [P _{(n−k) × k} I _(n−k) ] in a systematic form, where P _{(n−k). ) × k} is a binary matrix, and I _(n−k) is an discriminant matrix of order n−k.

を満たし、

は、Nビットの符号語である。生成器行列モジュール304は、次に、生成されたバイナリ（K×N）生成器行列Gを符号語生成器308に転送する。 Based on the LDPC parity check matrix generated by the LDPC matrix generator 302, the generator matrix module 304 can generate the generator matrix G. The systematic form of the generator matrix G corresponding to H _{can be G = [I k} P ^T ], where "T" represents the matrix transpose. The generator matrix G is a binary K × N matrix. The row space of G is orthogonal to H so that ^{GH T = 0.} Therefore, in LDPC coding, when H is designed, G can be determined accordingly. Similarly, the matrix H

The filling,

Is an N-bit codeword. The generator matrix module 304 then transfers the generated binary (K × N) generator matrix G to the codeword generator 308.

と見なすことができる。ソース語入力インターフェース306は、次に、受信したソース語を符号語生成器308に転送する。ソース語

とバイナリ（K×N）生成器行列Gとを用いて、ソース語と生成器行列G

とを乗算することによって、符号語生成器308はNビットの符号語

を生成する。 The source word input interface 306 receives the source word from the source word division module 202. As mentioned above, the received source word is a row vector

Can be regarded as. The source word input interface 306 then transfers the received source word to the codeword generator 308. Source word

And the binary (K × N) generator matrix G, the source word and the generator matrix G

By multiplying with, the codeword generator 308 is an N-bit codeword.

To generate.

が符号語生成器308によって受信された後、符号語生成器308は、LDPC行列Hまたは生成器行列Gを生成せずに、符号語

を生成してもよい。 In one embodiment, the generator matrix G can be pre-stored in the LDPC encoder 204. Source word

Is received by the codeword generator 308, after which the codeword generator 308 produces the codeword without generating the LDPC matrix H or the generator matrix G.

May be generated.

は、次に、ビット対シンボルマッピング変調器206においてシンボルに変調される（ステップ226）。適切な変調技術は、BPSK、QPSK、16QAM、または64QAMであり得るが、これらに限定されない。BPSK、QPSK、および16QAM変調は、802.11adで規定されている。64QAM変調は、802.11REVmcで採用されている。BPSK変調では、バイナリビットは単にバイポーラ｛−1、1｝シンボルになるようにマッピングされる。QPSK、16QAMおよび64QAM変調では、入力符号化ビットストリーム（ビット単位の符号語

）は、それぞれ2、4および6ビットのセットにグループ化される。各ビットセットは、対応するコンスタレーション上のシンボルにマッピングされる。例えば、BPSK、QPSK、16QAM、および64QAMの場合、シンボルはそれぞれ1ビット、2ビット、4ビット、および6ビットを表す。複数のシンボルは、変調された符号語としてグループ化されてもよい。例えば、変調された符号語は、336のシンボル（802.11adのSC QPSKブロッキング用）、168のシンボル（802.11adのSC 16QAMブロッキング用）、112のシンボル（802.11adのSC 64QAMブロッキング用）を含むことができる。 With reference to Figure 2, the encoded codeword

Is then modulated into a symbol in the bit-to-symbol mapping modulator 206 (step 226). Suitable modulation techniques can be, but are not limited to, BPSK, QPSK, 16QAM, or 64QAM. BPSK, QPSK, and 16QAM modulation are specified in 802.11ad. 64QAM modulation is used in 802.11REVmc. In BPSK modulation, binary bits are simply mapped to be bipolar {-1,1} symbols. For QPSK, 16QAM and 64QAM modulation, input coded bitstreams (bitwise codewords)

) Are grouped into sets of 2, 4 and 6 bits, respectively. Each bitset is mapped to a symbol on the corresponding constellation. For example, for BPSK, QPSK, 16QAM, and 64QAM, the symbols represent 1 bit, 2 bits, 4 bits, and 6 bits, respectively. Multiple symbols may be grouped as modulated codewords. For example, a modulated codeword should contain 336 symbols (for 802.11ad SC QPSK blocking), 168 symbols (for 802.11ad SC 16QAM blocking), and 112 symbols (for 802.11ad SC 64QAM blocking). Can be done.

The modulated codeword may be further assembled into appropriately sized data blocks (BLK) in blocking module 208 (step 228). In one embodiment, the assembled data block can contain 448 symbols as specified in the 802.11ad standard.

Therefore, the transmitter in Figure 2 can be used to generate the data blocks required by the 802.11ad standard.

Figure 4A shows an exemplary single carrier (SC) frame structure for the 802.11ad standard. Frames include short training field (STF), channel estimation (CE) field, PHY header, SC data block (BLK), and optional automatic gain control (AGC) and TRN-R / T sub for beam formation training. Includes fields. 802.11ad standard SC frames can contain multiple BLKs, as shown in Figures 4A and 4B.

Figure 4B shows an exemplary configuration of an SC data block (BLK) according to the 802.11ad standard. In Figure 4B, each BLK consists of 448 symbols. A 64-bit guard interval (GI) is used for each of the two adjacent BLKs to separate adjacent data blocks.

LDPC code with codeword length 672 in 802.11ad
Since the LDPC coded codeword is generated through the operation of the source word and the generator matrix G, and the generator matrix G is derived from the LDPC parity check matrix H, the LDPC parity check matrix H is the codeword of the source word. Affects the transformation. The design of the LDPC parity check matrix H may improve code performance. The parity check matrix H may be further divided into square sub-matrix of size Z × Z. Z is the lifting coefficient. The submatrix is either a cyclic permutation of the identity matrix or a null submatrix with all zero entries.

The position with the index i indicates the cyclic permutation submatrix Pi obtained from the _{Z × Z identity matrix P 0} by cyclically shifting the column to the right by i elements.

Figures 5A-5D show the parity check matrices for the four LDPC codes at rates 1/2, 5/8, 3/4, and 13/16 as defined by 802.11ad. In 802.11ad, each LDPC code has a common codeword length of 672 bits. The code rate K / N indicates that the K-bit source word is encoded into the N-bit codeword. For the 802.11ad standard, the codeword length N is 672 bits. Therefore, for the 1/2, 5/8, 3/4, and 13/16 code rates, the corresponding source word sizes are 336 bits, 420 bits, 504 bits, and 546 bits, respectively.

FIG. 5E shows exemplary cyclic permutation sub-matrixes P ₁ and P ₃ obtained from the Z × Z identity matrix P ₀ . In FIG. 5E, Z = 4. P ₁ is obtained by shifting the column of P _{0 to} the right by one element, and P ₃ is obtained by shifting the column of P _{0 to} the right by three elements.

In FIG. 5A, the submatrix with the value "0" _{represents P 0} , which is a unit submatrix of 42 x 42, and in FIG. 5A, the first submatrix with the value "40" has 40 elements in the column of _{P 0.} Obtained by shifting to the right by a minute. _{Similarly, the sub-matrix P i} of any nonzero value i in FIGS. 5B-5D can also be obtained from the respective identity matrix P _0.

FIG. 5A shows an LDPC parity check matrix H = 336 rows × 672 columns with a coding rate of 1/2, and Z = 42. FIG. 5B shows an LDPC parity check matrix H = 252 rows × 672 columns with a coding rate of 5/8, and Z = 42. FIG. 5C shows an LDPC parity check matrix H = 168 rows × 672 columns with a coding rate of 3/4, and Z = 42. FIG. 5D shows an LDPC parity check matrix H = 126 rows × 672 columns with a coding rate of 13/16, and Z = 42. In FIGS. 5A-5D, blank entries represent a Z × Z submatrix with all zero entries.

LDPC Codes with Codeword Length 1344 in 802.11ay Figures 6A-6D show the four LDPC codes proposed in 802.11ay at the rates 13/16, 3/4, 5/8 and 1/2. The code rate K / N indicates that the K-bit source word is encoded into the N-bit codeword. For the 802.11ay standard, the codeword length N is 1344 bits. Therefore, for the 13/16, 3/4, 5/8 and 1/2 coding rates, the corresponding source word sizes are 1092, 1008, 840 and 672 bits, respectively.

The LDPC codes shown in FIGS. 6A-6D are generated by two-step lifting. In the example of FIG. 6A, the LDPC code 606 with a codeword length of 1344 and a rate of 13/16 has a lifting matrix 602 and a base matrix 604 with a lifting factor Z = 42 and an 802.11ad rate of 13/16 as shown in FIG. 5D. Generated from and. In other words, the base matrix 604 has 126 rows x 672 columns at Z = 42, or has a sub-matrix of 3 rows x 16 columns.

As shown in FIG. 6A, the lifting matrix 602 has the same row and column sub-matrix as the 802.11ad rate 13/16 base matrix 604.

The lifting matrix 602 is proposed in the IEEE 802.11ay standard to provide a second lifting. Each entry in the lifting matrix 602 has one of three possible values "1", "0", and "-1". If the submatrix of the base matrix 604 is null, represented as "−1", then the corresponding entry in the lifting matrix 604 is also represented as "−1". For example, the entries in row 1, column 16 of the lifting matrix 604 correspond to the sub-matrix of row 1, column 16 of the base matrix 602. Both the entry in the lifting matrix 604 and the submatrix in the base matrix 602 have the value "-1".

A lifting matrix 602 is applied to the 13/16 LDPC base matrix 604 with codeword length 672 to generate 13/16 LDPC code 606 with codeword length 1344. In particular, for a submatrix with the value "V" of the base matrix 604, if the entry of the corresponding lifting matrix 602 has the value "1", then applying the lift matrix 602 to the base matrix 604 will result in the following four submatrix: Will be generated.

For a submatrix with the value "V" of the base matrix 604, if the entry of the corresponding lifting matrix 602 has the value "0", applying the lift matrix 602 to the base matrix 604 produces the following four submatrix: To.

In FIG. 6A, in the example of the sub-matrix of row 1 and column 1 having the value "29" of the base matrix 604 as the corresponding entry of row 1 and column 1 of the lifting matrix 602 with the value "1", the lifting matrix 602 Applying the entry in to the corresponding submatrix of the base matrix 604 produces the following four submatrix:

Similarly, in the example of the sub-matrix of row 3 and column 9 with the value "4" of the base matrix 604 as the corresponding entry in row 3 and column 9 of the lifting matrix 602 with the value "0", the lifting matrix 602 Applying the entry to the corresponding submatrix of the base matrix 604 produces the following four submatrix:

For the sub-matrix with the value "-1" in the base matrix 604, the corresponding entry in the lifting matrix 602 also has the value "-1". Applying one entry with the value "−1" in the lifting matrix 602 to the corresponding submatrix in the base matrix 604 produces four null submatrix.

Similarly, using the same rules as described above for a rate 13/16 LDPC code with codeword length 1344, the corresponding lifting matrix 602 is codeword length 672 with 802.11ad, as shown in FIGS. 6B-6D. When applied to rate 3/4, 5/8 and 1/2 base matrix 604, rate 3/4, 5/8 and 1/2 LDPC codes with codeword length 1344 are generated.

Similarly, an LDPC code with a codeword length of 1344 can also be generated by increasing the lifting factor Z. In particular, to construct a code with a submatrix size of 672 × 2 = 1344, the structure of the base matrix and the column position shift remain the same, but the lifting factor increases from Z = 42 to Z = 84. For example, an 802.11ad codeword length 672 3/4 base matrix contains 168 rows x 672 columns and Z = 42, as shown in FIG. 5C. In other words, the 3/4 base matrix contains 4 rows x 16 columns of sub-matrix, each sub-matrix having a size of Z x Z (42 x 42). When the lifting factor Z increases from 42 to 84, the 3/4 base matrix containing the 4 rows x 16 columns submatrix becomes 336 rows x 1344 columns.

Proposed code
The 802.11ad standard does not specify an LDPC code with a coding rate of 7/8. A rate 7/8 LDPC code with codeword length 624 is introduced in 802.11 REVmc. The 802.11 REVmc rate 7/8 LDPC code is based on the existing rate 13/16 LDPC code specified in 802.11ad by puncturing the first 48 parity bits from the rate 13/16 codeword. Will be generated. In practice, the transmitter does not transmit the punctured bits and the receiver puts an equal likelihood of 1/0 for the punctured bits. The source and codeword sizes of the rate 7/8 code are 546 bits and 624 bits, respectively.

A rate 7/8 LDPC code with codeword length 1248 is introduced in 802.11 ay. The 802.11ay rate 7/8 LDPC code is generated by puncturing the first 96 parity bits from a rate 13/16 LDPC code with codeword length 1344. In practice, the transmitter does not transmit the punctured bits and the receiver puts an equal likelihood of 1/0 for the punctured bits. The source and codeword sizes for the rate 7/8 code are 1092 bits and 1248 bits, respectively.

The 7/8 LDPC codes introduced in 802.11 REVmc and 802.11ay are not optimized and may require further improvements in their performance.

In addition, the LDPC codeword size has been changed from the standard 802.11ad 672 bits to 624 bits for 802.11 REVmc, and from 1344 bits for rates 1/2, 5/8, 3/4, and 13/16 to rate 7 / for 802.11ay. Changed to 8 1248 bits. However, the modulated codewords are still assembled into data blocks with a block size of 448 symbols in 802.11ad and 896 symbols in 802.11ay, so the blocking process for assembling the modulated codewords into data blocks must be modified accordingly. These changes in the assembly of data blocks require an additional process to perform the coding and decoding for the 7/8 LDPC code introduced in 802.11REVmc or the LDPC code proposed in 802.11ay.

For example, Figure 7A shows an example of SC QPSK blocking in 802.11ad and 802.11REVmc. In 802.11ad, QPSK turns one 672-bit codeword after modulation into one 336 symbol codeword. All three SC data blocks consist of four 336 symbol codewords, and each 448 symbol data block consists of two 336 symbol codewords, ie 448 = 336 + 112 or 448 = 224 + 224. However, in 802.11REVmc, the first 48 parity bits are punctured from the rate 13/16 LDPC code, so each codeword contains 624 bits, and in QPSK, one 624-bit codeword after modulation is 1. It becomes two 312 symbol codewords. As a result, the blocking process becomes more complex, with all 39 data blocks consisting of 56 codewords, and each data block consisting of 2 or 3 codewords, eg 448 = 312 + 136, or 448 = 176 + 272, Or 448 = 40 + 312 + 96, or 448 = 216 + 232, and so on.

Figure 7B shows an example of SC 16QAM blocking in 802.11ad and 802.11REVmc. With 802.11ad, 16QAM turns one 672-bit codeword after modulation into one 168 symbol codeword. All three SC data blocks consist of seven 168 symbol codewords, and each 448 symbol data block consists of three or four 168 symbol codewords, ie 448 = 168 + 168 + 112 or 448 = 56 + 168 + 168 + 56. However, in 802.11REVmc, each codeword contains 624 bits, and in 16QAM, one 624-bit codeword after modulation becomes one 156 symbol codeword. As a result, the blocking process becomes more complex, with all 39 data blocks consisting of 112 codewords and each data block consisting of 3 or 4 codewords, for example 448 = 156 + 156 + 136, 448 = 20 + 156 + 156 + 116, etc. is there.

Similarly, Figure 7C shows an example of SC 64QAM blocking in 802.11ad and 802.11REVmc. With 802.11ad, 64QAM turns one 672-bit codeword after modulation into one 112 symbol codeword. Each 448 symbol data block consists of four 112 symbol codewords, i.e. 448 = 112 + 112 + 112 + 112. However, in 802.11REVmc, one 624-bit codeword after modulation becomes one 104 symbol codeword. As a result, the blocking process becomes more complex, with all 13 data blocks consisting of all 56 codewords, and each data block consisting of 5 or 6 codewords.

In addition, the rate 7/8 LDPC code introduced in 802.11 REVmc has a codeword length (624 bits) that is different from the 672-bit LDPC codeword specified in 802.11ad. Coding of the source word in and decoding of the codeword in the receiver becomes more complicated.

は、LDPC符号器204において、1×Nの符号語ベクトル

に符号化することができる。GはKxNの生成器行列である。Gは、リフティング係数Zを有する（N−K）×Nのパリティ検査行列H＝［P_{（n−k）×k}I_（n−k）］
から導出することができる。

はバイナリ行列であり、

は位数N〜Kの識別行列である。H_nは複数のサブ行列を含み、各サブ行列はZ×Zのサイズを有する。H_n内の少なくとも1つのサブ行列はm₁の「1」の対角要素を含み、m₁は2以上の整数である。 New Code In one embodiment of the present disclosure, a 1 × K source word line vector.

Is a 1 × N codeword vector in the LDPC encoder 204.

Can be coded into. G is the generator matrix of KxN. G has a lifting coefficient Z (N−K) × N parity check matrix H = [P _{(n−k) × k} I _(n−k) ]
Can be derived from.

Is a binary matrix,

Is an identification matrix of orders N to K. H _n contains multiple sub-matrixes, each sub-matrix having a size of Z × Z. At least one sub-matrix in H _n includes a diagonal elements of "1" of the m _1, m ₁ is an integer of 2 or more.

である。「T」は行列

転置を表す。 Then G is derived from H, ie

Is. "T" is a matrix

Represents transpose.

In one embodiment of the present disclosure, the K / N rate LPDC parity check matrix H _n may be generated from the M × N parity check matrix H in the LDPC matrix generator 302 using the lifting factor Z. Here, M = IxZ, N = JxZ, I and J are integers of 2 or more. As shown in FIG. 8, the M × N parity check matrix H may be further divided into square sub-matrixes of size Z × Z (step 802). The divided parity check matrix H includes a sub-matrix of (M / Z) rows × (N / Z) columns. In other words, the divided parity check matrix H includes an M / Z check node and an N / Z variable node. The LPDC code of the K / N rate can be obtained by generating a _{new parity check matrix H n} from the divided parity check matrix H using the lifting coefficient Z. _{In particular, the LDPC matrix generator 302 can select m 1} row from the M / Z rows of the submatrix of the split parity check matrix H (step 804), where m ₁ > = 2 and the split parity. _{You can add m 1} row of the submatrix of the check matrix H as a new row of the submatrix of the new matrix H _n (step 806). Each of the remaining rows ((M / Z) −m ₁ ) of the submatrix of the divided parity check matrix H becomes one row of the _{new matrix H n.} In this case, the new parity check matrix matrix H _n contains a sub-matrix of ((M / Z) −m ₁ + 1) rows × (N / Z) columns. In other words, the new parity check matrix H _n contains (((M / Z) −m ₁ + 1) × Z) = N−K.

In one embodiment, the LDPC matrix generator 302 takes _{m 2 rows from the remaining rows ((M / Z) −m 1} ) of the submatrix of the divided parity check matrix H to the second of the submatrix of the new matrix H _n. It can be added as a new line (step 808), where m ₁ and m ₂ are integers, m ₁ + m ₂ = <M / Z, m ₁ > 1 and m ₂ > = 1. In one embodiment, m ₂ + m ₂ = M / Z, so in this embodiment the new matrix H _n includes a submatrix of 2 rows X (N / Z) columns.

In one embodiment, N = 672, Z = 42, and the LDPC parity check matrix H _n can be generated from the LDPC parity check matrix H of M rows X 672 columns, and Z = 42. The M × 672 parity check matrix H can be further divided into square matrices of size 42 × 42. The divided parity check matrix H includes a sub-matrix of (M / 42) rows × (672/42) columns. In other words, the divided parity check matrix H contains M check nodes and 672 variable nodes. In one embodiment, a 7/8 rate LPDC code may be obtained _{from the split parity check matrix H based on a new matrix H n with Z = 42. In particular, the LDPC matrix generator 302 adds m 1} row of the submatrix of the split parity check matrix H as the first submatrix row of the new matrix H _n. In one embodiment, the LDPC matrix generator 302 takes _{m 2 rows from the remaining rows ((M / Z) −m 1} ) of the submatrix of the divided parity check matrix H to the second row of the submatrix of the new matrix H _n. And where m ₂ > = 1 and m ₂ + m ₂ = <M / 42. In one embodiment, m ₂ + m ₂ = M / 42, so in this embodiment the new matrix H _n includes a submatrix of 2 rows × (672/42) columns.

In one embodiment, N = 1344, Z = 84, and the LDPC parity check matrix H _n can be generated based on the LDPC parity check matrix H of M rows × 1344 columns, and Z = 84. The M × 1344 parity check matrix H can be further subdivided into square matrices of size 84 × 84. The divided parity check matrix H includes a sub-matrix of (M / 84) rows × (1344/84) columns. In other words, the split parity check matrix H contains a check node of M and a variable node of 1344. In one embodiment, the 7/8 rate LDPC code may be obtained _{from the split parity check matrix H based on a new matrix H n with Z = 84.} In particular, first, the LDPC matrix generator 302 _{adds m 1} row of the submatrix of the divided parity check matrix H as the first submatrix row of the new matrix H _{n. Second, the LDPC matrix generator 302 adds m 2} rows of the submatrix of the split parity check matrix H as the second submatrix row of the new matrix H _n. M ₁ and m ₂ are integers, m ₁ + m ₂ = <M / 84, m ₁ > 1 and m ₂ > = 1. In one embodiment, m ₁ + m ₂ = M / 84, so in this embodiment the new matrix H _n contains a submatrix of 2 rows × 16 columns and Z = 84.

In one embodiment, N = 1344, Z = 42, and the LDPC parity check matrix H _n can be generated based on the LDPC parity check matrix H of M rows × 1344 columns, and Z = 42. The M × 1344 parity check matrix H can be further divided into square matrices of size 42 × 42. The divided parity check matrix H includes a sub-matrix of (M / 42) rows × (1344/42) columns. In other words, the split parity check matrix H contains a check node of M and a variable node of 1344. In one embodiment, a 7/8 rate LPDC code may be obtained _{from the split parity check matrix H based on a new matrix H n with Z = 42.} In particular, first, the LDPC matrix generator 302 _{adds m 1} row of the submatrix of the divided parity check matrix H as the first submatrix row of the new matrix H _{n. Second, the LDPC matrix generator 302 adds m 2} rows of the submatrix of the split parity check matrix H as the second submatrix row of the new matrix H _{n. Third, the LDPC matrix generator 302 adds m 3} rows of the submatrix of the split parity check matrix H as the third submatrix row of the new matrix H _n. Finally, the LDPC matrix generator 302 adds _{m 4} rows from the remaining rows of the submatrix of the split parity check matrix H as the fourth row of the submatrix of the new matrix H _n. m ₁ , m ₂ , m ₃ , and m ₄ are integers, m ₁ + m 2 ₊ m ₃ + m ₄ <M / 42, m ₁ > 1, m ₂ > = 1, m ₃ > = 1, and m ₄ > = 1. In one embodiment, m ₁ + m 2 ₊ m ₃ + m ₄ = M / 42, so the new matrix H _n contains a submatrix of 4 rows × 32 columns.

In one embodiment, in the LDPC parity check matrix H, M = 126, N = 672, Z = 42, and the new matrix H _n includes 84 rows × 672 columns.

In one embodiment, in the LDPC parity check matrix H, M = 168, N = 672, Z = 42, and the new matrix H _n includes 84 rows × 672 columns.

In one embodiment, in the LDPC parity check matrix H, M = 252, N = 672, Z = 42, and the new matrix H _n includes 84 rows × 672 columns.

In one embodiment, in the LDPC parity check matrix H, M = 336, N = 672, Z = 42, and the new matrix H _n includes 84 rows × 672 columns.

In one embodiment, in the LDPC parity check matrix H, M = 252, N = 1344, Z = 42, and the new matrix H _n includes 168 rows × 1344 columns.

In one embodiment, in the LDPC parity check matrix H, M = 336, N = 1344, Z = 42, and the new matrix H _n includes 168 rows × 1344 columns.

In one embodiment, in the LDPC parity check matrix H, M = 504, N = 1344, Z = 42, and the new matrix H _n includes 168 rows × 1344 columns.

In one embodiment, in the LDPC parity check matrix H, M = 672, N = 1344, Z = 42, and the new matrix H _n includes 168 rows × 1344 columns.

_{By adding m 1} , m ₂ , m ₃ , or m ₄ rows from the M / Z row submatrix of the split parity check matrix H to generate a new row, at least one submatrix of the new row As shown in the example of FIG. 11, it contains diagonal elements of "1" of _{m 1} , m ₂ , m ₃ , or m _{4, which will be described later.}

In one embodiment, the 7/8 rate LDPC parity check matrix H _n is Z = 42 of the rate 13/16 LDPC code specified in 802.11ad and is generated from H containing 126 rows × 672 columns. Alternatively, it may be generated from an LDPC parity check matrix H at a rate of 13/16 containing 252 rows x 1344 columns with Z = 84.

As shown in FIG. 5D, the LDPC parity check matrix H at a rate of 13/16 has 126 rows × 672 columns and Z = 42. In other words, the LDPC parity check matrix H at a rate of 13/16 includes the divided sub-matrix of 3 (= 126/42) rows × 16 (= 672/42) columns, and the size of each sub-matrix is 42 × 42. .. In one embodiment, the 7/8 rate LDPC code selects the first row with the second row of the split submatrix of the 802.11ad rate 13/16 LDPC parity check matrix H, and with the second row of the split submatrix. It can be obtained by adding the first row as the first row of the new LDPC parity check matrix H _n. The remaining third row is selected as the second row of the new LDPC parity check matrix H _n. As shown in Figure 9A, the new LDPC parity check matrix H _n contains a 42 × 42 2-row × 16-column sub-matrix.

Similarly, the LDPC parity check matrix H with a codeword length of 1344 and a rate of 13/16 includes a split submatrix of 3 (= 252/84) rows x 16 (= 1344/84) columns, and Z = 84. The size of each submatrix is 84x84. In one embodiment, the 7/8 rate LDPC code selects the first row along with the second row of the split submatrix of the rate 13/16 rate 13/16 LDPC parity check matrix H with codeword length 1344, and the first row of the split submatrix. It can be obtained by adding the first row along with the two rows as the first row of the new LDPC parity check matrix H _n. The remaining third row is selected as the second row of the new LDPC parity check matrix H _n.

In another embodiment, the 7/8 rate LDPC parity check matrix H _n sets the second row of the split submacheck of the 802.11ad rate 13/16 LDPC parity check matrix H to the second row of the new LDPC parity check matrix H _n . Select as one row, then select the first and third rows of the split submacheck of the rate 13/16 LDPC parity check matrix H, and select the first and third rows of the split submacheck with the new LDPC parity. It can be generated by adding it as the second line of the check H _n. Again, as shown in Figure 10B, the new LDPC parity check matrix H _n contains a 42 x 42 2-row x 16-column sub-matrix.

Similarly, the 7/8 rate LDPC parity check matrix H _n is a new LDPC parity check on the second row of the divided sub-macheck of the rate 13/16 rate 13/16 LDPC parity check matrix H with a code term length of 1344 and Z = 84. Select as the first row of the matrix H _n , then select the first and third rows of the divided sub-macheck of the LDPC parity check matrix H with a code-word length 1344 and a rate of 13/16, and select the first and third rows of the divided sub-macheck. It can be generated by adding lines 1 and 3 as the second line of the new LDPC parity check H _n. Again, the new LDPC parity check matrix H _n contains 84 x 84 2 rows x 16 columns submatrix.

In general, the 7/8 rate LDPC parity check matrix H _n is generated using H containing 126 rows x 672 columns, with Z = 42 from the rate 13/16 LDPC code specified in 802.11ad. It may also be generated from an LDPC parity check matrix H with a rate of 13/16 containing 252 rows x 1344 columns with Z = 84. First, in order to generate one row of new 7/8 rate LDPC parity check matrix H _n , the LDPC matrix generator 302 is a split sub of any two rows of rate 13/16 LDPC parity check matrix H. You can select and add a matrix. Second, the LDPC matrix generator 302 selects the remaining one row of the split submatrix of the rate 13/16 LDPC parity check matrix H as another _{row of the new 7/8 rate LDPC parity check matrix H n.} can do.

In one embodiment, the 7/8 rate LDPC parity check matrix H _n is Z = 42 and may be generated from a rate 3/4 LDPC parity check matrix H containing 168 rows × 672 columns, or Z. = 84, and may be generated from the LDPC parity check matrix H having a rate of 3/4 including 336 rows × 1344 columns.

As shown in FIG. 5C, the LDPC parity check matrix H at a rate of 3/4 includes 168 rows × 672 columns, and Z = 42. In other words, the rate 3/4 LDPC parity check matrix H contains 4 (= 168/42) rows x 16 (= 672/42) columns of divided sub-matrix, and the size of each sub-matrix is 42 x 42. .. Similarly, the LDPC parity check matrix H, which contains 336 rows x 1344 columns and has a Z = 84 rate of 3/4, also consists of 4 rows x 16 columns of divided sub-matrix, and the size of each sub-matrix is 84 x 84. is there.

In one embodiment, the parity check matrix of the 7/8 rate LDPC parity check matrix H _n having a code term length of either 672 or 1344 is the third of the divided sub-matrix of the rate 3/4 LDPC parity check matrix H. It can be generated by selecting rows 1 and 3 and adding the third row along with the first row of the split submatrix as the first row of the new LDPC parity check matrix H _n. The remaining second and fourth rows of the then split submatrix may be selected and added as the second row of the _{new LDPC parity check matrix H n.} FIG. 10A shows that the new rate 7/8 LDPC parity check matrix H _n contains 2 rows × 16 columns submatrix, and the size of each submatrix is Z × Z, where Z = 42 × 42. ..

In another embodiment, a 7/8 rate LDPC parity check matrix H _n having a code term length of either 672 or 1344 is first a second of the split sub-matrix of the rate 3/4 LDPC parity check matrix H. It can be generated by selecting rows and third rows and adding the selected second and third rows of the split submatrix as the first row of the new LDPC parity check matrix H _n. The remaining fist and fourth rows of the then split submatrix may be selected and added as the second row of the _{new LDPC parity check matrix H n.} FIG. 10B shows that the new LDPC parity check matrix H _n contains 2 rows × 16 columns of sub-matrix, and the size of each sub-matrix is Z × Z and Z = 42.

In general, for a 7/8 rate LDPC parity check matrix H _n with a sign length of either 672 or 1344, select any two rows of the split sub-macheck of the rate 13/16 LDPC parity check matrix H. Add the first row of the LDPC parity check matrix H _n for the new 7/8 rate, by using the remaining one line as the second row of the LDPC parity check matrix H _n for the new 7/8 rate, rate 13 / It can be generated from 16 LDPC parity check matrices H. When the codeword length is 672, Z = 42, and when the codeword length is 1344, Z = 84.

Similarly, for a 7/8 rate LDPC parity check matrix H _n having a code term length of either 672 or 1344, select two or more rows of any two or more of the divided sub-maeries of the rate 3/4 LDPC parity check matrix H. By adding as the first row of the new 7/8 rate LDPC parity check matrix H _n and adding the remaining one or more rows as the second row of the new 7/8 rate LDPC parity check matrix H _n. It can be generated from the LDPC parity check matrix H with a rate of 3/4. When the codeword length is 672, Z = 42, and when the codeword length is 1344, Z = 84.

_{Similarly, a 7/8 rate LDPC parity check matrix H n} with a sign length of either 672 or 1344 is either 2 of the split sub-machecks of a rate 1/2 or 5/8 LDPC parity check matrix H. Rate by adding more than one row as the first row of the new 7/8 rate LDPC parity check matrix H _n and the remaining rows as the second row of the _{new 7/8 rate LDPC parity check matrix H n.} It can be generated from a 1/2 or 5/8 LDPC parity check matrix H. When the codeword length is 672, Z = 42, and when the codeword length is 1344, Z = 84.

Codeword length = 1344, Z = 42
In one embodiment, the 7/8 rate LDPC code with codeword length 1344 is Z = 42 and may be generated from a rate 13/16 LDPC parity check matrix H containing 336 rows x 1344 columns. As shown in FIG. 6A, the generated matrix 606 H has 6 rows × 32 columns of sub-matrix, and the size of each sub-matrix is 42 × 42. In one embodiment, any three rows of the generated 1344 codeword 606 submatrix of FIG. 6A can be added as one row of _{the new 7/8 rate LDPC parity check matrix H n, and the rest.} The three rows of are the three rows of the 7/8 rate LDPC matrix H _{n with} a codeword length of 1344. In this case, the 7/8 rate LDPC matrix H _n with codeword length 1344 has a sub-matrix of 4 rows x 32 columns and Z = 42.

In another embodiment, any two rows of sub-matrix can be selected from the six rows of the generated matrix 606 H with codeword length 1344 of FIG. 6A. The two selected rows can then be added as one row of the new 7/8 rate LDPC parity check matrix H _n. The other two rows may be selected from the remaining four rows of the submatrix of matrix 606 H and added as the other row of _{the new 7/8 rate LDPC parity check matrix H n.} The remaining two rows of matrix 606 H are the remaining two rows of the 7/8 rate LDPC matrix H _n with codeword length 1344. In this case, the 7/8 rate LDPC matrix H _n with codeword length 1344 has a sub-matrix of 4 rows x 32 columns and Z = 42.

In one embodiment, the selected rows are derived from different rows of the base parity check matrix 604.

In one embodiment, a K / N rate LDPC parity check matrix H _n and / or its corresponding generator matrix G, such as, for example, a 7/8 rate LDPC parity check matrix H _{n and / or its corresponding generator matrix G.} May be stored in advance in the memory of the transmitter for encoding the source word or the memory of the receiver for decoding the demodulated codeword.

In the examples of FIGS. 9A-9B and 10A-10B, the result of adding two rows of the permutation submatrix of the LDPC parity check matrix H at a rate of 13/16 or 3/4 was generated as above. In a 7/8 rate LDPC matrix, a double cyclic shift permutation matrix may be present in some sub-matrix. In FIGS. 9A-9B and 10A-10B, "-" indicates a null submatrix with all zero entries. A double cyclic shift permutation matrix exists when the two join sub-matrix are not null sub-matrix with all zero entries.

For example, 7/8 sub-matrix of Figure 9A indicated by "37 + 29" in the parity check matrix H _n of the code, as the first row of the new LDPC parity check matrix H _n, the parity of the LDPC rate 13/16 in 802.11ad It is obtained by adding the first row with the second row of the check matrix H, or by adding the second row with the third row of the parity check matrix H with an LDPC rate of 3/4 at 802.11ad. As shown in FIG. 11, the submatrix represented by "37 + 29" indicates two diagonal elements of "1". The first diagonal element of "1" is from columns 0-36, then columns 37-41, the second diagonal element of "1" is from columns 0-28, then columns 29-41. Because.

When two rows are added, the variable node degree distribution of the sign remains unchanged, but the degree of the check node is doubled, that is, there are two "1s" in each row. For example, row "10" in Figure 11 has two "1" s, one in column 5 and the other in column 40.

As mentioned above, in the example of code term length 672, when the LDPC matrix generator 302 generates a _{new K / N rate LPDC code matrix H n from the divided parity check matrix H, the LDPC matrix generator 302 first generates the LPDC code matrix H n. You can add m 1} row of the submatrix of the divided parity check matrix H as one row of the submatrix of the new matrix H _n (step 806), optionally from the remaining submatrix of the divided parity check matrix H. You can also add the selected m ₂ rows as the second row of a submatrix of the new matrix H _n (step 808), where m ₁ and m ₂ are integers, m ₁ + m ₂ = <M / Z. And m ₁ > 1 and m ₂ > = 1. In the example codeword length 1344, _{rows m 3} and m ₄ may be selected from the remaining sub-matrix of the split parity check matrix H, or added as the third or fourth row of the _{new matrix H n.} Good. In this case, m ₁ + m ₂ + m ₃ + m ₄ = <M / Z, m ₁ > 1, m ₂ > = 1, m ₃ > = 1, m ₄ > = 1.

If at least one _{submatrix is generated by all non-null submatrixes of m 1} , m ₂ , m ₃ , or m ₄ , then the M / Z rows of the split parity check matrix H to generate new rows of the submatrix. By adding m ₁ , m ₂ , m ₃ , and / or m ₄ rows from the sub-matrix of, at least one sub-matrix of the new row is m ₁ , m ₂ , m ₃ , or m ₄ "1". Includes diagonal elements. When m ₁ , m ₂ , m ₃ , or m ₄ rows are added, the variable node order distribution of the sign remains unchanged, but the order of the check nodes is m ₁ , m ₂ , m ₃ , or m ₄ That is, each row has a "1" _{of m 1} , m ₂ , m ₃ , or m _4.

Conjugation As shown in Figure 12, the LDPC code is an extended irregular repeat accumulation (eIRA) characterized by a parity check matrix (n−k, n) obtained by juxtaposition of _{two matrices H = [H 1} H 2]. It may be limited to a code structure, where H ₁ is the systematic part of (n−k) × (k), which is a block structure matrix whose constituent sub-matrix is a null or cyclic shift identity matrix of Z × Z. And H ₂ is a full-rank (n−k) x (n−k) matrix whose columns have a weight of 2 except for the last column.

To enhance the fact that the maximum variable node degree, error floor performance can be improved, the design algorithm can optionally have a constitutive submatrix with two or more diagonal elements with different cyclic shifts. To. For example, in FIG. 12, the submatrix with the value "9 + 24 + 31" contains three diagonal elements.

In FIG. 12, row 1 1202 is a submatrix index and does not form part of H1. Rows 2 and 3 1204 are sub-matrixes of H1 and are used to generate the LDPC matrix H.

In one embodiment, to generate a rate 7/8 LDPC matrix H with parameters K = 588, N = 672, and Z = 42, the code matrix H ₁ 1201 is of a submatrix of size 42 × 42. It has only 2 lines 1204. In the example of FIG. 12, the variable node degree may be, for example, a maximum of 4, and the first column is (9 + 24 + 31) + 41. H2 is an 84 × 84 full rank matrix with Z = 42.

As shown in FIG. 12, H1 contains a submatrix of 2 rows x 14 columns, and Z = 42. H2 is a full-rank matrix of 84 × 84, and its size corresponds to a sub-matrix of 2 rows × 2 columns, and Z = 42. Therefore, the size of H = [H ₁ H ₂ ] corresponds to a submatrix of 2 rows x 16 columns, and Z = 42.

In one embodiment, to generate the LDPC matrix H at rate 7/8 with parameters K = 1176, N = 1344, and Z = 84, the code matrix H1 1201 has two rows of submatrix of size 84 × 84. Has only 1204. H2 is a 168 × 168 full rank matrix.

As shown in FIG. 12, H1 contains a submatrix of 2 rows x 14 columns, and Z = 84. H2 is a full-rank matrix of 168 x 168, its size corresponds to a sub-matrix of 2 rows x 2 columns, and Z = 84. Therefore, the size of H = [H ₁ H ₂ ] corresponds to a submatrix of 2 rows x 16 columns, and Z = 84.

Performance The examples in Figures 13A to 13C include puncturing the 13/16 sign, adding the first and second lines of the 802.11ad 13/16 sign, and the first and second lines of the 3/4 code. Performance of _{Z = 42 and rate 7/8 N = 672 code H n} generated by adding the optimization code by juxtaposition of lines 3, 2 and 4, and H1 and H2. Is shown. The codewords in FIGS. 13A, 13B and 13C are modulated with QPSK, 16QAM and 64QAM, respectively.

As shown in FIGS. 13A, 13B, and 13C, for a given signal-to-noise ratio (SNR) value, the first and third lines, the second and fourth lines, and H1 of the 3/4 code. _{And the 7/8 rate LDPC parity check H n} generated by adding the juxtaposed optimization code of H2 generally has a lower frame error rate (FER). Alternatively, the 7/8 rate LDPC parity check H generated by adding the 1st and 3rd lines, the 2nd and 4th lines of the 3/4 code, and the optimization code by juxtaposition of H1 and H2. _n requires a lower SNR value to achieve a given FER.

For the 7/8 code generated by adding the first and second lines of the 13/16 code, for a given SNR, the 7/ generated by adding the first and second lines. The 8-rate LDPC parity check H _n generally has a slightly higher FER. However, the codeword length of this code is 672, which is the same as the codeword length of other codes specified in 802.11ad, so this 7/8 rate LDPC parity check H _n blocking and decoding. The blocking implementation remains unchanged, but the 7/8 code blocking and deblocking implementation punctured from the 802.11ad 13/16 code requires additional modifications at the transmitter and receiver. Become.

The examples in FIGS. 14A-14C are by puncturing the 13/16 sign (n = 1248, K = 1092), and the 1st and 3rd lines, 2nd and 4th lines of the 3/4 sign. Shows the performance _{of N = 1344 sign H n at} a rate of 7/8 with Z = 42 generated by the addition of. The codewords in Figures 14A, 14B, and 14C are modulated at QPSK, 16QAM, and 64QAM, respectively. As shown in Figures 14A, 14B, and 14C, for a given signal-to-noise ratio (SNR), the 7/8 rate generated by the 1st and 3rd lines, 2nd and 4th lines of the 3/4 code. The LDPC parity check H _{n of} is generally low in frame error rate (FER).

を復元するために、1×Nの行ベクトル

を生成する。有効な符号語であるためには

であり、

である。LDPC符号化信号を復号するために様々なアルゴリズム、例えばメッセージ通過アルゴリズムが利用可能である。図16は、LDPC符号化ソース語を復号するためにメッセージ通過アルゴリズムを使用するLDPC復号器の例である。LDPC復号を実施するために他の復号アルゴリズムを使用することもできる。メッセージ通過アルゴリズムが使用される場合、LDPC復号器1508は、コントローラ1602、検査ノードモジュール1604、および変数ノードモジュール1606を含むことができる。 Decoder and decoding method
The LDPC encoded signal can be received by the receiver of STA102 or AP104. As shown in the example of FIG. 15A, the receiver includes an equalization and deblocking module 1502, a demodulator 1504, an LLR calculator 1506, and an LDPC decoder 1508. Optionally, the LLR calculator 1506 can be a component of the demodulator 1504. As shown in FIG. 15B, using the received LDPC encoded signal, the equalization and deblocking module 1502 first equalizes the received signal 1501 to reduce intersymbol interference caused by the channel on which the received signal is transmitted. Then, the equalization signal is deblocked to restore the codeword symbol (step 1522). The demodulator 1504 demodulates the deblocked codeword symbols into bit-by-bit codewords, eg, BPSK, QPSK, 16QAM, or 64QAM (step 1524). The LLR calculator 1504 can be used to generate the log-likelihood ratio of the bit values of the deblocked codeword symbols (step 1526). The log-likelihood ratio can be used as an input for the LDPC decoder 1508. The LDPC decoder 1508 can then use the LDPC matrix H _n used to encode the source word to decode the demodulated signal, the signal having a 1 × N row vector S. (Step 1528). LDPC decoder 1508 is a 1 × K source word line vector

1 × N row vector to restore

To generate. To be a valid codeword

And

Is. Various algorithms are available for decoding LDPC encoded signals, such as message passing algorithms. FIG. 16 is an example of an LDPC decoder that uses a message-passing algorithm to decode an LDPC-encoded source word. Other decoding algorithms can also be used to perform LDPC decoding. When the message passing algorithm is used, the LDPC decoder 1508 can include a controller 1602, a check node module 1604, and a variable node module 1606.

As mentioned above, the LDPC coding information of the transmitted signal, such as the K / N rate LPDC code H _{n = (N−K) xN LDPC matrix information used to encode the source word, is transmitted.} May be included in the frame. In one embodiment of the present application, in the LDPC decoder 1508, the LPDC code H _n = (N−K) × N of the K / N rate can be used with the lifting coefficient Z. As explained in the coding process, H _n contains multiple sub-matrixes, each sub-matrix having a size of ZxZ. At least one sub-matrix in H _n includes diagonal elements of "1" in m _1, where m ₁ is an integer of 2 or more. A method of generating a parity check matrix is described in the coding process.

であり、

である。 Bit-by-bit codewords can be decoded using _{H n} , for example, using a message-passing algorithm (MPA) with an LLR value. As shown in the example of FIG. 17, LDPC decoding using MPA is an iterative decoding algorithm that uses the structure of the Tanner graph, which is a graph representation of _{the LPDC parity check matrix H n.} In the LDPC decoder 1508, each check node 1702 determines the value of the erased bit based on the LLR value if it is the only erased bit in its parity check equalization. The message passed along the Tanner Graph Edge 1706. At each iteration of the algorithm, each variable node 1704 sends a message (“external information”) to each inspection node 1702 to which the variable node 1704 is connected. Each check node 1702 sends a message (“external information”) to the variable node 1704 to which the check node 1702 is connected. By "external" in this context is meant that information already owned by inspection node 1702 or variable node 1704 is not passed to those nodes. The posterior probability for each codeword bit is calculated _{based on the signal received by the LLR calculator 1506 and the parity constraint defined in H n} , that is, to be a valid codeword.

And

Is.

In the decoding, at least one sub-matrix in H _n includes a diagonal elements of "1" in m _1, since it is m _1> = 2, the presence of the superimposed layers of the parity check matrix H _n is the hierarchy The impact on the implementation of the LDPC decoder 1508, which may be assumed to have a modified architecture, is small.

In the LDPC decoder 1508 layered architecture, the Z parallel check node processor sequentially processes edge messages for the Z row submatrix of the parity check matrix. In one example, Z = 42 and the edge is 16. The cyclic shift structure simplifies the decoder architecture, which allows it to be fed to a parallel processor using a simple barrel shifter. When the processing of one layer is completed, the parity check processor is reinitialized and the next layer is processed.

When a row of m ₁ is superimposed on a parity check node, at least one sub-matrix in H _n includes a diagonal elements of "1" in m _1, where m ₁ is an integer of 2 or more. The processor is not initialized after the end of the first layer, but rather continues to process the next 16 edges of the superposed submatrix rows. This process is repeated _once m. Therefore, the decryption complexity remains the same as the original code complexity, and the existing hardware architecture can be reused.

The present disclosure provides specific exemplary algorithms and calculations for implementing examples of the disclosed methods and systems. However, this disclosure is not bound by any particular algorithm or calculation. Although this disclosure describes a method and process in a particular sequence of steps, one or more steps of the method and process may be omitted or modified as needed. If desired, one or more steps can be performed in an order other than those listed.

Through the description of the embodiments described above, the invention can be implemented by using only the hardware, by using the software and the required general purpose hardware platform, or by a combination of the hardware and the software. Based on such an understanding, the technical solution of the present invention can be embodied in the form of a software product. Software products can be stored in compact disc read-only memory (CD-ROM), USB flash drives, or non-volatile or non-temporary storage media that can be hard disks. The software product includes several instructions that allow a computer device (personal computer, server, or network device) to perform the methods provided in embodiments of the present invention.

Having described the invention and its advantages in detail, it is understood that various modifications, substitutions and modifications can be made herein without departing from the invention as defined by the appended claims. I want to.

Moreover, the scope of this application is not intended to be limited to specific embodiments of the processes, machines, products, compositions, means, methods and steps described herein. Those skilled in the art can perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein, as will be readily appreciated from the disclosure of the present invention. Processes, machines, products, compositions, means, methods or steps that currently exist or are developed later can be used by the present invention. Therefore, the appended claims are intended to include such processes, machines, products, compositions, means, methods, or steps within that scope.

100 communication networks
102 stations
104 access points
110 Backhaul Network
150 processing system
152 Processing device
154 Input / output (I / O) interface
158 Network interface
160 Receiving antenna, transmitting antenna
162 Coder
164 Modulator
170 storage
172 Non-temporary memory
180 demodulator
190 Decoder
192 bus
202 Source word split module
204 LDPC encoder
206-bit vs. symbol mapping modulator
208 blocking module
302 LDPC parity check matrix generator
304 Generator Matrix Module
306 Source word input interface
308 Codeword Generator
1501 Received signal
1502 deblocking module
1504 demodulator
1506 LLR calculator
1508 LDPC decoder
1602 controller
1604 Inspection node module
1606 Variable Node Module
1702 inspection node
1704 variable node
1706 Tanner Graph Edge

Claims (11)

A way to code the source word
1 × K source word line vector

Steps to receive and
1 × N codeword vector

Including the steps to generate
G is a K × N generator matrix, where G is _{derived from a second low density parity check (LDPC) matrix H n} , the second matrix H _n containing multiple sub-matrixes of each sub-matrix. The size is Z × Z, and the second matrix H _n is

Is the way. The second matrix H _n is derived from the parity check matrix H of the first MxN, M = I × Z, N = J × Z, I and J are integers, and I> 2. The method of claim 1, wherein the first matrix H comprises (M / Z) rows and (N / Z) columns. The second matrix H _n is
_{Add m 1} row from the (M / Z) row as the row of the second matrix H _{n,
Derived by adding m 2} rows from the remaining rows of the (M / Z) row as another row of the second matrix H _{n , where m 1} is an integer greater than or _{equal to 2} and m 2 is 1 The method according to claim 2, which is the above integer. The first matrix H is an LDPC matrix having a coding rate of 3/4 defined by IEEE 802.11ad, and the first matrix H has 168 rows × 672 columns and Z = 42. The method of claim 2 or 3, wherein the second matrix H _n is derived using the parameters m ₁ = 2 and m _{2 = 2, Z = 42.} A method of decoding codewords
A step of receiving a demodulated signal with a 1 × N row vector S,
Including the step of decoding the 1 × N row vector S using the second low density parity check (LDPC) matrix H _{n used in the coding process.}
The second matrix H _n includes a plurality of sub-matrix, the size of each sub-matrix is Z × Z, and the second matrix H _n is.

Is the way. The second matrix H _n is derived from the parity check matrix H of the first MxN, M = I × Z, N = J × Z, I and J are integers, and I> 2. The method of claim 5, wherein J> 0 and the first matrix H comprises (M / Z) rows and (N / Z) columns. The second matrix H _n is
_{Add m 1} row from the (M / Z) row as the row of the second matrix H _{n,
Derived by adding m 2} rows from the remaining rows of the (M / Z) row as another row of the second matrix H _{n , where m 1} is an integer greater than or _{equal to 2} and m 2 is 1 The method according to claim 5, which is the above integer. The first matrix H is an LDPC matrix having a coding rate of 3/4 defined by IEEE 802.11ad, and the first matrix H has 168 rows × 672 columns and Z = 42. The method of claim 6 or 7, wherein the second matrix H _n is derived using the parameters m ₁ = 2 and m _{2 = 2, Z = 42.} An apparatus configured to perform the method according to any one of claims 1-8. A program that causes a computer to perform the method according to any one of claims 1 to 8. A computer-readable recording medium on which a program is recorded, wherein the program, when executed by the computer, causes the computer to perform the method according to any one of claims 1 to 8.

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