KR102539474B1 - Sc-ldpc codes for wireless communication systems - Google Patents

Abstract

A receiving node such as a mobile station or base station is provided. The receiving node uses a receiver configured to receive signals including at least one codeword based on a spatially coupled low density parity check (SC-LDPC) code from the transmitting node, and a sliding window. and a decoder configured to decode the at least one codeword. Here, the sliding window selectively moves forward or backward.

Description

SC-LDPC codes for wireless communication systems {SC-LDPC CODES FOR WIRELESS COMMUNICATION SYSTEMS}

The present invention relates generally to wireless communications, and more particularly to data encoding and decoding in wireless communication systems.

In information theory, low-density parity-check (LDPC) codes are error-correcting codes for transmitting messages over noisy transmission channels. LDPC codes are a type of linear block codes. LDPC and other error correcting codes cannot guarantee perfect transmission, but the probability of information loss can be made as small as desired. LDPC was the first code to allow data rates close to the theoretical maximum, known as the Shannon limit. LDPC codes can perform with a Shannon limit of 0.0045 dB. When LDPC was developed in 1963, it was impractical to implement. Discovered in 1993, turbo codes became the coding scheme of choice in the late 1990s. Turbo codes are used in applications such as deep-space satellite communications. Although LDPC requires complex processing, it is the most efficient method found so far in 2007. LDPC codes can reduce decoding complexity by yielding a large minimum distance (hereinafter "d _min ").

One aspect of the present disclosure provides LDPC codes that have higher performance than conventional low-density parity-check (LDPC) codes.

In a first embodiment, an apparatus is provided. The device includes an input buffer configured to receive a protograph-based spatially coupled low density parity check (SC-LDPC) code from a transmitter. The apparatus also includes decoder processing circuitry configured to perform an SC-LDPC decoding operation on an SC-LDPC code comprising a parity check matrix. The SC-LDPC decoding operation involves a sliding window containing a subset of protograph sections over which decoding calculations are repeatedly performed. Additionally, the SC-LDPC decoding operation includes a stopping rule configured to stop decoding calculations as a function of the syndrome of one or more check nodes (CN) in a sliding window.
In a second embodiment, a method is provided. The method includes receiving a protograph based SC-LDPC code from a transmitter. Also, the method includes performing an SC-LDPC decoding operation on the SC-LDPC codes that include parity check matrices. The SC-LDPC decoding operation includes a sliding window. The sliding window contains a subset of protograph sections over which decoding calculations are repeatedly performed. Additionally, the SC-LDPC decoding operation includes a stopping rule configured to stop decoding calculations as a function of the syndrome of one or more CNs in a sliding window.
In the third embodiment, a receiver is provided. The receiver includes at least one antenna and a sliding window-decoder. The antenna is configured to receive the protograph based SC-LDPC code from the transmitter. The sliding window-decoder is configured to perform SC-LDPC decoding operations on SC-LDPC codes using a sliding window. SC-LDPC codes include a parity check matrix. The sliding window contains a subset of protograph sections over which decoding calculations are repeatedly performed. The sliding window-decoder performs a stopping rule configured to stop decoding calculations as a function of the syndrome of CNs in the sliding window.
In a fourth embodiment, an apparatus is provided. The apparatus includes a receiver configured to receive signals including at least one codeword based on an SC-LDPC code from a transmitting node, and a decoder configured to decode the at least one codeword using a sliding window. The sliding window selectively moves forward or backward.
In the fifth embodiment, a method is provided. A method of operating a receiving node of a communication system includes receiving signals including at least one codeword based on an SC-LDPC code from a transmitting node, and decoding the at least one codeword using a sliding window. includes The sliding window selectively moves forward or backward.
Other technical features may be readily apparent to those skilled in the art from the following figures, descriptions and claims.
Before entering into the detailed description below, it may be helpful to understand the present invention to set forth definitions of certain words and phrases used throughout this patent document. The term “couple” and its derivatives may refer to any direct or indirect communication between two or more elements, or whether or not these elements are in physical contact with each other. The terms "transmit", "receive" and "communicate", as well as their derivatives, include direct and indirect communication thereof. The terms "include" and "comprise", as well as their derivatives, mean inclusion without limitation. The term "or" is inclusive and means 'and/or'. The phrase "associated with", as well as its derivatives, also include, be included within, interconnect with, contain , be contained within, connect to or with, couple to or with, be communicable with, cooperate with , interleave, juxtapose, be proximate to, be bound to or with, have, have properties It can mean a property of), have a relationship to or with. The term “controller” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware or a combination of hardware and software and/or firmware. Functions related to a particular controller may be centralized or distributed, either locally or remotely. When the phrase "at least one of" is used with a listed item, it means that different combinations of one or more of the listed items may be used. For example, “at least one of A, B, C” includes any one of A, B, C, A and B, A and C, B and C, and A and B and C combinations.
Definitions of certain words and phrases are provided throughout this disclosure, and skilled artisans should understand that, in most cases, these definitions are applicable to prior as well as future uses of the defined words and phrases. do.

Decoding performance can be improved.

For a more complete understanding of the present disclosure and effect, reference is made to the following detailed description in conjunction with the accompanying drawings, wherein reference numerals in the drawings indicate corresponding parts.
1 illustrates an exemplary wireless network in accordance with the present disclosure.
2A and 2B show exemplary wireless transmit and receive paths in accordance with the present disclosure.
3 illustrates an exemplary user equipment (UE) according to the present disclosure.
4 illustrates an exemplary enhanced NodeB (eNB) according to this disclosure.
5A, 5B, 5C and 5D show exemplary protograph based SC-LDPC code structures.
6 shows an example of a (3, 6, 720) protograph-based SC-LDPC code with a lifting factor Z = 112 according to the present disclosure.
7 illustrates a sliding window decoder according to the present disclosure.
8 illustrates a sliding window decoder 800 with an early stopping rule according to the present disclosure.
9 shows the bit error rate (BER) and frame error rate (FER) performance of this stopping rule according to the present disclosure.
10A and 10B show zigzag window decoder states according to the present disclosure.
10c and 10d show the decoding window schedule for the proposed zigzag window decoder according to the present disclosure.
10E shows an example of comparing a sliding window decoder according to the present disclosure and a proposed zigzag window decoder.
11A and 11B show examples of one Z round and two Z rounds of the zigzag window decoder according to the present disclosure.
12A and 12B show the performance of each zigzag window decoder according to the present disclosure.
13 shows the probability of correcting the divergence of size x protograph sections with one Z round of a zigzag window decoder according to the present disclosure.
14 shows the FER (dotted line) and BER (solid line) performance of a zigzag window decoder with different Z window sizes according to the present disclosure.
15 shows average iteration number performance of a zigzag window decoder applying an early codeword failure detection rule with different Z window sizes according to the present disclosure.
16 illustrates a (3, 6) protograph-based SC-LDPC code according to the present disclosure.
17 shows a rate-1/2 protograph based SC-LDPC code punctured at rate-3/4 using a puncturing pattern according to the present disclosure.
18 shows an infinitely long SC-LDPC code divided into several block LDPC codes using divider protograph sections according to the present disclosure.
19 shows a very long SC-LDPC code split into several block LDPC codes using unequal error protection according to the present disclosure.
20 illustrates a method of using stronger header protection to create divider protograph sections according to this disclosure.
21 illustrates an example of strengthening a portion of an SC-LDPC codeword using an iteration, or shortened then iterative process to convey packet headers according to this disclosure.
22 illustrates an example of hybrid automatic repeat request (HARQ) support using the SC-LDPC coding scheme according to the present disclosure.
23 is a puncturing matrix [1, 0, 1; 1, 1, 0] to show an example of puncturing a (3, 6, L) SC-LDPC ensemble at rate-3/4.
24 shows a rate-5/6 (3, 18) LDPC code protograph that can be shortened to rate-4/5, rate-3/4, rate-2/3, or rate-p according to the present disclosure; do.
25 is a (3, 18, L) SC- with rate-5/6 that can be shortened to rate-4/5, rate-3/4, rate-2/3, or rate-p according to the present disclosure. Shows the LDPC code protograph.
26 shows a comparison of FER performance of a punctured code group and a shortened code group according to the present disclosure.
27 shows a comparison of iteration count performances of a punctured code group and a shortened code group according to the present disclosure.
28 illustrates exemplary SC-LDPC code families based on shortening according to the present disclosure.
29 illustrates an operating process of a receiving node according to the present disclosure.

Z=42인 경우, 리프팅 행렬의 일 예는 아래의 표와 같다.

Z=27인 경우, 리프팅 행렬의 일 예는 아래의 표와 같다.

Z=24인 경우, 리프팅 행렬의 일 예는 아래의 표와 같다.

도 29는 본 개시에 따른 수신 노드의 동작 프로세스를 도시한다. 흐름도는 순차적인 일련의 단계들을 도시하지만, 명시적으로 언급하지 않는 한, 수행의 구체적인 순서, 중복 방식 또는 동시적이 아닌 순차적인 단계들 또는 그의 부분들의 수행, 또는 개입 또는 중간 단계들의 발생 없이 독점적으로 도시되는 단계들의 수행과 관련하여 해당 순서로부터 어떠한 추론도 이끌어내어서는 안된다. 도시된 예에 도시된 프로세스는 예를 들어 기지국 또는 단말기와 같은 수신 노드에서 구현된다.
도 29를 참조하면, 단계 2901에서, 수신 노드는 송신 노드로부터 SC-LDPC 코드를 기반으로 하여 적어도 하나의 코드워드를 포함하는 신호들을 수신한다. 적어도 하나의 코드워드는 SC-LDPC 코드를 사용하여 송신 노드에 의해 생성된다. 적어도 하나의 코드워드는 헤더 및 페이로드를 포함하는 패킷을 포함하고, 헤더는 하나 이상의 SC-LDPC 코드의 프로토그래프 섹션들을 분할하기 위한 디바이더 프로토그래프 섹션으로서 구성된다.
그 후, 단계 2903에서, 수신 노드는 슬라이딩 윈도우를 사용하여 적어도 하나의 코드워드를 디코딩한다. 여기서, 슬라이딩 윈도우는 선택적으로 순방향 또는 역방향으로 이동한다. 슬라이딩 윈도우는 현재의 슬라이딩 윈도우에서 하나 이상의 CN의 신드롬을 기반으로 하여 역방향으로 이동한다. 특히, 수신 노드는 중지 규칙이 충족될 때까지 반복적으로 디코딩 계산들을 수행한다. 중지 규칙은 현재의 슬라이딩 윈도우에서 하나 이상의 CN의 신드롬의 함수로서 정의된다.
SC-LDPC 코딩 방식은 HARQ를 지원한다. 이 경우, 수신 노드는 디코더가 프로토그래프 섹션들 내의 정보 비트들을 복구할 수 있는 한 SC-LDPC 코드의 프로토그래프 섹션들을 디코딩하고, 관련 패킷의 재전송을 요청하고, 디코더 실패에 응답하여 재전송된 관련 패킷을 기다리는 동안 수신된 정보를 계속 버퍼링한다. 다른 실시 예에서, 수신 노드는 적어도 실패한 패킷, 모든 패킷, 또는 실패의 시작부터의 섹션들을 버퍼링하고, 디코더 실패에 응답하여 다음 패킷의 헤더를 디코딩하기 시작한다, 재전송은 실패한 패킷과 관련된 모든 비트의 재전송, 패킷과 관련된 펑처링된 비트의 일부 또는 전부의 전송을 포함하는 증분 중복 재전송, 실패한 프로토그래프 섹션 및 실패한 패킷의 끝까지의 모든 다음 섹션들과 관련 모든 비트 또는 증분 중복의 재전송, 및 실패한 프로토그래프 섹션과만 관련되거나 실패한 프로토그래프 섹션 이후의 몇 개의 섹션들과 관련된 모든 비트 또는 증분 중복의 재전송 중 하나이다. 또한, 수신 노드는 단축 동작에 의해 SC-LDPC 코드의 레이트를 감소시킬 수 있다.
특허청 및 본 출원에 공표된 모든 특허의 독자들이 첨부된 청구 범위들을 해석하는 것을 돕기 위해, 출원인들은 "~를 위한 수단" 또는 "~를 위한 단계"라는 단어들이 특정 청구 범위에 명시적으로 사용되지 않는 한, 첨부된 청구 범위 또는 청구 범위 요소들의 어느 것도 35U.S.C.§112(f)를 적용하는 것을 의도하지 않는다는 점을 유의하기를 바란다. 청구 범위 내에서 "메커니즘", "모듈", "장치", "유닛", "구성 요소", "요소", "부재", "장치", "기계", "시스템", "프로세서", 또는 "제어기"를 제한 없이 포함하여 모든 다른 용어의 사용은 당업자들에게 알려진 구조들을 언급하는 것으로 출원인들에 의해 이해되며, 35U.S.C.§112(f)를 적용하기 위해 의도된 것은 아니다.
본 개시는 예시적인 실시 예로 설명되었지만, 다양한 변경 예 및 수정 예가 당업자에게 제안될 수 있다. 본 개시는 첨부된 청구 범위의 범위 내에 속하는 이러한 변경 예 및 수정 예들을 포함하는 것으로 의도된다.1 through 29 discussed below and the various embodiments used to explain the principles of the present disclosure are for illustrative purposes only and should not be construed as limiting the scope of the present disclosure in any way. Those skilled in the art will appreciate that the principles of this disclosure may be implemented in any suitably arranged wireless communication system.
The following documents are incorporated by reference as if set forth in this disclosure in their entirety. DJ Costello, Jr., L. Dolecek, TE Fuja, J. Kliewer, DGM Mitchell, and R. Smarandache, "Spatially Coupled Sparse Codes on Graphs - Theory and Practice," arXive, October 2013 (REF-1); Michael Lentmaier, Maria Mellado Prenda, and Gerhard P. Fettweis, "Efficient Message Passing Scheduling for Terminated LDPC Convolutional Codes," IEEE ISIT, August 2011 (REF-2); Shrinivas Kudekar, Tom Richardsony and Rødiger Urbanke, "Threshold Saturation via Spatial Coupling: Why Convolutional LDPC Ensembles Perform so well over the BEC," arXiv, October 2010 (REF-3); Vikram Arkalgud Chandrasetty, Sarah J. Johnson and Gottfried Lechner, "Memory Efficient Quasi-Cyclic Spatially Coupled LDPC Codes", arXive October 2013 (REF-4); and Najeeb ul Hassan, Michael Lentmaier, and Gerhard P. Fettweis, "Comparison of LDPC Block and LDPC Convolutional Codes Based on their Decoding Latency," IEEE ISTC August 2012 (REF-5); D. Hocevar, "A reduced complexity decoder architecture via layered decoding of LDPC codes," IEEE Workshop on Signal Processing Systems, 2004., pp. 107-112, Oct. 2004 (REF-6); Shadi Abu-Surra, Eran Pisek, Thomas Henige, and Sridhar Rajagopal, "Low-Power Dual Quantization-Domain Decoding for LDPC Codes," IEEE Globecom 2014 (REF-7); M. Davey and DJ Mackay, "Low density parity check codes over GF(q)," IEEE Commun. Letters, vol. 2, p. 165-167, Jun 1998 (REF-8); J. Chen, A Dholakia, E. Eleftheriou, M. Fossorier, "Reduced-Complexity Decoding of LDPC Codes," IEEE Trans. on Commun., vol. 53, pp. 53; 1288-1299, Aug. 2005 (REF-9); RG Gallager, "Low-density parity-check codes", Cambridge, MA: MIT Press, 1963 (REF-10); DJC MacKay and RM Neal, "Near Shannon limit performance of low density parity check codes," Electronics Letters, vol. 32, pp. 32; 1645-1646, Aug. 1996 (REF-11); IEEE 802.11ad standard spec., Part 11: Wireless LAN medium access control (MAC) and physical layer (PHY) Specifications, Amendment 3: Enhancements for very high throughput in the 60 GHz Band, (REF-12); RG Gallager, "A simple derivation of the coding theorem and some applications," IEEE Trans. on Information Theory, vol. 11, p. 3-18, Jan. 1965 (REF-13); IEEE 802.11n-2009 standard spec., Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications Amendment 5: Enhancements for Higher Throughput, retrieved from the Internet <URL: http://standards.ieee. org/getieee802/download/802.11ad-2012.pdf>(REF-14); 3GPP, "Evolved Universal Terrestrial Radio Access (E-UTRA); Physical channels and modulation; (release 11)," 3GPP, 2013, retrieved from the Internet <URL: http://www.3gpp.org/ftp/Specs/ html-info/36211.htm>(REF-15); DJ Costello, Jr., L. Dolecek, TE Fuja, J. Kliewer, DGM Mitchell, and R. Smarandache, "Spatially Coupled Sparse Codes on Graphs—Theory and Practice," arXive, October 2013, (REF-16); Michael Lentmaier, Maria Mellado Prenda, and Gerhard P. Fettweis, "Efficient Message Passing Scheduling for Terminated LDPC Convolutional Codes," IEEE ISIT, Aug. 2011, (REF-17); S. Abu-Surra, E. Pisek, and T. Henige, "Gigabit Rate Achieving Low-Power LDPC Codes: Design and Architecture," IEEE Wireless Commun. And Networking Conf., Mar. 2011, (REF-18); and D. Divsalar, S. Dolinar, and C. Jones, "Construction of Protograph LDPC Codes with Linear Minimum Distance," IEEE ISIT, Jul. 2006, (REF-19).
In a communication system, channel coding is important to achieve capacity access performance. Many schemes such as turbo codes and LDPC block codes are used in wireless communication standards. However, these coding schemes have limitations. For example, the structure of turbo codes does not provide sufficient parallelism to achieve very large gigabits per second (GB/s) throughput. Alternatively, the structure of LDPC block codes provides a large parallelism factor, but the granularity is limited by the fixed block size of the code.
Spatially-coupled low-density parity-check (SC-LDPC) codes are new capacity achieving codes that combine the advantages of both turbo codes and LDPC block codes. SC-LDPC codes have the potential to achieve high data rates and have a small granularity compared to LDPC block codes.
Embodiments of this disclosure relate to the design and decoding of SC-LDPC codes. Certain embodiments of this disclosure address the SC-LDPC code structure (specifically, termination) and how to realize it in a wireless communication standard. While some of these embodiments are geared towards WLAN systems, other embodiments have lower level details to cover adoption in other standards, such as mobile communication standards. Certain embodiments of the present disclosure propose a new decoder, referred to as a zigzag window decoder, capable of improving SC-LDPC code performance and reducing the number of iterations.
Embodiments of the present disclosure propose an SC-LDPC code scheme for adding SC-LDPC to a communication system. SC-LDPC codes have a high parallel factor that can achieve several gigabits per second (GB/s) with low power consumption. They have low granularity and extensible codeword length to enable high efficiency in dynamic radio environments. In addition, certain embodiments of the present disclosure propose a new decoding scheme, such as one configured for use by a new zigzag window decoder, that can achieve better performance than a sliding window decoder.
1 depicts an exemplary wireless network 100 in accordance with the present disclosure. The embodiment of the wireless network 100 shown in FIG. 1 is for illustration only. Other embodiments of the wireless network 100 may be used without departing from the scope of the present disclosure.
As shown in FIG. 1 , a wireless network 100 includes an eNodeB (eNB) 101 , an eNB 102 , and an eNB 103 . eNB 101 communicates with eNB 102 and eNB 103 . The eNB 101 also communicates with at least one internet protocol (IP) network 130, such as the Internet, a dedicated IP network, or other data network.
Depending on the network type, other well-known terms such as "base station" or "access point" may be used instead of "eNodeB" or "eNB". For convenience, the terms “eNodeB” and “eNB” are used in this patent document to denote network infrastructure components that provide wireless access to remote terminals. Also, depending on the type of network, other well-known terms such as "mobile station", "subscriber station", "remote terminal", "wireless terminal", or "user equipment" may also be used to refer to "user equipment" or "UE". can be used instead. For convenience, the term “user equipment” or “UE” in this patent document refers to whether a UE is a mobile device (such as a mobile phone or smartphone) or a fixed device (such as a desktop computer or vending machine). Whether considered as , it is used to indicate a remote wireless terminal wirelessly accessing an eNB.
The eNB 102 provides wireless broadband access to a network 130 to a first plurality of user equipment (UEs) within a coverage area 120 of the eNB 102 . The first plurality of UEs include UE 111 that may be located in a small business (SB), UE 112 that may be located in a large enterprise (E), and UE 113 that may be located in a WiFi hotspot (HS). , UE 114 that can be located in the first residence (residence, R), UE 115 that can be located in the second residence (residence, R), and mobile devices such as mobile phones, wireless laptops, or wireless PDAs (mobile devices, M) UE 116, which may be The eNB 103 provides wireless broadband access to the network 130 to a second plurality of UEs within a coverage area 125 of the eNB 103 . The second plurality of UEs include UEs 115 and UEs 116 . In some embodiments, one or more eNBs 101 - 103 may communicate with each other and with UEs 111 - 116 using 5G, LTE, LTE-A, WiMAX, or other evolved wireless communication technologies.
Dotted lines indicate approximate extents of coverage area 120 and coverage area 125, which are drawn approximately circular for illustration and description only. It should be clearly understood that coverage areas associated with eNBs, such as coverage area 120 and coverage area 125, may have different shapes, including irregular shapes, depending on the configuration of the eNBs and variations in the wireless environment related to natural and man-made obstacles. do.
As described in more detail below, one or more eNBs 101 to 103 are configured to encode data using zigzag windows and SC-LDPC codes as described in embodiments of the present disclosure. In certain embodiments, one or more eNBs 101 - 103 are configured to decode data using zigzag windows and SC-LDPC codes as described in embodiments of this disclosure. In certain embodiments, one or more UEs 111 - 116 are configured to encode data using zigzag windows and SC-LDPC codes as described in embodiments of this disclosure. In certain embodiments, one or more UEs 111 - 116 are configured to decode data using zigzag windows and SC-LDPC codes as described in embodiments of this disclosure.
Although FIG. 1 shows an example of a wireless network 100 , various changes may be made to FIG. 1 . For example, wireless network 100 may include any number of eNBs and any number of UEs in all suitable arrangements. In addition, eNB 101 may communicate directly with any number of UEs and provide wireless broadband access to network 130 to these UEs. Similarly, each of eNB 102 and eNB 103 can communicate directly with network 130 and provide direct wireless broadband access to network 130 for UEs. Additionally, eNB 101 , eNB 102 , and/or eNB 103 may provide access to other or additional external networks, such as an external telephone network or other types of data networks.
2A and 2B show exemplary wireless transmit and receive paths according to the present disclosure. In the description that follows, transmit path 200 may be described as being implemented in an eNB (such as eNB 102) and receive path 250 may be described as being implemented in a UE (such as UE 116). However, it will be appreciated that receive path 250 can be implemented in an eNB and transmit path 200 can be implemented in a UE. In certain embodiments, transmit path 200 is configured to encode data using zigzag windows and SC-LDPC codes as described in embodiments of this disclosure. In certain embodiments, receive path 250 is configured to decode data using zigzag windows and SC-LDPC codes as described in embodiments of this disclosure.
Transmit path 200 includes channel coding and modulation block 205, serial-to-parallel (S-to-P) block 210, size N inverse fast fourier transform (IFFT) block 215, parallel - includes a parallel-to-serial (P-to-S) block 220, an additional cyclic prefix block 255, and an up-converter (UC) 230. Receive path 250 includes a down-converter (DC) 255, a rejection cyclic prefix block 260, a serial-to-parallel (S-to-P) block 265, a fast fourier transform of size N transform (FFT) block 270, parallel-to-serial (P-to-S) block 275, and channel decoding and demodulation block 280.
On transmit path 200, channel coding and modulation block 205 receives a set of information bits, applies coding (such as low-density parity check (LDPC) coding), and generates a sequence of frequency domain modulation symbols. modulates the input bits (eg using quadrature phase shift keying (QPSK) or quadrature amplitude modulation (QAM)) to Serial-to-parallel conversion block 210 converts (such as demultiplexing) serial modulated symbols to parallel data to produce N parallel symbol streams, where N is the IFFT/FFT size used in eNB 102 and UE 116. . IFFT block 215 of size N performs IFFT operations on the N parallel symbol streams to generate time domain output signals. Parallel-to-serial conversion block 220 converts (such as multiplexing) the parallel time domain output symbols from IFFT block 215 of size N to produce a serial time domain signal. Add cyclic prefix block 225 inserts a cyclic prefix into the time domain signal. Upconverter 230 modulates (such as upconverts) the output of additional cyclic prefix block 225 to an RF frequency for transmission over a wireless channel. Additionally, the signal may be filtered at baseband prior to conversion to the RF frequency.
The transmitted RF signal from the eNB 102 arrives at the UE 116 after passing through the radio channel, and reverse operations to those at the eNB 102 are performed at the UE 116 . Downconverter 255 downconverts the received signal to baseband frequency, and remove cyclic prefix block 260 removes the cyclic prefix to produce a serial time domain baseband signal. Serial-to-parallel conversion block 265 converts the time domain baseband signals to parallel time domain signals. FFT block 270 of size N performs an FFT algorithm to generate N parallel frequency domain signals. Parallel-to-serial conversion block 275 converts the parallel frequency domain signals into a sequence of modulated data symbols. Channel decoding and demodulation block 280 demodulates and decodes the modulated symbols to recover the original input data stream.
Each of eNB 101 to eNB 103 can implement a transmit path 200 similar to a transmit step in downlink to UE 111 to UE 116, and a receive path 250 similar to a receive step in uplink from UE 111 to UE 116. can be implemented Similarly, each of UE 111 to UE 116 may implement a transmit path 200 for a transmit step in uplink to eNB 101 to eNB 103, and a receive path for a receive step in downlink from eNB 101 to eNB 103. 250 can be implemented.
Each of the components of FIGS. 2A and 2B may be implemented using only hardware or a combination of hardware and software/firmware. As a specific example, at least some of the components of FIGS. 2A and 2B may be implemented in software, while other components may be implemented by configurable hardware or a mixture of configurable hardware and software. For example, FFT block 270 and IFFT block 215 can be implemented as configurable software algorithms, where the value of size N can be modified depending on the implementation.
Also, although described using FFT and IFFT, this is for illustrative purposes only and should not be construed as limiting the scope of the present disclosure. Other types of transforms may be used, such as discrete fourier transform (DFT) and inverse discrete fourier transform (IDFT) functions. The value of variable N for DFT and IDFT functions can be any integer (such as 1, 2, 3, 4, etc.), and the value of variable N for FFT and IFFT functions is (1, 2, 4, 8, 16, etc.) like) can be any integer that is a power of 2.
2A and 2B show examples of wireless transmit and receive paths, various modifications may be made to FIGS. 2A and 2B. For example, various components in FIGS. 2A and 2B may be combined, further subdivided, or omitted, and additional components may be added according to specific needs. 2A and 2B are also intended to illustrate examples of the types of transmit and receive paths that may be used in a wireless network. Other suitable architectures may be used to support wireless communication in a wireless network.
3 shows an exemplary UE 116 in accordance with the present invention. The embodiment of the UE 116 shown in FIG. 3 is for illustrative purposes only, and the UEs 111 to 115 of FIG. 1 may have the same or similar configuration. However, UEs come in a wide variety of configurations, and FIG. 3 does not limit the scope of the present invention to a particular implementation of a UE.
The UE 116 includes antennas 305a through 305n, radio frequency (RF) transceivers 310a through 310n, transmit (TX) processing circuitry 315, a microphone 320, and receive (RX) processing circuitry 325. TX processing circuit 315 and RX processing circuit 325 are respectively RF transceiver 310a to RF transceiver 310n respectively, for example, RF transceiver 310a, RF transceiver 310b to Nth RF coupled to antenna 305a, antenna 305b and Nth antenna 305n, respectively coupled to the transceiver 310n. In certain embodiments, UE 116 includes one antenna 305a and one RF transceiver 310a. In addition, the UE 116 includes a speaker 330, a main processor 340, an input/output (I/O) interface (IF) 345, a keypad 350, a display 355, and a memory 360. The memory 360 includes a basic operating system (OS) program 361 and one or more applications 362 .
RF transceivers 310a through 310n receive an input RF signal transmitted by an eNB or AP of network 100 from respective antennas 305a through 305n. In certain embodiments, each RF transceiver 310a through 310n and each antenna 305a through 305n is configured for a particular frequency band or technology type. For example, a first RF transceiver 310a and antenna 305a may be configured to communicate via short-range wireless communication such as BLUETOOTH®, while a second RF transceiver 310b and antenna 305b may be configured to communicate via IEEE 802.11 communication such as Wi-Fi. The other RF transceiver 310n and antenna 305n may be configured to communicate via cellular communication such as 3G, 4G, 5G, LTE, LTE-A, or WiMAX. In certain embodiments, one or more RF transceivers 310a through 310n and each antenna 305a through 305n are configured for a particular frequency band or the same technology type. RF transceivers 310a through 310n downconvert the input RF signal to generate an intermediate frequency (IF) or baseband signal. The IF or baseband signal is sent to RF processing circuitry 325 which generates a processed baseband signal by filtering, decoding, and/or digitizing the baseband or IF signal. The RF processing circuitry 325 sends the processed baseband signal to the main processor 340 for further processing (such as for web browsing data) or to the speaker 330 (such as for voice data).
TX processing circuitry 315 receives analog or digital voice data from microphone 320, or other output baseband data (such as web data, e-mail, or interactive video game data) from main processor 340. TX processing circuitry 315 encodes, multiplexes, and/or digitizes the output baseband data to generate a processed baseband or IF signal. The RF transceivers 310a to 310n receive the output-processed baseband or IF signals from the TX processing circuit 315 and upconvert the baseband or IF signals to RF signals transmitted through one or more antennas 305a to 305n.
The main processor 340 may include one or more processors or other processing units, and may execute a basic OS program 361 stored in the memory 360 to control the overall operation of the UE 116 . For example, main processor 340 may control reception of forward channel signals and transmission of reverse channel signals by RF transceivers 310a through 310n, RX processing circuitry 325 and TX processing circuitry 315 according to well-known principles. In some embodiments, main processor 340 includes at least one microprocessor or microcontroller. The main processor 340 includes processing circuitry configured to encode or decode data information, including a sliding window encoder with a pause function, a sliding window decoder with a pause function, a zigzag window encoder, a zigzag window decoder, or a combination thereof.
In addition, the main processor 340 may execute other processes and programs residing in the memory 360, such as operations for using zigzag windows and SC-LDPC codes as described in embodiments of the present disclosure. The main processor 340 can move data into or out of the memory 360 as needed by the executing process. In some embodiments, main processor 340 is configured to execute application 362 in response to signals received from workers or eNBs, or based on OS program 361 . The main processor 340 is also coupled with an I/O interface 345 that provides the UE 116 with the ability to connect to other devices such as laptop computers and handheld computers. The I/O interface 345 is a communication path between the main processor 340 and these accessory devices.
Also, the main processor 340 is coupled to the keypad 350 and display unit 355. A user of UE 116 can use keypad 350 to enter data into UE 116 . Display 355 may be a liquid crystal display or other display capable of rendering text or at least limited graphics, for example from web sites, or a combination thereof.
Memory 360 is coupled to main processor 340 . A portion of the memory 360 may include random access memory (RAM), and another portion of the memory 360 may include flash memory or other read-only memory (ROM).
Although FIG. 3 shows an example of UE 116 , various modifications may be made to FIG. 3 . For example, various components of FIG. 3 may be combined, further subdivided, or omitted, and additional components may be added according to specific needs. As a specific example, main processor 340 may be divided into multiple processors, such as one or more central processing units (CPUs) and one or more graphics processing units (GPUs). Further, although FIG. 3 shows UE 116 configured as a mobile phone or smartphone, UEs may be configured to operate as other types of mobile or stationary devices.
4 depicts an exemplary eNB 102 in accordance with the present invention. The embodiment of eNB 102 shown in FIG. 4 is for illustrative purposes only, and other eNBs in FIG. 1 may have the same or similar configuration. However, eNBs come in a wide variety of configurations, and FIG. 4 does not limit the scope of the present invention to a particular implementation of an eNB.
The eNB 102 includes a plurality of antennas 405a through 405n, a plurality of RF transceivers 410a through 410n, transmit (TX) processing circuitry 415, and receive (RX) processing circuitry 420. The eNB 102 also includes a controller/processor 425 , memory 430 , and a backhaul or network interface 435 .
RF transceivers 410a through 410n receive input RF signals, such as signals transmitted by UEs or other eNBs, from antennas 405a through 405n. RF transceivers 410a through 410n downconvert the input RF signals to generate IF or baseband signals. The IF or baseband signals are sent to RF processing circuitry 420 which generates processed baseband signals by filtering, decoding, and/or digitizing the baseband or IF signals. RF processing circuitry 420 sends the processed baseband signals to controller/processor 425 for further processing.
TX processing circuitry 415 receives analog or digital data (such as voice data, web data, e-mail, or interactive video game data) from controller/processor 425. TX processing circuitry 415 encodes, multiplexes, and/or digitizes the output baseband data to generate processed baseband or IF signals. The RF transceivers 410a to 410n receive the output-processed baseband or IF signals from the TX processing circuit 415 and upconvert the baseband or IF signals to RF signals transmitted through the antennas 405a to 405n.
The controller/processor 425 may include one or more processors or other processing devices that control the overall operation of the eNB 102 . For example, controller/processor 425 may control the reception of forward channel signals and the transmission of reverse channel signals by RF transceivers 410a through 410n, RX processing circuitry 420, and TX processing circuitry 415 according to well-known principles. The controller/processor 425 may also support additional functions such as using zigzag windows and SC-LDPC codes as described in embodiments of this disclosure. Any of a wide variety of different functions may be supported in the eNB 102 by the controller/processor 425 . In some embodiments, controller/processor 425 includes at least one microprocessor or microcontroller. The controller/processor 425 includes processing circuitry configured to encode or decode data information, including a sliding window encoder with a pause function, a sliding window decoder with a pause function, a zigzag window encoder, a zigzag window decoder, or a combination thereof. .
Additionally, the controller/processor 425 may execute other processes and programs residing in memory 430, such as a basic OS. Controller/processor 425 can move data into or out of memory 430 as needed by the executing process.
A controller/processor 425 is also coupled to a backhaul or network interface 435. The backhaul or network interface 435 allows the eNB 102 to communicate with other devices or systems over a network or via a backhaul connection. Interface 435 may support communication over any suitable wired or wireless connection(s). For example, if eNB 102 is implemented as part of a cellular communication system (such as supporting 5G, LTE, or LTE-A), interface 435 allows eNB 102 to communicate with other eNBs via wired or wireless backhoe connections. can make it possible When eNB 102 is implemented as an access point, interface 435 can enable eNB 102 to communicate over a wired or wireless connection to a larger network (such as the Internet) or over a wired or wireless local area network. Interface 435 includes any suitable structure that supports communication over a wired or wireless connection, such as an Ethernet or RF transceiver.
A memory 430 is coupled to the controller/processor 425. Part of memory 430 may include RAM, and another part of memory 430 may include flash memory or other ROM.
As described in more detail below, the transmit and receive paths of the eNB 102 (implemented using RF transceivers 410a through 410n, TX processing circuitry 415, and/or RX processing circuitry 420) are frequency division duplexing (FDD) cells and TDD (time division duplexing) supports communication with a set of cells.
4 shows an example of an eNB 102 , various modifications may be made to FIG. 4 . For example, eNB 102 may include any number of each component shown in FIG. 4 . As a specific example, an access point may include multiple interfaces 435 and a controller/processor 425 may support routing functions to route data between different network addresses. As another particular example, while shown as including a single instance of TX processing circuitry 415 and a single instance of RX processing circuitry 420 , eNB 102 may include multiple instances of each (such as one per RF transceiver).
LDPC codes have recently received a lot of attention. This is due to their ability to achieve performance close to the Shannon limit, their ability to design codes that facilitate high parallelism in hardware, and their high data rate support. The most commonly deployed form of LDPC codes are block LDPC codes. However, in highly dynamic wireless communication systems, where channel conditions and per-user data allocation change continuously, block LDPC codes offer rather limited flexibility.
Using block LDPC codes requires allocating data in multiples of the code's block length to avoid unnecessary padding, which reduces link efficiency. Among wireless standards that have adopted LDPC as part of their specifications, the following three approaches can be cited to address the granularity limitation of block LDPC codes: (1) Codes with one very short block length, such as IEEE 802.11ad. In use, the smaller the block length, the finer the granularity of the code, but the block LDPC codes with short block length lack performance, which also reduces the link efficiency; 2) the use of block LDPC codes with multiple block lengths like IEEE 802.11n, this approach mitigates performance degradation instead of implementing a more complex decoder due to the requirement to support multiple codes; and 3) using turbo codes like 3GPP. The circular structure of turbo codes can provide scalable code length with high granularity without increasing the complexity of the decoder. However, turbo codes do not provide sufficient parallelism, which in turn limits their ability to achieve multi-gigabits per second (Gb/s) throughput.
Spatially-coupled low-density parity-check (SC-LDPC) codes are new capacity achieving codes. SC-LDPC codes combine the advantages of both turbo codes and LDPC block codes. SC-LDPC codes form a special kind of LDPC codes with a relatively small syndrome former memory. Thus, SC-LDPC codes have parity check matrices with a circular structure. This structure allows for scalable code length with high granularity compared to other block LDPC codes. In addition, since SC-LDPC codes inherit the high parallel processing capability of LDPC codes, they can support a throughput of several gigabytes.
It is possible to decode terminated SC-LDPC codes as any other block LDPC code, but doing so negates the fine granularity and flexible length advantages of SC-LDPC codes. Also, the latency and hardware complexity of this approach makes it impractical for SC-LDPC codes with very large block lengths. Due to the circular structure of the SC-LDPC code Patrick's check matrix, this decoder also requires a large number of iterations before it converges. Alternatively, SC-LDPC codes can be decoded using a sliding window decoder. This approach appears to alleviate most of the full block decoder problems. However, there are still some important performance issues that need to be addressed.
First, the average number of iterations of the current SC-LDPC decoder is high. For example, if we run a sliding window decoder on an SC-LDPC code with a window size of 15, a fixed 10 iterations per window is a variable node. 150 repetitions per VN). To increase the throughput, it is necessary to reduce the average number of iterations per VN in the sliding window decoder. In addition, it is necessary to use a simple early stopping rule to end decoding of the current window and start decoding of the next window. An early stopping rule to estimate the bit error rate (BER) within the decoding window based on the soft bit indicator for VN was proposed in REF-4. However, evaluation of these rules requires a lookup table and the addition of N _t real numbers, where N _t is the number of target variable nodes (VN) within the decoding window. Instead, embodiments of the present disclosure propose and evaluate a simple stopping rule based on partial syndrome computation (see Section III).
Second, the full block decoder uses both ends of the SC-LDPC code to improve the decoding threshold, whereas the sliding window decoder uses only the start end. Thus, full block decoders outperform sliding window decoders. To further reduce the gap between the two decoders, embodiments of the present disclosure introduce a zigzag window decoder. In addition, embodiments of the present disclosure show that a zigzag window decoder requires fewer average number of iterations per VN than a sliding window decoder.
Third, in order to adapt to a dynamic radio channel, a coding scheme of a radio system must support a plurality of code rates. Embodiments of the present disclosure solve the problem of designing an SC-LDPC code family that supports multiple code rates. In particular, the two approaches are compared in terms of BER performance and decoding complexity. The first approach uses code puncturing and the second approach uses code shortening. The results show that the SC-LDPC code family based on shortening converges faster and has better error performance than the SC-LDPC code family based on puncturing.
SC-LDPC codes: review and examples
5A, 5B, 5C, and 5D show exemplary protograph-based SC-LDPC code structures. The embodiments of the SC-LDPC code structures shown in FIGS. 5A to 5D are for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
The protograph-based SC-LDPC code starts with Protograph 500, a Tanner graph with a relatively small number of VN 505 and check node (CN) 510. An example of a regular (3,6) LDPC code protograph is shown in FIG. 5A. As shown in Fig. 5b, (3, 6, L) SC-LDPC code ensembles are generated using L copies of the protograph. As shown in FIG. 5C, protographs 500 are not interconnected with cycles having VN coupled to each CN. Rather, as shown in FIG. 5D , protographs 500 are coupled to chain 520 . Each protograph 500 in chain 520 is coupled to at most m copies of the protograph to its left and at most m copies of the protograph to its right, where m is called the syndrome former memory, or simply the memory of code. In contrast to protograph-based block LDPC codes with multiple step lifting, SC-LDPC codes have a small code memory, i.e., m<<L, which means that the parity check matrix of SC-LDPC codes has a circular structure. indicates that It should be noted that the CNs 510 in the first and last m copies of the protograph have lower order than their corresponding CNs 510 in the other copies of the protograph. This means stronger CNs at the beginning and end of the SC-LDPC combined chain, which improves the iterative decoding threshold of SC-LDPC codes at the cost of a small reduction in code rate. The first m copies of the protograph in the combined chain are called start-to-end 525 and the last m copies of the protograph are called end-to-end 530, and these are shown in shaded colors in FIG. 5D.
6 shows an example of a (3, 6, 720) protograph-based SC-LDPC code with a lifting factor Z = 112 according to the present disclosure. The embodiment of the protograph-based SC-LDPC code shown in FIG. 6 is for illustrative purposes only. Other embodiments may be used without departing from the scope of the present disclosure.
For example, (3, 6, 720) SC-LDPC code 600 is designed using the protograph shown in FIG. 5A. First, a code ensemble is constructed by combining chains 520 of 720 protograph copies as shown in FIG. 5D, and then a code is constructed by lifting the combined chains having a lifting factor Z=112. A parity check matrix 605 for the designed SC-LDPC code 600 is shown in FIG. 6 . The number x in the parity check matrix 605 denotes a ZxZ identity matrix with x positions shifted cyclically to the right. Empty entries of the parity check matrix 605 are a ZxZ matrix in which all elements are zero. Each of the two columns of the parity check matrix is marked with a number, which indicates the protograph section to which these 2Z VNs belong. In each protograph section, the first Z VNs are information bits, and the second Z VNs are parity bits. The designed SC-LDPC code 600 is a quasi-cyclic (QC) SC-LDPC code with a period of 3. The permutation matrices in this parity check matrix were chosen to maximize the gus of the first 9 protograph sections. Since the period of this code is 3, the gus of the whole code is the same as the gus of the first 9 protograph sections.
Typically, SC-LDPC code parity check matrices have irregularities at the beginning and end resulting from assumptions that entries before the start are 0 and entries after the end are 0. The parity check matrix 600 includes an initial start end 610 and an end end 615 . The SC-LDPC code 600 will be used in generating performance results in the next two sections.
7 illustrates a sliding window decoder 700 according to the present disclosure. The embodiment of the sliding window decoder 700 shown in FIG. 7 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
SC-LDPC code 600 can be decoded like a block LDPC code, but if SC-LDPC codewords of very large length are used, it is generally impractical to decode SC-LDPC code 600 like a block LDPC code. Also, using a block decoder eliminates the fine granularity and flexible length advantages of SC-LDPC codes. Certain systems use a sliding window decoder to decode SC-LDPC codes. A sliding window decoder is shown in FIG. 7 . The decoder processes VNs in a window 705 defined by the number W of protograph sections, e.g. size W 710. The decoder runs the maximum number of iterations or stops when the early termination criterion is met. After that, the decoder determines the value of the first protograph section (or the first S sections), then outputs the first protograph section (or the first S sections) and the protograph section after the last section in the decoding window. (or S sections) to advance the decoding window to step S715.
In the sliding window decoder 700, a decoding window 705 of size W 710 moves along the protograph sections of the SC-LDPC code 600. Position p of the decoding window 705 represents the corresponding protograph section of the window 705. The sliding window decoder 700 performs an iterative decoding algorithm when the decoding window 705 is at the first position, that is, when P=1, and then when the decoding window 705 is at the second position, that is, when P=2. An iterative decoding algorithm is performed, and then an iterative decoding algorithm is performed when the decoding window 705 is in the third position, that is, when P=3, and so forth.
In certain systems, decoding windows either stop after a fixed number of iterations (with no stopping rule), or they use an estimated bit error rate metric that requires the calculation of soft bit error indicators for VNs. To reduce the average number of iterations (to reduce decoding power consumption), an early stopping rule should be implemented. However, the stopping rule in other systems is complex to compute.
The use of a predetermined number of iterations is not very efficient, but should be set for worst case channel conditions. Instead, a real-time early stopping rule based on estimating BER has been proposed using the log-likelihood-ratio (LLR) of target VNs within the decoding window. When the estimated BER is less than the BER of the threshold or the maximum number of iterations is reached, the decoding window 705 moves forward. The BER is estimated by averaging the soft bit error indicators of target VNs, where the soft bit error indicator for a VN with LLR Γ is 1/(1+exp(|Γ|)). However, evaluation of the soft bit error indicator requires a lookup table, and calculating the average requires N _t , eg, N _t =2Z·s real additions after each iteration.
8 illustrates a sliding window decoder 800 with an early stopping rule according to the present disclosure. The embodiment of the sliding window decoder 800 shown in FIG. 8 is for illustration only. The sliding window decoder 800 can be the same as the sliding window decoder 700, but also includes a stopping rule. Other embodiments may be used without departing from the scope of the present disclosure. The sliding window decoder 800 includes a decoding window 705 of size W=10 and a partial syndrome checking window 810 of size W _s =5.
Embodiments of the present disclosure use a simple stopping rule based on examining only some of the syndromes of the code related to only a few CNs within the decoding window. Here, W _s is defined as the partial syndrome test window width 810 (in the number of protograph sections) as shown in FIG. 8 . Suggested stopping rule: if the syndrome check is passed or the maximum number of iterations is reached, the syndrome is checked for the CNs in W _s , then the decision for the VNs in S is output, after which the position of the sliding window is updated
Embodiments of this disclosure suggest using a simple stopping rule based on checking the syndromes of only a few CNs within the decoding window 705. In these embodiments, a partial syndrome check window 810 of size W _s is defined as the first W _s protograph sections in the decoding window 705 . In the sliding window decoder 800, a decoding window 705 of size W moves along the protograph sections of the SC-LDPC code 600. The position of the decoding window, _Pi denotes the first protograph section in the window. The updated sliding window decoder 800 is:
For all window locations p _i =p _i-1 +s, where s is the window step size, i=1,… ,L and p ₁ =1,
1) For the maximum number of iterations I _w ,
- Update all VNs and CNs in the decoding window 805 according to the iterative LDPC code decoding algorithm.
- Calculate syndromes for CNs within the partial syndrome check window. When all CNs are satisfied or the maximum number of iterations is reached, go to the next step. Otherwise, continue with the next iteration.
2) Determine the values of the target VNs. The VNs in the first S sections of the decoding window are called target VNs.
Within the decoding window 705, any one of the iterative decoding algorithms used for LDPC codes such as sum-product, min-sum, dual-quantization domain, etc. can be used It should also be noted that updating the CNs within the decoding window 705 requires access to external information about VNs outside the decoding window. In particular, the VNs in the m protograph sections immediately before the decoding window 705. These VNs transmit their extrinsic information based on the last update from the previous window. The maximum number of iterations can be selected to achieve a targeted error probability within the window. This can be done using density evolution techniques.
Figure 9 shows such a stop using a sliding window decoder 800 with different partial syndrome check window sizes W _s =5, W _s =4, and W _s =3, W = 15, s = 1 and I _w =90. Shows the BER and frame error rate (FER) performance of the rule. Also, the results were compared with those using a full-block decoder with up to 1000 iterations. It is noteworthy that the FER performance of the sliding window decoder starts to degrade for W _s < 5. Results for W _s >5 appear to have similar performance to W _s =5. It should be noted that W _s for this code must be greater than or equal to 3, since CNs in window 705 are directly connected to target VNs.
Zigzag Window Decoder
10A and 10B show zigzag window decoder states according to the present disclosure. The embodiment of the zigzag window decoder states is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
In the sliding window decoder 800, the window moves in one direction from the start end 610 to the end end 615. This allows information to flow between decoding windows 705 in only one direction, resulting in a slight performance degradation compared to a full block decoder. In addition, simulations using the sliding window decoder 800 show that several successive decoding windows also diverge when the decoding window does not converge, i.e., the maximum number of iterations is reached, and the CNs in the partial syndrome check window 805 are not satisfied. After that, sliding window decoding 800 showed that it would converge back to the correct decision. This is shown in Fig. 10a, where the circles represent the state of the decoding windows as the sliding window decoder 800 moves along the protograph sections of the SC-LDPC code 600. A white circle 1005 indicates that the decoding window has converged on the correct decision, and a gray circle 1010 indicates that the decoding window has not converged. Here, divergence is defined as a set of consecutive protograph sections that fail to converge, and divergence size is defined as the number of protograph sections within divergence. For example, the divergence in FIG. 10A has a magnitude of 4.
Certain embodiments provide a new decoder called a zigzag window decoder. In the zigzag window decoder, the decoding window has two directions as shown in Figs. 10c, 10d and 10e.
Forward: When the early stopping rule is met or the maximum number of iterations is reached, the decoding window advances one protograph section (or SW sections) to the right, pushing information from left to right. If the early stopping rule is met, the targeted protograph section(s) are set to pass decoding. Otherwise, it is set to decoding failure. Consecutive protograph sections that fail to decode are called divergence.
Reverse direction: At the end of divergence, the decoding window changes its direction, pushing information from right to left. This direction continues until the decoding window reaches the beginning of the divergence, after which it turns forward.
In a zigzag window decoder, the decoding window reverses its direction to correct the divergence by pushing the information at the end of the divergence back into the divergence from the correct state at the end of the divergence. Figure 10b shows the direction of the zigzag window decoder. The decoding window has two directions, a forward direction in which the decoding window moves from the start end to the end end (right), and a reverse direction in which the decoding window moves from the end end to the start end (left). The zigzag window decoder process is as follows:
1) Set window position p = 1, window_direction = forward, and previous_window_converged = true.
2) For the maximum number of iterations I _w ,
- Update all VNs and CNs in the decoding window according to the iterative LDPC code decoding algorithm.
- Calculate syndromes for CNs within the partial syndrome check window.
- If all CNs are met, set window_converged = true, and go to step 3.
- When the maximum number of iterations is reached, set window_converged = false and go to step 3.
3) Check the decoding window direction.
- if window_direction = forward direction,
- If window_converged = false and previous_window_converged = true,
- divergence_start_position = p.
- If window_converged = true, previous_window_converged = false, and the number of Z rounds is less than the maximum number of Z rounds,
- divergence_end_position = p.
- window_direction = reverse.
- p=p-2s.
- If window_converged = true,
- Determine the value of the target VNs.
- previous_window_converged = window_converged.
- p=p+s.
- If window_direction = reverse,
(a) If p > divergence_start_position,
-p=ps.
(b) else
- p=p+s.
- window_direction = forward direction.
- previous_window_converged = True.
- If p<L, go to step 2, otherwise stop.
In the proposed zigzag window decoder, a Z round is defined as a combination of forward, backward, and then forward windows when divergence occurs. Alternatively, Z rounds may be referred to as 'window iteration', 'window round', 'window reversal', and the like. In certain embodiments, if some protograph sections in divergence do not converge in the second forward window of Z round, the second Z round overlaps within the first Z round. An example of this concept is shown in FIGS. 11A and 11B . 11A shows one Z round 1105 with forward 1115, backward 1120, then forward 1125 windows when divergence occurs. 11B shows one Z round 1110 with a forward 1115, backward 1120, second forward 1125, second backward 1130 and then third forward 1135 window when divergence occurs. Similarly, multiple Z rounds may be performed. However, to prevent unlimited bouncing within a set of VNs in a low signal to noise ratio (SNR) region, the maximum number of Z rounds must be specified.
Actual implementations of the zigzag window decoder support a predetermined maximum divergence size called Z window 1015. Z window 1015 is the maximum divergence size supported. In certain embodiments, implementation memory is proportional to W+Z _w +m. If divergence size>Z window, the zigzag window decoder ends codeword decoding and requests retransmission.
12A and 12B show the performance of each zigzag window decoder according to the present disclosure. Fig. 12a shows the performance of the zigzag window decoder for one Z round, Z _R =1, and Fig. 12b shows the performance of the zigzag window decoder for two Z rounds, Z _R =2. The capabilities shown in FIGS. 12A and 12B are for illustration only. Other embodiments and data may be used without departing from the scope of the present disclosure.
12a and 12b show the performance of the zigzag window decoder for different maximum number of iterations I _w and different maximum number of Z rounds Z _R . The simulation is performed using binary phase shift keying (BPSK) modulation over an additive white gaussian noise (AWGN) channel, and the decoder used within the decoding window is min-sum scaled with flood scheduling. A zigzag window decoder with Z _R =0 is a sliding window decoder. It should be noted that the zigzag window decoder allows information to flow backwards at the end of the divergence. Accordingly, the BER/FER performance of the zigzag window decoder is better than that of the sliding window decoder. In addition, the zigzag window decoder allows the use of a smaller maximum number of iterations compared to the sliding window decoder without degrading the BER performance. It should be noted that the zigzag window decoder with Z _R =1 and I _W =5 is 0.25 decibel (dB) better than the sliding window decoder with I _W =90. 12b also shows that the zigzag window decoder with Z _R =1 and I _W =5 requires fewer average number of iterations per VN than the sliding window decoder with I _w =90. Finally, Figures 12a and 12b show that increasing the number of Z rounds beyond Z _R =1 reduces returns.
The results in FIGS. 12A and 12B assume that there is no limit on divergence magnitude. However, a feasible implementation of a zigzag window decoder must specify a maximum divergence size. The memory required to implement the zigzag window decoder increases as you increase the maximum divergence size supported. The maximum divergence size is called the Z window size, Z _W . The implementation memory required is proportional to W+Z _W +m.
In certain embodiments, any of the decoding algorithms used in the process of decoding the block LDPC codes may be used to update the VNs and CNs within the decoding window. Some of the commonly used decoders are product-sum, scaled min-sum (SMS), and dual-quantization domain (DQD). Algorithms within the decoding window may perform flooding or layered scheduling. Also, processing of CNs and VNs within a window can be performed in parallel or serially.
Recall that SC-LDPC codes have a finite memory of codes, and are defined as follows: the value of bits in an arbitrarily given protograph section is the value of bits in up to m protograph sections before or after that protograph section. Depending on , the SC-LDPC code has memory m. For SC-LDPC codes, m is typically a small number, eg SC-LDPC code 600 memory m=2 in FIG.
This property of SC-LDPC codes can be used to increase the parallelism factor of a layered decoding machine working in window W of SC-LDPC. In general, the parallelism factor of LDPC codes is Z, but it should be noted that the structure of the SC-LDPC code 600 allows for parallelism factors higher than Z.
In certain embodiments, an SC-LDPC code in memory m is constructed using a ZxZ circulant matrix and decoded with a decoding window of size W in layered scheduling. It is possible to process Z*floor(W/(m+1)) CNs without parallel contention (two CNs do not need to access the same VN memory at the same time).
As an example, SC-LDPC code 600 using a zigzag window decoder (or sliding window decoder) with W = 15 requires 15 layers per iteration in a typical layered decoder (each layer has Z = 112 CNs). process). However, according to the above embodiment, it is possible to end repetition in three layers. In the first layer, 112*5 CNs in rows 1, 4, 7, 10, and 13 of the decoding window are processed. In the second layer, 112*5 CNs in rows 2, 5, 8, 11, and 14 of the decoding window are processed. In the third layer, 112*5 CNs of rows 3, 6, 9, 12, and 15 of the decoding window are processed.
13 shows the probability of correcting the divergence of protograph sections of size x with one Z round of a zigzag window decoder according to the present disclosure. 14 shows the FER (dotted line) and BER (solid line) performance of a zigzag window decoder with different Z window sizes according to the present disclosure. The examples shown in FIGS. 13 and 14 are for illustrative purposes only. Other embodiments and data may be used without departing from the scope of the present disclosure.
Figure 13 shows that the probability of correcting divergence decreases with its magnitude. 14 shows the performance of the zigzag window decoder for different Z window sizes (Z _w =5, Z _w =10, Z _w =15, Z _w =20, and infinity). Results show that increasing Z window size improves performance, but requires more implementation memory. Future work is needed to optimize the choice of Zw _{and Iw} . For example, it is possible to decrease Z _w and increase I _w to maintain performance.
In certain embodiments, the zigzag window decoder includes a codeword failure detection rule. A zigzag window decoder with a finite Z window size Z _w observing a divergence of magnitude greater than Z _w is used as an early indication of block decoding failure. In this case, the zigzag window decoder can stop decoding the remainder of the SC-LDPC codeword, and then the receiver can request retransmission of the SC-LDPC codeword from the transmitter. This early codeword failure detection rule reduces the average number of iterations, especially at low SNRs, e.g., see Fig. 15, which reduces the power consumption of the decoder. In addition, the early codeword failure detection rule allows the receiver to quickly request retransmission through automatic repeat request (ARQ) or hybrid ARQ (HARQ), which reduces the latency of feedback error correction schemes. Decrease.
SC-LDPC code design based on rate-1/2 protograph:
16 illustrates a (3,6) protograph-based SC-LDPC code according to the present disclosure. The embodiment of the SC-LDPC code 1600 based on the (3,6) protograph shown in FIG. 16 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
Embodiments of the present disclosure are described with reference to SC-LDPC code 1600, which may be the same as or similar to SC-LDPC code 600 of FIG. 6 with “ZZ” values instead of blanks for all zero matrices. SC-LDPC code 1600 or SC-LDPC code 600 are used as examples throughout this invention. However, embodiments of the present disclosure are not limited to this example and may be applied to all SC-LDPC codes.
SC-LDPC code 1600 is constructed from multiple copies of the (3,6) regular protograph. The lifting factor is Z = 112, and the matrix of FIG. 16 shows IDs (identifiers) for cyclic permutation matrices constituting the SC-LDPC code 1600. In the example shown in FIG. 16, A(1), A(2),... , and A(18) have values of 0, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 3, 6, 14, 12, 28, 21 and 39, respectively. It should be noted that the cyclic permutation matrix with ID 0 is a ZxZ identity matrix. In addition, the cyclic permutation matrix with ID i is a ZxZ identity matrix in which the position of i is shifted to the right periodically. Also, in the example shown in Fig. 16, ZZ denotes a ZxZ matrix in which all elements are 0. Rows of this matrix correspond to check nodes (CN), and columns correspond to variable nodes (VN).
Each of the two columns of cyclic permutations is marked with a number, which indicates the protograph section to which these 2Z VNs belong. In each protograph section, the VNs of the first Z represent information bits, and the VNs of the second Z represent parity bits. It is also possible to have the VNs of the first Z representing the parity bits and the VNs of the second Z representing the information bits. Figure 16 shows 720 protograph sections, but the length of this SC-LDPC code 1600 may vary depending on the amount of information bits available and need to be encoded in one codeword. In general, the length of a codeword (CW) is ceil (#/Z of information bits)*Z/R, where R is the code rate (R = 1/2 in this example). It is important to note the small granularity of these codes (granularity = Z information bits) and CW length flexibility, which makes protograph-based SC-LDPC codes favorable for adoption in wireless communication standardization. Protograph-based SC-LDPC codes have CW length flexibility and small granularity of spiral/turbo codes, and protograph-based SC-LDPC codes have a high parallelization factor of LDPC codes required in high throughput systems.
Also, it should be noted that only 18 cyclic permutations are used to construct SC-LDPC code 1600 that repeats as the CW length increases. For example, cyclic permutations used in the protograph of section 1 1605 are reused in protograph section 4 1620, section 7 1635, section 10, etc., cyclic permutations used in the protograph of section 2 1610 are re-used in protograph section 5 1625, Protograph sections reused in section 8 1640, section 11, etc., used in protograph section 3 1615, are used in section 6 1630, section 9 1645, section 12, etc.
Puncturing the designed rate-1/2 SC-LDPC to get higher rates:
17 shows a rate-1/2 protograph based SC-LDPC code punctured at rate-3/4 using a puncturing pattern according to the present disclosure. The embodiment of the SC-LDPC code 1700 shown in FIG. 17 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
Protograph based codes can be punctured to obtain codes with higher rates. For example, SC-LDPC code 1600 has rate-1/2, but SC-LDPC code 1600 has a puncturing pattern [1, 0; 1, 1] at rate-2/3, puncturing pattern [1, 0, 1; 1, 1, 0] at a rate-3/4, or the puncturing pattern [1, 0, 1, 0, 1; 1, 1, 0, 1, 0] can be punctured at rate-5/6. These patterns look similar to those commonly used for puncturing round codes, but here the puncturing pattern is applied to protograph sections. For example, the puncturing pattern [1, 0, 1; 1, 1, 0] applies to every three consecutive protograph sections of SC-LDPC code 1600. The values before the semicolon indicate whether to transmit or puncture the Z information bits of each protograph section. Values after the semicolon indicate whether to transmit ('1' value) or puncture ('0' value) Z parity bits of each section.
End of protograph based SC-LDPC codes:
In general, the SC-LDPC code gain for a block LDPC code comes from the termination of the SC-LDPC code. This termination is typically indicated by low-order CNs at the edges of the graph of the code. For example, in the SC-LDPC code 1600 of FIG. 16 , all CNs have degree 6, except for the CNs of protograph section 1, protograph section 2, protograph section 721 and protograph section 722 (sections 1 and 722). CNs of section 722 have degree 2, and CNs of protograph section 2 and protograph section 721 have degree 4). From another point of view, SC-LDPC code 1600 of FIG. 16 can be seen as sections from an infinitely long code, but protograph section 0, protograph section -1, protograph section -2, . . . and protograph section 721, protograph section 722, protograph section 723, . . . The information and parity bits in have a value of 0.
In certain embodiments, an SC-LDPC code such as SC-LDPC code 1600 can be viewed as a section from an infinitely long SC-LDPC code, but with a protograph section before the beginning ending protograph sections and after the ending ending protograph sections. The information and parity bits in s are either fixed (reliably know the pattern). For example, in SC-LDPC code 1600, protograph section 0, protograph section -1, protograph section -2,… and protograph section 721, protograph section 722, protograph section 723, . . . The bits in are fixed and have known values. It should be noted that the codewords of the SC-LDPC code depend on the fixed pattern used. Changing these fixed values changes the codeword of the code (changes the code).
In certain embodiments, the SC-LDPC codeword can be changed by changing the end bits of the divider protograph sections. These bits can be encrypted and transmitted over a secure link to a receiver. In certain embodiments, these bits are used to initialize the SC-LDPC decoder so that it can decode the received SC-LDPC codeword.
SC-LDPC codes have a finite memory of codes (i.e. syndrome former memory) defined as It has a memory m if it depends on the values of the bits of the protograph section. In the SC-LDPC code 1600 of FIG. 16, the code's memory m=2.
18 shows an infinitely long SC-LDPC code divided into several block LDPC codes using divider protograph sections according to the present disclosure. The embodiment of the divided SC-LDPC code 1800 shown in FIG. 18 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
In certain embodiments, an SC-LDPC code with memory m is seen as a section from an infinitely long SC-LDPC code, but the information in m protograph sections before the beginning ending protograph sections and after the ending ending protograph sections and the parity bits have a fixed or positively known pattern. For example, in SC-LDPC code 1600 of FIG. 16, the bits in protograph section 0, protograph section -1, protograph section 721, and protograph section 722 have fixed and known values. This is true regardless of the value of the bits in the protograph sections before -1 and after 722. Any m consecutive protograph sections with known bit values are referred to as divider protograph sections 1805. It should be noted that the protograph sections of the SC-LDPC code between the two divider protograph sections 1805 form the block LDPC code 1810. Unlike typical block LDPC codes, the split SC-LDPC code 1800 can be decoded using an SC-LDPC decoder in conjunction with the protograph sections before and after the divider protograph sections 1805. It should be noted that in the example shown in FIG. 18 , the lengths of the LDPC blocks 1810 need not be the same.
The use of a value of '0' (or a known fixed pattern) in the divider protograph sections 1805 reduces the rate of the code.
In certain embodiments, instead of using a known fixed pattern within the divider protograph sections, divider protograph section 1805 may use some method to convey parity bits and information that can be checked for correctness. As an example, transmitted packets typically undergo a cyclic redundancy check (CRC) to check packet correctness. If the bits in m contiguous protograph sections that are part of the CRC codeword pass the CRC check, then these bits can be treated as a known fixed pattern of bits, namely divider protograph sections 1805.
19 shows a very long SC-LDPC code split into several block LDPC codes using unequal error protection according to the present disclosure. The embodiment of the divided SC-LDPC code 1900 shown in FIG. 19 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
In certain embodiments, instead of using a known fixed pattern in divider protograph sections 1805, divider section 1805 conveys information and parity bits that have a bit error probability less than other bits in a codeword. For example, non-identical error protection methods can be used to create divider protograph sections as shown in the example shown in FIG. 19 . These methods include a) a lower modulation and coding scheme (MCS), ie a lower modulation order and/or a lower coding rate; b) a narrower analog beam; and c) fewer multiple input multiple output (MIMO) streams in the case of MIMO transmission.
20 illustrates a method of using stronger header protection to create divider protograph sections according to this disclosure. 21 illustrates an example of strengthening a portion of an SC-LDPC codeword using an iteration, or shortened then iterative process to transmit packet headers according to this disclosure. The embodiments shown in FIGS. 20 and 21 are for illustration only. Other embodiments may be used without departing from this disclosure.
In certain embodiments, each packet 2000 in a packet-based communication system such as WLAN IEEE 802.11 consists of a header 2005 and data (payload) 2010. It is common that headers should be protected more than data. In certain embodiments, for all packets belonging to a large chunk, such as one file transfer or one data stream, packets 2000 are encoded as one SC-LDPC codeword 2015. Header 2005 of packets 2000 will serve as divider protograph sections. Header 2005 may be better protected using low modulation order (QPSK), no puncturing, repetition, shortening, or a combination of these methods. In the example shown in Figure 21, the header information bits occupy one protography section for illustrative purposes only. In a real system, header information bits may occupy more than one protograph section, and padding may be required to fit the protograph sections.
In certain embodiments, header 2005 may be first encoded using an inner code, and then the information and parity bits of the inner code are encoded using an SC-LDPC code. In this case, SC-LDPC will be the outer code for the header section.
It is important to point out that since header 2005 contains information about how to demodulate and decode packet data 2010, header 2005 should be able to be decoded independently of data 2010 following header 2005. This can be done in several ways: one way is to ensure that the header occupies at least W protograph sections (the size of one decodable window), then while the sections carry repetition and parity bits. Putting header information bits into the first few sections. Alternatively, one can use the inner code to decode header 2005 and then use the recovered header to decode data 2010 as a divider protograph section.
In certain embodiments, the structure shown in FIGS. 20 and 21 encoding multiple packets 2000 into one using one SC-LDPC codeword indicates that there is a successive packet following the corresponding packet, or It can be signaled using a field in the packet header 2005 to indicate that the packet is not present. Alternatively, there may be higher level signaling such as MAC level messages that set up the SC-LDPC encoding structure such as number of jointly encoded packets, termination type, termination frequency, data modulation and coding scheme, etc.
22 illustrates an example of HARQ support using the SC-LDPC coding scheme according to the present disclosure. The embodiment of the SC-LDPC coding scheme 2200 shown in FIG. 22 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
In certain embodiments, the SC-LDPC coding scheme supports hybrid automatic repeat request (HARQ) in the following way: A receiver capable of recovering the information bits in these sections Decode protograph sections. If the decoder fails, 2205, the decoder requests retransmission of the related packet, then the decoder continues to buffer the received information and waits for the retransmitted information. Alternatively, the decoder can buffer at least the failed packet, all packets, or sections from the start of the failure, and start decoding the header of the next packet.
retransmission is
(1) retransmission of all bits associated with the failed packet (e.g. resulting in a combined chase at the receiver);
(2) Incremental redundancy retransmission by transmitting some or all of the punctured bits (if any) associated with that packet.
(3) Retransmission of all bits (or incremental redundancy) associated with the failed protograph section and all subsequent sections to the end of the failed packet.
(4) It may be a retransmission of all bits (or incremental redundancy) that relate only to the failing protograph section, or to several sections after that.
Retransmission method 3 and retransmission method 4 above require the receiver to feed back information about the failure of the protograph section.
Code family design: shortening versus puncturing
In this section, the problem of designing a family of SC-LDPC codes supporting multiple code rates is addressed. The following two candidate approaches are considered: 1) Design an SC-LDPC ensemble with a low code rate, then puncture it to obtain codes with a higher code rate. This approach is similar to that used with round codes, except that the puncturing here is done at the protograph section level rather than at the bit level, i.e., if the VN type in the SC-LDPC code is punctured, then All Z VNs of that type in the lifted SC-LDPC code will be punctured. 2) After designing the SC-LDPC code ensemble with high code rate, shorten it to codes with lower code rate. This approach is similar to the method used in designing the AR4JA LDPC code family discussed in Ref. 19.
Embodiments of this disclosure illustrate and compare two code family design methods by designing and simulating two example families of SC-LDPC codes (one per approach). And the results so presented are intended to help understand how these two approaches compare in terms of BER performance and convergence speed and how that translates into computational complexity. Also, only codes with a regular degree distribution (regular except for the ends) are considered in this disclosure. Regular SC-LDPC codes have good decoding thresholds comparable to optimized irregular designs.
23 is a puncturing matrix [1, 0, 1; 1, 1, 0] to show an example of puncturing a (3, 6, L) SC-LDPC ensemble at rate-3/4. The embodiment of the punctured code structure 2200 shown in FIG. 23 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
In the first code family, (3, 6, 720) SC-LDPC code 1600 has the lowest rate (˜rate-1/2). SC-LDPC code 1600 is a puncturing pattern [1, 0; 1, 1], [1, 0, 1; 1, 1, 0], or [1, 0, 1, 0, 1; 1, 1, 0, 1, 0] is punctured at "approximately" rate-2/3, rate-3/4, or rate-5/6. An example of puncturing (3, 6, 720) SC-LDPC code 1600 at rate-3/4 is given in FIG. 23 , where gray circles 2305 indicate punctured VNs and white circles 2310 transmit displayed VNs.
24 is a rate-5/6 (3,18) LDPC code protograph that can be shortened to rate-4/5, rate-3/4, rate-2/3 or rate-1/2 according to the present disclosure. show The embodiment of protograph 2400 shown in FIG. 24 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
In the second code group, a (3, 18, L) SC-LDPC code ensemble is designed based on the protograph 2400 of FIG. 24 . Then, this code is lifted to a time-varying quasi-cyclic SC-LDPC code with period 3 using Z=112 cyclic permutation matrices. A parity check matrix 2500 for the designed code is shown in FIG. 25 . The permutation matrices were chosen in a hierarchical way: first, permutation matrices lifting i ₁ 2405 and p ₁ 2410, 5th and 6th columns 2505 were chosen to maximize the sur of the first 9 protograph sections of the code, Here all other permutations are set as ZxZ matrices with all elements zero. Then, permutation matrices were added lifting i ₂ 2415, i ₃ 2420, i ₄ 2425, and finally i ₅ 2430 to maximize the GUS. To shorten this code to a rate-4/5 code, all first column 2510 were deleted (i.e. set all VNs of i5 to '0' and then delete them before transmission). To shorten the code to a rate-3/4 code, all first column 2510 and second column 2515 are deleted, etc., the code can be further shortened to obtain a rate-2/3 code and a rate-1/2 code. there is.
In the punctured code group, the number of information bits in a codeword is fixed and equal to 80416 bits. In the shortened code family, the number L of protograph copies is adjusted for each code rate to maintain 80416 number of information bits in the codeword. Thus, L=720, L=360, L=240, and L=144 for Rate-1/2, Rate-2/3, Rate-3/4, and Rate-5/6, respectively. Also, trying to keep a fair comparison, the size of the decoding window is varied such that the number of VNs within the decoding window is 30. That is, W=15 for all codes in the punctured code group, and W=1/2, rate-2/3, rate-3/4, and rate-5/6 respectively in the shortened code group. 15, W = 10, W = 7 and W = 5 (for rate-3/4, W should be 7.5, but was approximated to 7).
The results of FER and average number of iterations in Figs. 26 and 27 show that the rate-1/2 codes of the punctured code group and the shortened code group have similar performance. Rate-2/3 codes from the shortened code family perform slightly better than rate-2/3 codes from the punctured code family. The rate-3/4 codes of the shortened code family outperform the rate-3/4 codes of the punctured code family by 0.6 dB in FER performance and provide an average reduction of more than 12 repetitions per VN at any given SNR point. do. The rate-5/6 codes of the shortened code family outperform the rate-5/6 of the punctured code family by 0.9 dB in terms of the FER designed so that the shortened code family performs better than the punctured code family.
Codes in the shortened code family have a low average number of iterations per VN, but this does not necessarily reduce computational complexity. It should be noted that the codes of the shortened code family have CNs of higher order than the codes of the punctured code family, and this should be taken into account in the computational complexity comparison. For computational complexity, a CN of degree d _c (per iteration) requires two additional operations for scaling: 3(d _c- 2) comparison operations to find the minimum and 2d _c- 1 operations to compute the sign. Assume the use of a scaled Min-Sum decoder requiring an XOR operation. Also, a VN of degree d _v requires 2d _{v -} 1 additional operations per iteration. In addition, assuming that one addition operation, one comparison operation, or eight XOR operations correspond to each other, the shortened/punctured complexity ratio is XOR (exclusive-or) for each step of decoding the VN of the punctured code group. It is defined as the number of XOR operations per step of decoding the VN of the shortened code group divided by the number of operations. Also, the comparison can be made at the same SNR point or the same FER performance. The complexity ratios are summarized in Table 1.
Embodiments of the present disclosure provide an early stopping rule for window decoding of SC-LDPC codes. The early stopping rule is based on partial syndrome checking that only performs XOR operations. In addition, embodiments of the present disclosure propose a zigzag window decoder capable of pushing back information at the end of divergence. The proposed zigzag window decoder with the proposed early stopping rule has similar FER performance to the full-block decoder and reduces the average number of iterations per VN from 55 to 30 for the full-block decoder at FER=1e-2.
Two examples of code families supporting different rates through puncturing or shortening were compared. The results show that the shortened code family performs better than the punctured code family and has lower computational complexity, especially for high rate codes.
28 illustrates exemplary SC-LDPC code families based on shortening according to the present disclosure. The embodiment of the SC-LDPC code families 2800 shown in FIG. 28 is for illustration only. Other embodiments may be used without departing from the scope of the present disclosure.
28 shows three protograph sections of the parity check matrix for the code with the highest code rate in the group, where ZZ denotes a ZxZ matrix with all elements zero, and the value A(i,j) is ( according to the lifting factor Z) in the i-th row and j-th column of the matrices below.
When Z = 112, an example of a lifting matrix is shown in the table below.

When Z = 42, an example of a lifting matrix is shown in the table below.

When Z = 27, an example of a lifting matrix is shown in the table below.

When Z = 24, an example of a lifting matrix is shown in the table below.

29 illustrates an operating process of a receiving node according to the present disclosure. A flow diagram depicts a sequential series of steps, but, unless explicitly stated otherwise, in a specific order of performance, in a redundant manner, or in a non-concurrent, sequential performance of steps or parts thereof, or exclusively without intervening or occurring intervening steps. No inference should be drawn from the sequence as to the performance of the steps shown. The process shown in the illustrated example is implemented at a receiving node, for example a base station or terminal.
Referring to FIG. 29 , in step 2901, the receiving node receives signals including at least one codeword based on the SC-LDPC code from the transmitting node. At least one codeword is generated by a transmitting node using an SC-LDPC code. At least one codeword comprises a packet comprising a header and a payload, and the header is configured as a divider protograph section for dividing protograph sections of one or more SC-LDPC codes.
Then, in step 2903, the receiving node decodes at least one codeword using a sliding window. Here, the sliding window selectively moves forward or backward. The sliding window moves backward based on the syndrome of one or more CNs in the current sliding window. In particular, the receiving node repeatedly performs decoding calculations until the stopping rule is satisfied. A stopping rule is defined as a function of the syndrome of one or more CNs in the current sliding window.
The SC-LDPC coding scheme supports HARQ. In this case, the receiving node decodes the protograph sections of the SC-LDPC code as long as the decoder is able to recover the information bits in the protograph sections, requests retransmission of the related packet, and retransmits the related packet in response to the decoder failure. Continue buffering received information while waiting for In another embodiment, the receiving node buffers at least the failed packet, all packets, or sections from the start of the failure and, in response to the decoder failure, begins decoding the header of the next packet. Retransmission of all bits associated with the failed packet Retransmission, incremental redundancy retransmission, including transmission of some or all of the punctured bits associated with the packet, retransmission of the failed protograph section and all subsequent sections to the end of the failed packet and all associated bits or incremental redundancy, and failed protograph Either retransmission of all bits or incremental redundancy involving only the section or several sections after the failed protograph section. Also, the receiving node may reduce the rate of the SC-LDPC code by shortening operation.
To assist readers of the Patent Office and any patents published herein in interpreting the appended claims, applicants request that the words "means for" or "steps for" not be expressly used in any particular claim. It should be noted that none of the appended claims or claim elements are intended to apply 35U.SC §112(f) unless otherwise specified. "mechanism", "module", "device", "unit", "component", "element", "member", "apparatus", "machine", "system", "processor", or Use of all other terms, including but not limited to "controller", is understood by Applicants to refer to structures known to those skilled in the art, and is not intended to apply 35U.SC §112(f).
Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications as fall within the scope of the appended claims.

Claims (15)

In the receiving node device in a wireless communication system,
at least one transceiver; and
including at least one processor functionally coupled to the at least one transceiver;
The at least one processor receives signals including at least one codeword based on a spatially coupled low density parity check (SC-LDPC) code from a transmission node, and uses a sliding window. to control decoding of the at least one codeword;
The sliding window moves in a forward or reverse direction,
The at least one codeword includes a packet including a header and a payload,
The header is configured as a divider protograph section to divide protograph sections of one or more SC-LDPC codes, and is first encoded using an inner code, information of the inner code and parity to check the correctness of the information. Bits are encoded using the SC-LDPC code,
constructing the header so that it occupies a plurality of protograph sections, placing header information bits in the first few sections, while subsequent sections repeat and carry the parity bits, decoding the header and then using the decoded header as a divider protograph section and after using the inner code to decode the packet data independently of the packet data following the header.
According to claim 1,
The sliding window moves in the reverse direction based on the syndrome of one or more check nodes (check nodes, CNs) within the current sliding window.
According to claim 1,
Controls the at least one processor to repeatedly perform decoding calculations until a stopping rule is satisfied;
wherein the stopping rule is defined as a function of a syndrome of one or more check nodes (CN) within a current sliding window.
According to claim 3,
The at least one processor checks a partial syndrome for the one or more CNs, and if the syndrome check passes or the maximum number of iterations is reached, variable nodes (VNs) in each protograph section are checked. A device for outputting a decision and controlling to determine whether the stopping rule is satisfied by updating the position of the sliding window.
According to claim 1,
The forward direction is a direction in which the sliding window proceeds to the right by at least one protograph section,
wherein the reverse direction is a direction in which the sliding window proceeds to the left by the at least one protograph section.
delete According to claim 1,
or the header is protected using at least one of low modulation order, no puncturing, repetition, and shortening;
At least one of header information bits containing information about demodulation and decoding of packet data occupy one or more protograph sections.
delete According to claim 1,
Multiple packets are encoded into one using one SC-LDPC codeword, and a field in the header is used to indicate either that a continuation packet follows the packet or that the continuation packet does not follow the packet. device that is signaled by
According to claim 1,
The SC-LDPC coding scheme supports hybrid automatic repeat request (HARQ),
the at least one processor decodes the protograph sections of an SC-LDPC code as long as it can recover the header information bits in the protograph sections, and in response to a decoding failure, requests retransmission of a related packet; A device for controlling to continue buffering received information or at least buffer a failed packet, all packets, or sections from the beginning of a failure while waiting for the retransmitted related packet, and start decoding the header of the next packet.
11. The apparatus of claim 10, wherein the at least one processor is further configured to reduce a rate of the SC-LDPC code by a shortening operation.
11. The method of claim 10, wherein the retransmission includes retransmission of all bits associated with the failed packet, incremental redundant retransmission including transmission of some or all of the punctured bits associated with the packet, a failed protograph section, and the failed packet. One of retransmission of all bits or incremental redundancy related to all following sections to the end, and retransmission of all bits or incremental redundancy related only to the failed protograph section or several sections after the failed protograph section.
In the method of operating a receiving node in a wireless communication system,
Receiving signals including at least one codeword based on a spatially coupled low density parity check (SC-LDPC) code from a transmitting node;
decoding the at least one codeword using a sliding window;
The sliding window moves in a forward or reverse direction,
The at least one codeword includes a packet including a header and a payload,
The header is configured as a divider protograph section to divide protograph sections of one or more SC-LDPC codes, and is first encoded using an inner code, information of the inner code and parity to check the correctness of the information. Bits are encoded using the SC-LDPC code,
constructing the header so that it occupies a plurality of protograph sections, placing header information bits in the first few sections, while subsequent sections repeat and carry the parity bits, decoding the header and then using the decoded header as a divider protograph section and after using the inner code to decode the packet data independently of the packet data following the header.
According to claim 13,
The sliding window is moved in the reverse direction based on the syndrome of one or more check nodes (check node, CN) within the current sliding window.
According to claim 13,
Iteratively performing decoding calculations until the stopping rule is satisfied;
wherein the stopping rule is defined as a function of the syndrome of one or more check nodes (CN) within the current sliding window.

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